HD6417041AVF16V Renesas Electronics America, HD6417041AVF16V Datasheet - Page 433

• Manufacturer Part Number: HD6417041AVF16V
• Description: IC SUPERH MCU ROMLESS 144QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7040r

Specifications of HD6417041AVF16V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 28.7MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

7.2.2
Relationship between Load Instructions and the Instructions that Follow: Instructions that
involve loading from memory return data to the destination register during the WB/DSP stage,
which comes at the end of the pipeline. The WB/DSP stage of such a load instruction (load
instruction 1) will thus not have ended before after the EX stage of the instruction that
immediately follows it (instruction 2) begins.
When instruction 2 uses the same destination register as load instruction 1, the contents of that
register will not be ready, so any slot containing the MA of instruction 1 and EX of instruction 2
will split. When the destination register of load instruction 1 is the same as the destination, not the
source, of instruction 2 it will still split.
When the destination of load instruction 1 is the status register (SR) and the flag in it is fetched by
instruction 2 (as ADDC does), a split occurs. No split occurs, however, in the following cases:
The number of cycles in the slot generated by the split is the number of MA cycles plus the
number of IF (or if) cycles, as shown in figure 7.9. This means the execution speed will be
lowered if the instruction that will use the results of the load instruction is placed immediately
after the load instruction. The instruction that uses the result of the load instruction will not slow
down the program if placed one or more instructions after the load instruction.
When data is loaded to a register in the previous instruction and the following memory access
instruction uses that register as an address pointer, the memory access is extended until the data
load of the MA stage of the previous instruction ends.
Load instruction 1 (MOV @Ra,Rb)
When instruction 2 is a load instruction and its destination is the same as that of load
instruction 1
When instruction 2 is MAC @Rm+,@Rn+ and the destinations of Rm and load instruction 1
were the same
Contention when the Previous Instruction’s Destination Register Is Used
Instruction 2 (ADD Rb,Rc)
Figure 7.9 Effects of Memory Load Instructions on the Pipeline (1)
Instruction 3
Instruction 4
IF
ID
IF
EX
ID
IF
MA
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Rev. 5.00 Jun 30, 2004 page 417 of 512
W/D
EX
ID
IF
EX
ID
Section 7 Pipeline Operation
MA
EX
REJ09B0171-0500O
W/D
MA W/D
: Slot