HD6417041AVF16V Renesas Electronics America, HD6417041AVF16V Datasheet - Page 434

• Manufacturer Part Number: HD6417041AVF16V
• Description: IC SUPERH MCU ROMLESS 144QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7040r

Specifications of HD6417041AVF16V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 28.7MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 7 Pipeline Operation
In the DSP unit, all operation instructions are executed in the WB/DSP stage, so transfers and
operations do not contend. When the destination of the previous MOV instruction is used as the
address pointer for the following instruction, however, contention can occur.
Load instruction 1 (MOVX @Ra,X0)
Relationship between Data Operation Instructions and Store Instructions: When DSP
operations are executed by the DSP unit and the results are stored in memory by the next
instruction, contention occurs just as with memory load instructions. In such cases, the data store
of the MA stage of the following instruction is extended until the data operation of the WB/DSP
stage of the previous instruction ends.
Since the operation is executed in the EX stage by the CPU core, however, no stall cycle is
produced.
Figure 7.12 shows the relationship between DSP unit data operation instructions and store
instructions; figure 7.13 shows the relationship to the CPU core.
Rev. 5.00 Jun 30, 2004 page 418 of 512
REJ09B0171-0500O
Load instruction 1 (MOV @Ra,Rb)
Instruction 2 (PADD X0,Y0,A0)
Figure 7.11 Effects of Memory Load Instructions in the DSP Unit on the Pipeline
Instruction 2 (MOV @Rb,Rc)
Figure 7.10 Effects of Memory Load Instructions on the Pipeline (2)
Instruction 3
Instruction 4
Instruction 3
Instruction 4
IF
IF
ID
IF
ID
IF
EX
ID
IF
EX
ID
IF
MA
EX
ID
IF
MA
—
—
W/D
MA W/D
EX
ID
W/D
EX
ID
IF
MA
EX
MA W/D
EX
ID
W/D
MA W/D
MA
EX
W/D
MA W/D
: Slot
: Slot