HD6417041AVF16V Renesas Electronics America, HD6417041AVF16V Datasheet - Page 436

IC SUPERH MCU ROMLESS 144QFP

HD6417041AVF16V

Manufacturer Part Number
HD6417041AVF16V
Description
IC SUPERH MCU ROMLESS 144QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7040r
Datasheets

Specifications of HD6417041AVF16V

Core Processor
SH-2
Core Size
32-Bit
Speed
28.7MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417041AVF16V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 7 Pipeline Operation
Relationship between MAC and STS Instructions: The MAC.W instruction has two MA stages
and two mm (multiplier access) stages. When an STS instruction that stores a MACL or MACH
register in the Rn register comes after a MAC.W instruction, the MA stage of the STS instruction
is executed after the mm stage of the MAC.W instruction ends. Likewise, when an STS instruction
that stores a MACL or MACH register in memory comes after a MAC.W instruction, the MA
stage of the STS instruction is executed after the mm stage of the MAC.W instruction ends.
Instruction 1 (MAC.W @Ra+,@Rb+)
7.2.3
Instructions that access multiplier type instructions (Multiply/Accumulate instructions and
multiplication instructions) or the multiply and accumulate calculation registers (MACH and
MACL) contend with multiplier accesses.
In multiplier type instructions, the multiplier operates for either four cycles (for double-length 64
bits instructions) or two cycles (single-length 32 bit instructions) after the MA ends, regardless of
the slot. When the MA (or the second MA, if there are two) of a multiplier type instruction
(Multiply/Accumulate instructions and multiplication instructions) contends with the multiplier
Rev. 5.00 Jun 30, 2004 page 420 of 512
REJ09B0171-0500O
STS.L MAC.L memory
Instruction 1 (MOVS.L @R4,Ds)
Instruction 2 (MOVS.L Ds,@R5)
Figure 7.17 Example of Multiplier Access Contention—MAC.L and STS.L Instructions
Figure 7.15 Relationship between Load and Store Instructions in the DSP Unit
Instruction 2 (STS MACL,Rc)
Next instruction
Multiplier Access Contention
Figure 7.16 Relationship between MAC.W and STS Instructions
MAC.L
Slot
Instruction 3
Instruction 4
Instruction 3
IF
ID
IF
IF
EX
if
ID
IF
MA
ID
IF
ID
IF
EX
ID
IF
MA
EX
ID
EX
MA
EX
ID
IF
mm
MA
M
ID
if
W/D
MA
EX
ID
mm
MA mm mm
EX
ID
W/D
MA W/D
EX
mm mm
MA W/D
A
MA W/D
MA
EX
EX
MA W/D
: Slot
: Slot

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