HD6417041AVF16V Renesas Electronics America, HD6417041AVF16V Datasheet - Page 442

• Manufacturer Part Number: HD6417041AVF16V
• Description: IC SUPERH MCU ROMLESS 144QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7040r

Specifications of HD6417041AVF16V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 28.7MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 7 Pipeline Operation
7.4
This section describes the operation of the instruction pipelines. By combining these with the rules
described so far, the way pipelines flow in a program and the number of instruction execution
cycles can be calculated.
In the following figures, “Instruction A” refers to the instruction being discussed. When “IF” is
written in the instruction fetch stage, it may refer to either “IF” or “if”. When there is contention
between IF and MA, the slot will split, but the manner of the split is not discussed in the tables,
with a few exceptions. When a slot has split, see section 7.2.1, Contention between Instruction
Fetch (IF) and Memory Access (MA). Base your response on the rules for pipeline operation given
there.
Table 7.2 shows the number of instruction stages and number of execution cycles as follows:
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REJ09B0171-0500O
Type: Given by function
Category: Categorized by differences in instruction operation
Stages: The number of stages in the instruction
Cycles: The number of execution cycles when there is no contention
Contention: Indicates the contention that occurs
Instructions: Gives a mnemonic for the instruction concerned
Operation of Instruction Pipelines