HD6417041AVF16V Renesas Electronics America, HD6417041AVF16V Datasheet - Page 481

• Manufacturer Part Number: HD6417041AVF16V
• Description: IC SUPERH MCU ROMLESS 144QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7040r

Specifications of HD6417041AVF16V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 28.7MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Multiplication Instructions (SH-1 CPU): Include the following instruction types:
The pipeline has six stages: IF, ID, EX, MA, mm, and mm. The MA accesses the multiplier. mm
indicates that the multiplier is operating. mm operates for three cycles after the MA ends,
regardless of slot. The MA of the MULS.W instruction, when it contends with IF, splits the slot as
described in Section 7.2.1, Contention between Instruction Fetch (IF) and Memory Access (MA).
When an instruction that does not use the multiplier comes after the MULS.W instruction, the
MULS.W instruction may be considered to be a four-stage pipeline instruction of IF, ID, EX, and
MA. In such cases, it operates like a normal pipeline. When an instruction that uses the multiplier
comes after the MULS.W instruction, however, contention occurs with the multiplier, so operation
is different from normal.
This occurs in the following cases:
1. When a MAC.W instruction is located immediately after a MULS.W instruction
2. When a MULS.W instruction is located immediately after another MULS.W instruction
3. When an STS (register) instruction is located immediately after a MULS.W instruction
4. When an STS.L (memory) instruction is located immediately after a MULS.W instruction
5. When an LDS (register) instruction is located immediately after a MULS.W instruction
6. When an LDS.L (memory) instruction is located immediately after a MULS.W instruction
MULS.W
MULU.W
Third instruction
Next instruction
Rm, Rn
Rm, Rn
Instruction A
Figure 7.54 Multiplication Instruction Pipeline
......
IF
ID
IF
EX
ID
IF
MA mm mm
EX
ID
Rev. 5.00 Jun 30, 2004 page 465 of 512
MA
EX
WB
MA
Section 7 Pipeline Operation
WB
REJ09B0171-0500O
: Slot