HD6417041AVF16V Renesas Electronics America, HD6417041AVF16V Datasheet - Page 51

• Manufacturer Part Number: HD6417041AVF16V
• Description: IC SUPERH MCU ROMLESS 144QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7040r

Specifications of HD6417041AVF16V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 28.7MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 4 Instruction Features
4.4
DSP
DSP operations and data transfers are listed below:
ALU Fixed Decimal Point Operations: These are fixed decimal point operations with either 40-
bit (with guard bits) or 32-bit (with no guard bits) fixed decimal point data. These include
addition, subtraction, and comparison instructions.
ALU Integer Operations: These are integer arithmetic operations with either 24-bit (with guard
bits) or 16-bit (with no guard bits) integer data. They include increment and decrement
instructions.
ALU Logical Operations: These are logical operations with 16-bit logical data. They include
AND, OR, and exclusive OR.
Fixed Decimal Point Multiplication: This is fixed decimal point multiplication (arithmetic
operation) of the top 16 bits of fixed decimal point data. Condition bits such as the DC bit are not
updated.
Shift Operations: These are arithmetic and logical shift operations. Arithmetic shift operations
are arithmetic shifts of 40 bits (with guard bits) or 32 bits (with no guard bits) of fixed decimal
point data. Logical shift operations are logical operations on 16 bits of logical data. The amount of
the arithmetic shift operation is –32 to +32 (negative for right shifts, positive for left shifts); for
logical shifts, the amount is –16 to +16.
MSB Detection Instruction: This operation finds the amount of the shift to normalize the data. It
finds the position of the MSB bit in either 40-bit (with guard bits) or 32-bit (with no guard bits)
fixed decimal point data as either 24 bits (with guard bits) or 16 bits (with no guard bits) integer
data.
Rounding Operation: Rounds 40-bit fixed decimal point data (with guard bits) to 24 bits or 32-
bit (with no guard bits) fixed decimal point data to 16 bits.
Data Transfers: Data transfers consist of X and Y data transfers, which load or store 16-bit data
to and from X and Y memory, and single data transfers, which load and store 16- or 32-bit data
from all memories. Two X and Y data transfers can be processed in parallel. Condition bits such
as the DC bit are not updated.
The operation instructions include both conditional operation instructions and instructions that are
conditionally executed depending on the DC bit. Condition bits such as the DC bit are not updated
by conditional instructions. Their settings vary for arithmetic operations, logical operations,
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