HD6417041AVF16V Renesas Electronics America, HD6417041AVF16V Datasheet - Page 512

IC SUPERH MCU ROMLESS 144QFP

HD6417041AVF16V

Manufacturer Part Number
HD6417041AVF16V
Description
IC SUPERH MCU ROMLESS 144QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7040r
Datasheets

Specifications of HD6417041AVF16V

Core Processor
SH-2
Core Size
32-Bit
Speed
28.7MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417041AVF16V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 7 Pipeline Operation
MAC
instruction types:
The pipeline has four stages: IF, ID, EX, and MA (figure 7.91). MA is a stage for accessing the
memory and multiplier. MA contends with IF. This makes it the same as ordinary store
instructions. Since the multiplier does contend with the MA, however, the items noted for the
multiplication, Multiply/Accumulate, double-length multiplication, and double-length
multiply/accumulate instructions apply.
RTE Instruction (Common): RTE
The pipeline has five stages: IF, ID, EX, MA, and MA (figure 7.92). The MAs do not contend
with IF. RTE is a delayed branch instruction. The ID of the delay slot instruction is stalled 3 slots.
The IF of the branch destination instruction starts from the slot following the MA of the RTE.
Rev. 5.00 Jun 30, 2004 page 496 of 512
REJ09B0171-0500O
STS.L
STS.L
STS.L
STS.L
STS.L
STS.L
STS.L
STS.L
Memory Transfer Instructions (Common, or SH-DSP): Include the following
Branch destination
MACH, @–Rn
MACL, @–Rn
DSR,@–Rn (SH-DSP)
A0,@–Rn (SH-DSP)
X0,@–Rn (SH-DSP)
X1,@–Rn (SH-DSP)
Y0,@–Rn (SH-DSP)
Y1,@–Rn (SH-DSP)
Third instruction in series
Figure 7.91 MAC
Delay slot
RTE
Next instruction
.....
Instruction A
Figure 7.92 RTE Instruction Pipeline
IF
.....
ID
IF
Memory Transfer Instruction Pipeline
EX
IF
MA
ID
IF
MA
EX
ID
IF
MA
EX
ID
ID
IF
.....
EX
EX
ID
.....
.....
EX
: Slot
.....
: Slot

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