HD6417041AVF16V Renesas Electronics America, HD6417041AVF16V Datasheet - Page 515

• Manufacturer Part Number: HD6417041AVF16V
• Description: IC SUPERH MCU ROMLESS 144QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7040r

Specifications of HD6417041AVF16V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 28.7MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 7 Pipeline Operation
Illegal Instruction Exception Processing (Common): The illegal instruction is received during
the ID stage of the instruction and everything after the ID stage is replaced by the illegal
instruction exception processing sequence. The pipeline has nine stages: IF, ID, EX, EX, MA,
MA, MA, EX, and EX (figure 7.97). Illegal instruction exception processing is not a delayed
branch. In illegal instruction exception processing, overrun fetches (IF) occur. Whether there is an
IF only in the next instruction or in the one after that as well depends on the instruction that was to
be executed. In branch destination instructions, the IF starts from the slot that has the final EX in
the illegal instruction exception processing.
Illegal instruction exception processing is caused by ordinary illegal instructions and by
instructions with illegal slots. When undefined code placed somewhere other than the slot directly
after the delayed branch instruction (called the delay slot) is decoded, ordinary illegal instruction
exception processing occurs. When undefined code placed in the delay slot is decoded or when an
instruction placed in the delay slot to rewrite the program counter is decoded, an illegal slot
instruction occurs.
: Slot
Interrupt
IF
ID
EX
EX MA MA MA EX EX
Next instruction
IF
IF)
IF
ID
EX
Branch destination
......
IF
ID
Figure 7.97 Illegal Instruction Exception Processing Pipeline
Rev. 5.00 Jun 30, 2004 page 499 of 512
REJ09B0171-0500O