HD6417041AVF16V Renesas Electronics America, HD6417041AVF16V Datasheet - Page 52

IC SUPERH MCU ROMLESS 144QFP

HD6417041AVF16V

Manufacturer Part Number
HD6417041AVF16V
Description
IC SUPERH MCU ROMLESS 144QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7040r
Datasheets

Specifications of HD6417041AVF16V

Core Processor
SH-2
Core Size
32-Bit
Speed
28.7MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417041AVF16V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 4 Instruction Features
arithmetic shifts, and logical shifts. or MSB detection instructions and rounding instructions, set
the condition bits like for arithmetic operations.
Arithmetic operations include overflow preventing instructions (saturation operations). When
saturation operation is specified with the S bit in the SR register, the maximum (positive) or
minimum (negative) value is stored when the result of operation overflows.
4.5
The DSP command performs two different types of memory accesses. One uses the X and Y data
transfer instructions (MOVX.W and MOVY.W) while the other uses the single data transfer
instructions (MOVS.W and MOVS.L). Data addressing for these two types of instructions also
differs. Table 4.9 summarizes the data transfer instructions.
Table 4.9
Item
Address registers
Index registers
Addressing
Modulo addressing
Data buses
Data length
Bus contention
Memory
Source registers
Destination registers
Rev. 5.00 Jun 30, 2004 page 36 of 512
REJ09B0171-0500O
DSP Data Addressing
Summary of Data Transfer Instructions
X and Y Data Transfer
Processing (MOVX.W and
MOVY.W)
Ax: R4, R5; Ay: R6, R7
Ix: R8; Iy: R9
Nop/Inc(+2)/Index addition:
Post-increment
Available
XDB, YDB
16 bits (word)
None
X and Y data memories
Da: A0, A1
Dx: X0/X1; Dy: Y0/Y1
Single Data Transfer Processing
(MOVS.W and MOVS.L)
As: R2, R3, R4, R5
Is: R8
Nop/Inc(+2, +4)/Index addition:
Post-increment
Dec(–2, –4): Pre-decrement
Not available
IDB
16 or 32 bits (word or longword)
Occurs
All memory spaces
Ds: A0/A1, M0/M1, X0/X1, Y0/Y1,
A0G, A1G
Ds: A0/A1, M0/M1, X0/X1, Y0/Y1,
A0G, A1G

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