HD6417041AVF16V Renesas Electronics America, HD6417041AVF16V Datasheet - Page 65

IC SUPERH MCU ROMLESS 144QFP

HD6417041AVF16V

Manufacturer Part Number
HD6417041AVF16V
Description
IC SUPERH MCU ROMLESS 144QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7040r
Datasheets

Specifications of HD6417041AVF16V

Core Processor
SH-2
Core Size
32-Bit
Speed
28.7MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417041AVF16V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Figure 4.5 Field B ALU Operation Instructions and Multiplication Instructions (cont)
Notes: 1.
instructions
Conditional
Category
operand
three
A
2.
3.
(if cc)*
[if cc]: DCT (DC bit true), DCF (DC bit false), or none (unconditional
instruction)
Unconditional
System reserved code
(if cc) PXOR Sx, Sy, Dz
(if cc) PSHA Sx, Sy, Dz
(if cc) PSUB Sx, Sy, Dz
(if cc) PSTS MACH, Dz
(if cc) PLDS Dz, MACH
(if cc) PADD Sx, Sy, Dz
(if cc) PAND Sx, Sy, Dz
(if cc) PSTS MACL, Dz
(if cc) PLDS Dz, MACL
(if cc) POR Sx, Sy, Dz
(if cc) PDMSB Sx, Dz
(if cc) PCOPY Sx, Dz
(if cc) PDMSB Sy, Dz
(if cc) PCOPY Sy, Dz
(if cc) PNEG Sx, Dz
(if cc) PDEC Sx, Dz
(if cc) PDEC Sy, Dz
(if cc) PNEG Sy, Dz
(if cc) PINC Sx, Dz
(if cc) PINC Sy, Dz
(if cc) PCLR Dz
1
Mnemonic
Reserved
Reserved
Reserved
Reserved
Reserved
PSHL Sx, Sy, Dz
B
31–27
1
1
26
0
C
Field A
25–16
1
15
1 1
1
14 13 12
0
Rev. 5.00 Jun 30, 2004 page 49 of 512
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
11
0
0
1
1
1
1
0*
3
10 9
0
1
0
1
0
1
Section 4 Instruction Features
10:DCT
11:DCF
0
0
if cc
if cc
01*
8 7 6 5 4 3 2 1 0
2
0
0
0:X0
1:X1
2:Y0
3:Y1
Sx
REJ09B0171-0500O
E
2:M0
3:M1
0:Y0
1:Y1
Sy
D:(*
F:(*
0:(*
1:(*
2:(*
3:(*
4:(*
6:(*
C:M0
E:M1
A:Y0
B:Y1
5:A1
7:A0
8:X0
9:X1
Dz
1
1
1
1
1
1
1
1
)
)
)
)
)
)
)
)

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