HD6417041AVF16V Renesas Electronics America, HD6417041AVF16V Datasheet - Page 70

• Manufacturer Part Number: HD6417041AVF16V
• Description: IC SUPERH MCU ROMLESS 144QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7040r

Specifications of HD6417041AVF16V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 28.7MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 4 Instruction Features
Zero Mode: CS2–CS0 = 010: The DC bit indicates whether the operation result is zero. When it
is, the DC bit is 1. When the operation result is nonzero, the DC bit is 0. In this mode, the DC bit
has the same value as the condition bit Z.
Overflow Mode: CS2–CS0 = 011: The DC bit indicates whether the operation result has caused
an overflow. When the operation result without the guard bits has exceeded the bounds of the
destination register, the DC bit is set to 1. The DC bit considers there to be no guard bits, which
makes it an overflow even when there are guard bits. This means that the DC bit is always set to 1
when large numbers use guard bits. In this mode, the DC bit has the same value as the condition
bit V. Figure 4.10 shows an example of distinguishing overflows.
Signed Greater Than Mode: CS2–CS0 = 100: The DC bit indicates whether the source 1 data
(signed) is greater than the source 2 data (signed) in the result of a comparison instruction PCMP.
For that reason, the PCMP instruction is executed before checking the DC bit in this mode. When
the source 1 data is larger than the source 2 data, the result of the comparison is positive, so this
mode becomes similar to the negative mode. When the source 1 data is larger than the source 2
data and the bounds of the destination operand are exceeded, however, the sign of the result of the
comparison becomes negative. The DC bit is updated. In this mode, the DC bit has the same value
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Example 1: Negative
Example 1: Overflow
+)
+)
1100 0000 0000 0000 0000 0000
0000 0000 0000 0000 0000 0001
1100 0000 0000 0000 0000 0001
1111 1111 1111 1111 1111 1111
1111 1111 1000 0000 0000 0000
1111 1111 0111 1111 1111 1111
Guard bits
Guard bits
Sign bit
Overflow detection range
Figure 4.9 Distinguishing Negative and Positive
Figure 4.10 Distinguishing Overflows
Example 2: Positive
Example 2: No overflow
+)
+)
0011 0000 0000 0000 0000 0000
0000 0000 1000 0000 0000 0001
0011 0000 1000 0000 0000 0001
1111 1111 1111 1111 1111 1111
1111 1111 1000 0000 0000 0001
1111 1111 1000 0000 0000 0000
Guard bits
Guard bits
Sign bit
Overflow detection range