HD6417041AVF16V Renesas Electronics America, HD6417041AVF16V Datasheet - Page 79

• Manufacturer Part Number: HD6417041AVF16V
• Description: IC SUPERH MCU ROMLESS 144QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7040r

Specifications of HD6417041AVF16V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 28.7MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

4.11.1
Function: ALU arithmetic shift operations basically work with a 32-bit unit to which 8 guard bits
are added for a total of 40 bits. ALU fixed decimal point operations are basically performed
between registers. When the source operand has no guard bits, the register’s sign bit is copied to
the guard bits. When the destination operand has no guard bits, the lower 32 bits of the operation
result are stored in the destination register.
In arithmetic shifts, all bits of the source 1 operand and destination operand are valid. The source 2
operand, which specifies the shift amount, is integer data. The source 2 operand is specified as a
register or immediate operand. The valid amount of shift is –32 to +32. Negative values are shifts
to the right; positive values are shifts to the left. Between –64 and +63 can be specified for the
source 2 operand, but only –32 to +32 is valid. When an invalid number is specified, the results
cannot be guaranteed. When an immediate value is specified for the shift amount, the source 1
operand must be the same as the destination operand. The action of the operation is the same as for
fixed decimal point operations and is executed in the DSP stage (the last stage) of the pipeline.
Whenever an arithmetic shift operation is executed, the DSR register’s DC, N, Z, V, and GT bits
are basically updated by the operation result. This is the same as for ALU fixed decimal point
operations. For conditional instructions, condition bits are not updated even when the specified
condition is achieved and the instruction executed. For unconditional instructions, the bits are
always updated according to the operation result.
Figure 4.14 shows the arithmetic shift operation flowchart.
Shift amount data
(source 2)
7g
Arithmetic Shift Operations
Shift out
0g 31
Left shift
Figure 4.14 Arithmetic Shift Operation Flowchart
7g 0g 31 23 22 16 15
16 15
0
+32 to –32
6
imm1
0
Dz
0
0
< 0
7g 0g 31
(Copy MSB)
0
Rev. 5.00 Jun 30, 2004 page 63 of 512
Right shift
Update
Section 4 Instruction Features
16 15
GT
: Ignored
REJ09B0171-0500O
Z
DSR
N V
0
Shift out
DC