HD6417041AVF16V Renesas Electronics America, HD6417041AVF16V Datasheet - Page 82

• Manufacturer Part Number: HD6417041AVF16V
• Description: IC SUPERH MCU ROMLESS 144QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7040r

Specifications of HD6417041AVF16V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 28.7MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 4 Instruction Features
Condition Bits: The condition bits are set as follows.
4.12
4.12.1
The MSB detection instruction (PDMSB: most significant bit detection) finds the amount of shift
for normalizing the data.
The operation result is the same as for ALU integer operations. Basically, the top 16 bits and 8
guard bits are valid for a total 24 bits. When the destination operand is a register that has no guard
bits, it is stored in the top 16 bits of the destination register.
The MSB detection instruction works on all bits of the source operand, but gets its operation result
in integer data. This is because the shift amount for normalization must be integer data for the
arithmetic shift operation. The action of the operation is the same as for fixed decimal point
operations and is executed in the DSP stage (the last stage) of the pipeline.
Whenever a PDMSB instruction is executed, the DSR register’s DC, N, Z, V, and GT bits are
basically updated by the operation result. For conditional instructions, condition bits are not
updated even when the specified condition is achieved and the instruction executed. For
unconditional instructions, the bits are always updated according to the operation result.
Figure 4.16 shows the MSB detection instruction flowchart. Table 4.24 shows the relationship
between source data and destination data.
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Signed Greater Than Mode: CS2–CS0 = 100: The DC bit is always 0. In this mode, the DC bit
has the same value as bit GT.
Signed Greater Than Or Equal To Mode: CS2–CS0 = 101: The DC bit is always 0.
The N bit is the same as the result of the ALU logical operation. It is set to the value of bit 31
of the operation result.
The Z bit is the same as the result of the ALU logical operation. It is set to 1 when the
operation result is all zeros; otherwise, the Z bit is 0.
The V bit is always 0.
The GT bit is always 0.
The MSB Detection Instruction
Function