HD6417041AVF16V Renesas Electronics America, HD6417041AVF16V Datasheet - Page 91

• Manufacturer Part Number: HD6417041AVF16V
• Description: IC SUPERH MCU ROMLESS 144QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7040r

Specifications of HD6417041AVF16V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 28.7MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Table 4.28 Condition Select Bits (CS) and DSP Condition Bit (DC)
2
0
0
0
0
1
1
1
1
CS Bits
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
Condition Mode
Carry/borrow
Negative
Zero
Overflow
Signed greater
than
Greater than or
equal to
Reserved
Description
The DC bit is set to 1 when a carry or borrow occurs in the result
of an ALU arithmetic operation. Otherwise, it is cleared to 0.
In logical operations, the DC bit is always cleared to 0.
For shift operations (the PSHA and PSHL instructions), the bit
shifted out last is copied to the DC bit.
In ALU arithmetic operations or arithmetic shifts (PSHA), the
MSB of the result (including the guard bits) is copied to the DC
bit.
In ALU logical operations and logical shifts (PSHL), the MSB of
the result (not including the guard bits) is copied to the DC bit.
When the result of an ALU or shift operation is all zeros (0), the
DC bit is set to 1. Otherwise, it is cleared to 0.
In ALU arithmetic operations or arithmetic shifts (PSHA), when
the operation result (not including the guard bits) exceeds the
destination register’s value range, the DC bit is set to 1.
Otherwise, it is cleared to 0.
In ALU logical operations and logical shifts (PSHL), the DC bit is
always cleared to 0.
This mode is like the Greater Than Or Equal To mode, but the
DC bit is cleared to 0 when the operation result is zero (0).
When the operation result (including the guard bits) exceeds the
expressible limits, the TRUE condition is VR.
DC bit = ~{(N bit ^ VR)|Z bit)}; for arithmetic operations
DC bit = 0; for logical operations
In ALU arithmetic operations or arithmetic shifts (PSHA), when
the result does not overflow, the value is the inversion of the
negative mode’s DC bit. When the operation result (including the
guard bits) exceeds the expressible limits, the value is the same
as the negative mode’s DC bit.
In ALU logical operations and logical shifts (PSHL), the DC bit is
always cleared to 0.
DC bit = ~(N bit ^ VR)); for arithmetic operations
DC bit = 0; for logical operations
Rev. 5.00 Jun 30, 2004 page 75 of 512
Section 4 Instruction Features
REJ09B0171-0500O