HD6417041AVF16V Renesas Electronics America, HD6417041AVF16V Datasheet - Page 95

IC SUPERH MCU ROMLESS 144QFP

HD6417041AVF16V

Manufacturer Part Number
HD6417041AVF16V
Description
IC SUPERH MCU ROMLESS 144QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7040r
Datasheets

Specifications of HD6417041AVF16V

Core Processor
SH-2
Core Size
32-Bit
Speed
28.7MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417041AVF16V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
The guard bit registers A0G and A1G can be specified for operands as independent registers.
Single data transfers use the IAB and IDB buses in place of the X bus and Y bus, so contention
occurs on the IDB bus between data transfers and instruction fetches.
Single data transfers handle word and longword data. Word data transfers involve only the top
word of the register. When data is loaded to a register, it goes to the top word and the bottom word
is automatically filled with zeros. If there are guard bits, the sign bit is extended to fill them. When
storing from a register, the top word is stored.
When a longword is transferred, 32 bits are valid. When loading a register that has guard bits, the
sign bit is extended to fill the guard bits.
When a guard bit register is stored, the top 24 bits become undefined, and the read out is to the
IDB bus. When the guard bit registers A0G and A1G load word data as the destination registers of
the MOVS.W instruction, the bottom byte is written to the register.
Figure 4.20 Single Data Transfer Flowchart (Word)
X0
X1
A0
A1
: Not affected for storing; cleared for loading. See
: Cannot be set
Pointer (R2, R3, R4, R5)
the text for information about A0G and A1G.
All memory areas
IAB[31:0]
IDB[15:0]
Y0
Y1
M0
M1
A0G
–2, 0, +2, +R8
Rev. 5.00 Jun 30, 2004 page 79 of 512
A1G DSR
Section 4 Instruction Features
REJ09B0171-0500O

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