M30626FJPFP#U7C Renesas Electronics America, M30626FJPFP#U7C Datasheet - Page 57

IC M16C/62P MCU FLASH 100QFP

M30626FJPFP#U7C

Manufacturer Part Number
M30626FJPFP#U7C
Description
IC M16C/62P MCU FLASH 100QFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheets

Specifications of M30626FJPFP#U7C

Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
31K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
M16C/62P Group (M16C/62P, M16C/62PT)
Switching Characteristics
(V
= V
= 5V, V
= 0V, at T
CC1
CC2
SS
Table 5.29
Memory Expansion and Microprocessor Modes (for 2- to 3-wait setting, external area
access and multiplex bus selection)
Symbol
t
Address Output Delay Time
d(BCLK-AD)
t
Address Output Hold Time (in relation to BCLK)
h(BCLK-AD)
t
Address Output Hold Time (in relation to RD)
h(RD-AD)
t
Address Output Hold Time (in relation to WR)
h(WR-AD)
t
Chip Select Output Delay Time
d(BCLK-CS)
t
Chip Select Output Hold Time (in relation to BCLK)
h(BCLK-CS)
t
Chip Select Output Hold Time (in relation to RD)
h(RD-CS)
t
Chip Select Output Hold Time (in relation to WR)
h(WR-CS)
t
RD Signal Output Delay Time
d(BCLK-RD)
t
RD Signal Output Hold Time
h(BCLK-RD)
t
WR Signal Output Delay Time
d(BCLK-WR)
t
WR Signal Output Hold Time
h(BCLK-WR)
t
Data Output Delay Time (in relation to BCLK)
d(BCLK-DB)
t
Data Output Hold Time (in relation to BCLK)
h(BCLK-DB)
t
Data Output Delay Time (in relation to WR)
d(DB-WR)
t
Data Output Hold Time (in relation to WR)
h(WR-DB)
t
HLDA Output Delay Time
d(BCLK-HLDA)
t
ALE Signal Output Delay Time (in relation to BCLK)
d(BCLK-ALE)
t
ALE Signal Output Hold Time (in relation to BCLK)
h(BCLK-ALE)
t
ALE Signal Output Delay Time (in relation to Address)
d(AD-ALE)
t
ALE Signal Output Hold Time (in relation to Address)
h(AD-ALE)
t
RD Signal Output Delay From the End of Address
d(AD-RD)
t
WR Signal Output Delay From the End of Address
d(AD-WR)
t
Address Output Floating Start Time
dz(RD-AD)
NOTES:
1. Calculated according to the BCLK frequency as follows:
9
0.5x10
[
]
----------------------- - 10 ns
(
)
f BCLK
2. Calculated according to the BCLK frequency as follows:
9
(
) x10
n 0.5
[
]
----------------------------------- - 40 ns
(
)
f BCLK
3. Calculated according to the BCLK frequency as follows:
9
0.5x10
[
]
----------------------- - 25 ns
(
)
f BCLK
4. Calculated according to the BCLK frequency as follows:
9
0.5x10
[
]
----------------------- - 15 ns
(
)
f BCLK
Rev.2.41
Jan 10, 2006
Page 55 of 96
REJ03B0001-0241
= −20 to 85°C / −40 to 85°C unless otherwise specified)
opr
Parameter
n is “2” for 2-wait setting, “3” for 3-wait setting.
5. Electrical Characteristics
V
=V
CC1
CC2
Standard
Min.
Max.
25
4
(NOTE 1)
(NOTE 1)
25
4
(NOTE 1)
(NOTE 1)
25
0
25
0
See
Figure 5.2
40
4
(NOTE 2)
(NOTE 1)
40
15
− 4
(NOTE 3)
(NOTE 4)
0
0
8
=5V
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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