DF2505BR26DV Renesas Electronics America, DF2505BR26DV Datasheet - Page 7

• Manufacturer Part Number: DF2505BR26DV
• Description: IC H8S/2505 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2505BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

7
A rich set of advanced functions that can completely support a wide range of applications.
EXDMAC makes high-speed data
transfers possible.
These MCUs include the EXDMAC direct memory access
controller that proves its worth in high-speed transfers of data
between two external data busses. System performance
increases significantly since data is transferred without
stopping CPU operation.
New A/D conversion mode that doubles
conversion speed.
Conversion speed is effectively doubled since the units can
convert at the same time, making high-speed conversion
possible. (Units 0 and 1 can operate independently from the
same external trigger (ADTRG0).) It is also possible to activate
the units independently from different external triggers.
Deep software standby mode
These MCUs provide deep software standby mode, which can
suppress standby mode power consumption even further.
Power to unneeded modules can be cut with register settings
and leakage current can be reduced greatly.
When EXDMAC is used for data transfers
from I/O pins to memory
Example in which ADC operation is linked using an external trigger
Unit 0
Unit 1
Example where each unit is activated by a different external trigger
Unit 0
Unit 1
Amount of data transferred: small
Execution time
ADTRG 0
CPU DMAC CPU DMAC CPU
EXD MAC
ADTRG 1
Motor control example using the CPU
AN 0
AN 1
AN 2
AN 3
AN 4
AN 5
AN 6
AN 7
Power supply
ADTRG 0
ADTRG 0
ADTRG 1
Interrupt
Interrupt
Interrupt
CPU
control
Power
supply
AN 0
AN 1
AN 2
AN 3
AN 4
AN 5
AN 6
AN 7
AN 0
AN 1
AN 2
AN 3
AN 4
AN 5
AN 6
AN 7
Motor
M
conversion 0
conversion 4
conversion 0
Earlier conversion mode
A/D
A/D
A/D
EXDMAC
Effect
CPU
ROM
TPU
conversion 1
conversion 5
conversion 1
conversion 4
Amount of data transferred: large
Execution time
A/D
A/D
A/D
A/D
EXDMAC
flash memory
CPU
CPU
Internal
ADC: Unit 0
ADC: Unit 1
OFF
conversion 2
conversion 6
conversion 2
conversion 5
Memory
I/O
A/D
A/D
A/D
A/D
DMAC
ADDR
ADDR
conversion 3
conversion 7
conversion 3
conversion 6
Effect
A/D
A/D
A/D
A/D
ADTRG 0
ADTRG 1
Logic
conversion 12
conversion 8
conversion 8
conversion 7
DMAC
EXDMAC
AN 0
AN 1
AN 2
AN 3
AN 4
AN 5
AN 6
AN 7
A/D
A/D
A/D
A/D
EXDMAC
External
External
DMAC
Clock
Clock
CPU
CPU
conversion 9
conversion 13
conversion 12
conversion 9
bus
bus
A/D
A/D
A/D
A/D
New conversion mode
OFF
With EXDMAC, CPU operation
at the same time is possible!
conversion 10
conversion 14
conversion 10
conversion 13
Read Write
Read Write
Read Write
Read Write
Leakage current
A/D
A/D
A/D
A/D
ON
conversion 11
conversion 15
conversion 11
conversion 14
CPU stopped period
The CPU is not stopped
Internal RAM
A/D
A/D
A/D
A/D
ADC: Unit 0
ADC: Unit 1
conversion 16
conversion 20
conversion 16
conversion 15
A/D
A/D
A/D
A/D
ADDR
ADDR
Synchronous serial communications unit
that provides high-speed synchronous
serial communications
These MCU provide a synchronous serial communications unit
that supports both a clock synchronous communications mode
and a 4-wire bus communications mode. This unit supports
communications with a wide range of devices that have a clock
synchronous CSI unit with CS signal by providing clock polarity
reversal, LSB/MSB first selection, conflict error detection and
other functions.
HSCI2 allows selection of an optimal
transfer clock.
HSCI2 (high-speed serial communications interface 2) allows
the selection of an optimal SCI transfer clock without
depending on the frequency of an oscillator element. It
generates the optimal average transfer rate clock source
required for the SCI from the MCU’s internal 8-bit timer (TMR
unit). This obviates the need to select an oscillator element
constrained by the SCI transfer clock, and allows an oscillator
element optimal for the system to be selected.
USB boot function that can write to
a connected flash memory.
The MCU’s internal flash memory can be written directly from
a PC using the USB boot function. Since this is a direct USB
connection, high-speed writing is possible. Furthermore, on-
site maintenance and other operations are quite and easy
since no USB/SCI converter or other external circuits are
required.
Base clock
TMO4 output: 4 MHz
Clock enable
TMO5 output
SCK5
Internal
reference clock
= 4 MHz × 3/4
= 3 MHz (average)
Vcc
GND
• SCI boot product
• USB boot product
Example of connection to a clock synchronous SCI EEPROM with CS line
Input
clock
The transfer clock is selected based
does not match.
on the input clock and the Pφ .
transfer rate
The SCI
Vcc
Vss
H8SX (master)
Earlier products
PLL
CPG
TMR (unit 2)
Pφ
1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2
1 2 3
Bφ
Iφ
Bit 1 = base clock × 16
Average transfer rate = 3 MHz / 16 = 187.5kbps
1 2 3
3MHz
USB
SSCK
External bus
SCS
SSO
SSI
TMO5
TMO4
TMR
CPU
SCI
TPU
D/A
A/D
4MHz
connected directly to the PC!
1 2 3
MCU internal circuit concept
If the device is USB
4 5 6
bootable, it can be
(Write adapter board)
USB
HS0008EAUF1H
Vcc
Clock enable
ACTION
POWER
Base clock
SCI converter
USB
1 2 3
7 8 9
H8SX/1653,1663,1638,1648,1558,1568 group
An optimal average
transfer rate can be
Input
clock
EEPROM (slave)
S
C
D
Q
set with the TMR
1 2 3
An arbitrary transfer clock is
generated using a TMR unit.
10 11 12
PLL
CPG
SCK5
SCI
Pφ
HOLD
Bφ
Iφ
Vcc
Vss
H8SX or H8S (USB boot)
W
1 2 3
H8SX or H8S (SCI boot)
SCI-5
External bus
13 14 15
H8SX/165xF
H8SX/166xF
H8S/221xUF
HSCI2
TMR
SCI
TMR
TPU
D/A
A/D
CPU
GND
Vcc
1 2
16 1
Vcc
8