MCF5484CZP200 Freescale Semiconductor, MCF5484CZP200 Datasheet

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... FIFOs – Universal serial bus (USB) version 2.0 device controller – Support for one control and six programmable © Freescale Semiconductor, Inc., 2007. All rights reserved. ® endpoints, interrupt, bulk, or isochronous – 4-Kbytes of shared endpoint FIFO RAM and 1 Kbyte of endpoint descriptor RAM – ...

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... C Input Timing Specifications between SCL and SDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2 Table 21 Output Timing Specifications between SCL and SDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 22.JTAG and Boundary Scan Timing . . . . . . . . . . . . . . . . 26 Table 23.Debug AC Timing Specifications . . . . . . . . . . . . . . . . . 28 Table 24.DSPI Modules AC Timing Specifications Table 25.Timer Module AC Timing Specifications . . . . . . . . . . . 29 ® MCF548x ColdFire Microprocessor, Rev. 4 Freescale Semiconductor ...

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... ColdFire V4e Core FPU, MMU EMAC 32K D-cache 32K I-Cache Interrupt Controller Watchdog Timer Slice Timers Timers x 4 FlexCAN x 2 DSPI Freescale Semiconductor DDR SDRAM PLL Interface XL Bus Memory Arbiter Controller XL Bus Master/Slave Interface Cryptography Accelerator*** 32K System XL Bus SRAM Read/Write Multi-Channel DMA Master Bus Interface & ...

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... Symbol PLL stg Table 2. Operating Temperatures Symbol Amax T Amin ® MCF548x ColdFire Microprocessor, Rev. 4 Value Units –0.3 to +4.0 V –0.5 to +2.0 V –0.3 to +4.0 SDR Memory V –0.3 to +2.8 DDR Memory –0.5 to +2.0 V –0 –55 to +150 C Value Units o 105 C < –40 C Freescale Semiconductor ...

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... PLL Analog operation voltage range USB oscillator operation voltage range USB digital logic operation voltage range USB PHY operation voltage range USB oscillator analog operation voltage range Freescale Semiconductor Table 3. Thermal Resistance Four layer board (2s2p) Four layer board (2s2p) Four layer board (2s2p) — ...

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... MCF548x ColdFire Microprocessor, Rev. 4 Min Max 1. 0.3 REF 0 0.3 SS REF 0 0 0.3 0. 2.4 — — 0.5 — TBD –1.0 1.0 Figure 2 input. DD pins. The filter shown in DD PLL V Pin DD ( PLL V (PLL V ), and Core Freescale Semiconductor Units μA for an DD ...

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... The recommended power down sequence is as follows: 1. Drop IV /PLL Drop EV /SD V supplies DD DD Freescale Semiconductor Supplies Stable 2 is non-critical during power-up and power-down sequences 0V, the sense circuits in the I/O pads cause all pad output drivers connected PLL V by more than 0.4V during power ramp up or there is DD ...

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... USB devices through the cable shield. 8 MCF548x (5V) (3.3V) A 8.2k B 50k 20k 50k Figure 4. Preferred VBUS Connections MCF548x (5V) (3.3V) A 50k B 50k 50k Figure 5. Alternate VBUS Connections ® MCF548x ColdFire Microprocessor, Rev. 4 Freescale Semiconductor ...

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... USB V USB V Pin DD USBVDD (Bias generator supply) USB_PHYVDD (Main transceiver supply) USB_PLLVDD (PLL supply) USB_OSCVDD (Oscillator supply) USB_OSCAVDD (Oscillator analog supply) Freescale Semiconductor and each of the USB V pins pin, a total of five circuits GND Figure 6. USB V Power Filter DD NOTE Table 5 ...

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... RSTO 1 The device’s pads have balanced sink and source current. The drive capability is the same as the sink capability. 10 USBRBIAS 9.1kΩ Figure 7. USBRBIAS Connection Table 6. I/O Driver Capability Signal ® MCF548x ColdFire Microprocessor, Rev Drive Output Capability Load ( Freescale Semiconductor ...

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... CLKIN, internal bus, and core clock frequencies for the 1x–4x multipliers. CLKIN 2x 50.0 25.0 50 100 CLKIN (MHz) Internal Clock (MHz) Figure 9. CLKIN, Internal Bus, and Core Clock Ratios Freescale Semiconductor Table 7. Clock Timing Specifications Characteristic Min 20 — — Figure 8. Input Clock Timing Diagram Table 8. MCF548x Divide Ratio Encodings ...

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... RSTI pulse duration 5 Table NOTE: Mode selects are registered on the rising clock edge before the cycle in which RSTI is recognized as being negated. Figure 10. Reset Timing ® MCF548x ColdFire Microprocessor, Rev. 4 Units Max — ns — ns — ns — CLKIN cycles R1 R3 Freescale Semiconductor ...

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... The FlexBus supports programming an extension of the address hold. Please consult the MCF548X specification manual for more information. 5 These specs are used when the PCIAD[31:0] signals are configured as 32-bit, non-muxed FlexBus address signals. Freescale Semiconductor Table 10. FlexBus AC Timing Specifications Characteristic ® MCF548x ColdFire Microprocessor, Rev ...

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... FlexBus CLKIN AD[X:0] AD[31:Y] R/W ALE TSIZ[1:0] FBCSn, BE/BWEn FB1 A[X:0] FB2 A[31:Y] DATA FB4 TSIZ[1:0] FB6 Figure 11. FlexBus Read Timing ® MCF548x ColdFire Microprocessor, Rev. 4 FB3 FB5 FB7 Freescale Semiconductor ...

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... SDR read. The MCF548x accomplishes this by asserting a signal called SDR_DQS during read cycles. Care must be taken during board design to adhere to the following guidelines and specs with regard to the SDR_DQS signal and its usage. Freescale Semiconductor FB1 A[X:0] ...

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... MCF548x ColdFire Microprocessor, Rev. 4 Min Max Unit 0 133 Mhz 7. TBD 0.45 0.55 SDCLK 0.45 0.55 SDCLK 0.5 × SDCLK + ns 1.0ns 2.0 ns Self timed ns ns Does not apply. 0.5 SDCLK fixed width. ns 1.0 ns 0.75 × SDCLK ns +0.500ns 1.5 ns Freescale Semiconductor Notes ...

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... SDDM SDRQS (Measured at Output Pin) SDDQS (Measured at Input Pin) Delayed SDCLK SDDATA form Memories NOTE: Data driven from memories relative to delayed memory clock. Freescale Semiconductor SD1 SD3 SD6 COL SD12 Figure 13. SDR Write Timing SD1 SD6 COL tDQS Board Delay Board Delay SD11 Figure 14 ...

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... SD_VDD + 0.6 1.05 1. Min Max Unit 1 50 133 MHz 7. 0.45 0.55 SDCLK 0.45 0.55 SDCLK 0.5 × SDCLK — 1.0 ns 2.0 — ns — 1.25 SDCLK 1.0 — ns 1.0 — 0.25 × SDCLK — 0.5ns 0.5 — ns 0.5 — ns Freescale Semiconductor Notes ...

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... This input skew must include DDR memory output skew and system level board skew (due to routing or other factors). 11 Data input hold is derived from each SDDQS clock edge. It begins with a SDDQS transition and ends when the first data line becomes invalid. Freescale Semiconductor ) RPRE ) RPST ...

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... SDRAM Bus SDCLK0 SDCLK1 SDCLK0 SDCLK1 SDCSn,SDWE, RAS, CAS DD4 SDADDR, SDBA[1:0] SDDM SDDQS SDDATA 20 DD1 DD2 DD5 CMD DD6 ROW COL WD1 WD2 WD3 WD4 Figure 16. DDR Write Timing ® MCF548x ColdFire Microprocessor, Rev. 4 DD3 DD7 DD8 DD7 DD8 Freescale Semiconductor ...

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... Address, Data, and Command (0 < PCI ≤ 33 Mhz)—Input Setup ( Address, Data, and Command (33–50 Mhz)—Output Valid (t P5 Address, Data, and Command (0–33 Mhz) - Output Valid (t P6 PCI signals (0–50 Mhz) - Output Hold (t Freescale Semiconductor DD1 DD2 DD5 CL=2 CMD CL=2.5 ROW ...

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... Characteristic ) Output Valid P2 Input Valid P7 Figure 18. PCI Timing ® MCF548x ColdFire Microprocessor, Rev. 4 Min Max Unit Notes 5 0 — — — — — — ns Freescale Semiconductor ...

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... TXCLK to TXD[3:0], TXEN, TXER invalid M6 TXCLK to TXD[3:0], TXEN, TXER valid M7 TXCLK pulse width high M8 TXCLK pulse width low TXCLK (Input) TXD[3:0] (Outputs) TXEN, TXER Figure 20. MII Transmit Signal Timing Diagram Freescale Semiconductor Table 15. MII Receive Signal Timing Characteristic Table 16. MII Transmit Signal Timing Characteristic ® ...

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... Characteristic M9 Figure 21. MII Async Inputs Timing Diagram Characteristic M14 M15 M10 M12 M13 ® MCF548x ColdFire Microprocessor, Rev. 4 Min Max Unit 1.5 — TX_CLK period Min Max Unit 0 — ns — — — ns 40% 60% MDC period 40% 60% MDC period M11 Freescale Semiconductor ...

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... Clock high time 1 I7 Data setup time 1 I8 Start condition setup time (for repeated start condition only Stop condition setup time Freescale Semiconductor Table 19. General AC Timing Specifications Characteristic C input timing parameters shown in Figure 2 C Input Timing Specifications between SCL and SDA Characteristic = 0 2 ...

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... JCYC CK t 15.15 — ns JCW t 0.0 3.0 ns JCRF t 5.0 — ns BSDST t 24.0 — ns BSDHT t 0.0 15.0 ns BSDV t 0.0 15.0 ns BSDZ t 5.0 — ns TAPBST t 10.0 — ns TAPBHT t 0.0 20.0 ns TDODV t 0.0 15.0 ns TDODZ t 100.0 — ns TRSTAT t 10.0 — ns TRSTST Freescale Semiconductor ...

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... TCLK (Input) TCLK Data Inputs Data Outputs Data Outputs Data Outputs TCLK TDI, TMS, BKPT TDO TDO TDO TCLK TRST Figure 27. TRST Timing Debug AC Timing Specifications Freescale Semiconductor Figure 24. Test Clock Input Timing Figure 25. Boundary Scan (JTAG) Timing Figure 26. Test Access Port Timing ...

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... Table 23. Debug AC Timing Specifications 50 MHz Characteristic Min 4.5 4 Table 23. D1 Figure 28. Real-Time Trace AC Timing Table 23. D5 Current D4 Past Figure 29. BDM Serial Port AC Timing ® MCF548x ColdFire Microprocessor, Rev. 4 29. Units Max — ns — ns — PSTCLKs — PSTCLKs — PSTCLKs D2 Next Current Freescale Semiconductor ...

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... Timer Module AC Timing Specifications Table 25 lists timer module AC timings. Table 25. Timer Module AC Timing Specifications Name T1 TIN0 / TIN1 / TIN2 / TIN3 cycle time T2 TIN0 / TIN1 / TIN2 / TIN3 pulse width Freescale Semiconductor Characteristic Figure 30. DS1 DS2 DS3 Figure 30. DSPI Timing Characteristic ® MCF548x ColdFire Microprocessor, Rev ...

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... Case Drawing 17 Case Drawing 30 ® MCF548x ColdFire Microprocessor, Rev. 4 Freescale Semiconductor ...

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... Freescale Semiconductor Figure 31. 388-pin BGA Case Outline ® MCF548x ColdFire Microprocessor, Rev. 4 Case Drawing 31 ...

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... Added footnote regarding pads having balanced source & sink current. Table 9: Added RSTI pulse duration spec. Added features list, pinout drawing, block diagram, and case outline. ® MCF548x ColdFire Microprocessor, Rev. 4 and Guidelines.” , θ , and θ JMA JB JC Freescale Semiconductor ...

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... Freescale Semiconductor THIS PAGE INTENTIONALLY BLANK ® MCF548x ColdFire Microprocessor, Rev ...

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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...