IC ARM CORTEX MCU 128K 108-BGA

LM3S6637-IBZ50-A2

Manufacturer Part NumberLM3S6637-IBZ50-A2
DescriptionIC ARM CORTEX MCU 128K 108-BGA
ManufacturerTexas Instruments
SeriesStellaris® 6000
LM3S6637-IBZ50-A2 datasheets
 


Specifications of LM3S6637-IBZ50-A2

Core ProcessorARM® Cortex-M3™Core Size32-Bit
Speed50MHzConnectivityEthernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
PeripheralsBrown-out Detect/Reset, POR, PWM, WDTNumber Of I /o41
Program Memory Size128KB (128K x 8)Program Memory TypeFLASH
Ram Size32K x 8Voltage - Supply (vcc/vdd)2.25 V ~ 2.75 V
Data ConvertersA/D 4x10bOscillator TypeInternal
Operating Temperature-40°C ~ 85°CPackage / Case108-NFBGA
Lead Free Status / RoHS StatusLead free / RoHS CompliantEeprom Size-
Other names726-1159
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Cortex-M3 / Cortex-M3 with ETM (AT420/AT425)
Date of Issue: 12-Nov-2008
ARM Errata Notice
Document Revision 2.0
ARM Core
Cortex-M3 / Cortex-M3 with ETM (AT420/AT425)
Errata Notice
This document contains the errata known at the date of issue covering supported releases from r1p1 up to and
including revision r2p0 of Cortex-M3 (AT420) and Cortex-M3 with ETM (AT425) products.
PR326-PRDC-009450 v2.0
Page 1 of 20
© Copyright ARM Limited 2008. All rights reserved.
Non Confidential

LM3S6637-IBZ50-A2 Summary of contents

  • Page 1

    Date of Issue: 12-Nov-2008 Cortex-M3 / Cortex-M3 with ETM (AT420/AT425) This document contains the errata known at the date of issue covering supported releases from r1p1 up to and including revision r2p0 of Cortex-M3 (AT420) and Cortex-M3 with ETM (AT425) ...

  • Page 2

    Date of Issue: 12-Nov-2008 Proprietary notice Words and logos marked with ® or ™ are registered trademarks or trademarks of ARM Limited in the EU and other countries, except as otherwise stated below in this proprietary notice. Other brands and ...

  • Page 3

    Date of Issue: 12-Nov-2008 Feedback on the product If you have any comments or suggestions about this product, contact your supplier giving: • The product name • A concise explanation of your comments. Feedback on this document If you have ...

  • Page 4

    Date of Issue: 12-Nov-2008 Contents INTRODUCTION ERRATA SUMMARY TABLE ERRATA PRESENT ON RELEASE R2P0-00REL0 563915: Event Register is not set by interrupts and debug 602117: LDRD with base in list may result in incorrect base register when interrupted or faulted ...

  • Page 5

    Date of Issue: 12-Nov-2008 Introduction Scope This document describes errata categorised by level of severity. Each description includes: • a unique defect tracking identifier • the current status of the defect • where the implementation deviates from the specification and ...

  • Page 6

    Date of Issue: 12-Nov-2008 PR326-PRDC-009450 v2.0 Cortex-M3 / Cortex-M3 with ETM (AT420/AT425) ARM Errata Notice © Copyright ARM Limited 2008. All rights reserved. Non Confidential Document Revision 2.0 Page ...

  • Page 7

    Date of Issue: 12-Nov-2008 Errata Summary Table The errata associated with this product affect product versions as below cell shown thus indicates that the defect affects the revision shown at the top of that column. ID Cat Summary ...

  • Page 8

    Date of Issue: 12-Nov-2008 Errata present on release r2p0-00rel0 563915: Event Register is not set by interrupts and debug Status Affects: product Cortex-M3, Cortex-M3 with ETM. Fault status: Cat 2, Present in: r0p0,r1p0,r1p1,r1p1-00rel0,r1p1-01rel0,r2p0-00rel0, Open. Description The event register used for ...

  • Page 9

    Date of Issue: 12-Nov-2008 602117: LDRD with base in list may result in incorrect base register when interrupted or faulted Status Affects: product Cortex-M3, Cortex-M3 with ETM. Fault status: Cat 2, Present in: r0p0,r1p0,r1p1,r1p1-00rel0,r1p1-01rel0,r2p0-00rel0, Open. Description LDRD with the base ...

  • Page 10

    Date of Issue: 12-Nov-2008 Implications The base register will not be restored as expected preventing the instruction from being restarted correctly upon return from the interrupt service routine or from the fault handler. Workaround There are two workarounds for this ...

  • Page 11

    Date of Issue: 12-Nov-2008 Errata fixed on release r2p0-00rel0 531064: SWJ-DP missing POR reset sync Status Affects: product Cortex-M3, Cortex-M3 with ETM. Fault status: Impl, Present in: r1p1,r1p1-00rel0,r1p1-01rel0, Fixed in r2p0-00rel0. Description In Cortex-M3 r0p0 and r1p0, the SWJ-DP has ...

  • Page 12

    Date of Issue: 12-Nov-2008 511864: Cortex-M3 may fetch instructions using incorrect privilege on return from an exception Status Affects: product Cortex-M3, Cortex-M3 with ETM. Fault status: Cat 3, Present in: r0p0,r1p0,r1p1,r1p1-00rel0,r1p1-01rel0, Fixed in r2p0-00rel0. Description Whilst unstacking registers on return ...

  • Page 13

    Date of Issue: 12-Nov-2008 532314: DWT CPI counter increments during sleep Status Affects: product Cortex-M3, Cortex-M3 with ETM. Fault status: Cat 3, Present in: r0p0,r1p0,r1p1,r1p1-00rel0,r1p1-01rel0, Fixed in r2p0-00rel0. Description The DWT contains a number of counters for the profiling of ...

  • Page 14

    Date of Issue: 12-Nov-2008 538714: Cortex-M3 TPIU Clock Domain crossing Status Affects: product Cortex-M3, Cortex-M3 with ETM. Fault status: Cat 3, Present in: r0p0,r1p0,r1p1,r1p1-00rel0,r1p1-01rel0, Fixed in r2p0-00rel0. Description Combinatorial paths exist in control signals crossing the asynchronous clock boundary between ...

  • Page 15

    Date of Issue: 12-Nov-2008 548721: Internal write buffer could be active whilst asleep Status Affects: product Cortex-M3, Cortex-M3 with ETM. Fault status: Cat 3, Present in: r0p0,r1p0,r1p1,r1p1-00rel0,r1p1-01rel0, Fixed in r2p0-00rel0. Description If a store immediate that is marked as not ...

  • Page 16

    Date of Issue: 12-Nov-2008 463763: BKPT in debug monitor mode can cause DFSR mismatch Status Affects: product Cortex-M3, Cortex-M3 with ETM. Fault status: Cat 3, Present in: r0p0,r1p0,r1p1,r1p1-00rel0,r1p1-01rel0, Fixed in r2p0-00rel0. Description A BKPT may be executed in debug monitor ...

  • Page 17

    Date of Issue: 12-Nov-2008 463764: Core may freeze for SLEEPONEXIT single instruction ISR Status Affects: product Cortex-M3, Cortex-M3 with ETM. Fault status: Cat 3, Present in: r0p0,r1p0,r1p1,r1p1-00rel0,r1p1-01rel0, Fixed in r2p0-00rel0. Description The SLEEPONEXIT functionality causes the core to enter the ...

  • Page 18

    Date of Issue: 12-Nov-2008 463769: Unaligned MPU fault during a write may cause the wrong data to be written to a successful first access Status Affects: product Cortex-M3, Cortex-M3 with ETM. Fault status: Cat 3, Present in: r0p0,r1p0,r1p1,r1p1-00rel0,r1p1-01rel0, Fixed in ...

  • Page 19

    Date of Issue: 12-Nov-2008 Errata fixed on release r1p1-01rel0 429964: Async not generated if no trace in previous session Status Affects: product Cortex-M3 with ETM. Fault status: Cat 2, Present in: r0p0,r1p0,r1p1,r1p1-00rel0, Fixed in r1p1-01rel0. Description The ETM is required ...

  • Page 20

    Date of Issue: 12-Nov-2008 429965: Trigger packets sometimes not inserted in trace stream Status Affects: product Cortex-M3 with ETM. Fault status: Cat 2, Present in: r0p0,r1p0,r1p1,r1p1-00rel0, Fixed in r1p1-01rel0. Description It is possible to configure a trigger event for the ...

  • Page 21

    ... Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’ ...