ATTINY25-20SUR Atmel, ATTINY25-20SUR Datasheet

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ATTINY25-20SUR

Manufacturer Part Number
ATTINY25-20SUR
Description
MCU AVR 2KB FLASH 20MHZ 8SOIC
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet

Specifications of ATTINY25-20SUR

Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
6
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
High Performance, Low Power AVR
Advanced RISC Architecture
Non-volatile Program and Data Memories
Peripheral Features
Special Microcontroller Features
I/O and Packages
Operating Voltage
Speed Grade
Industrial Temperature Range
Low Power Consumption
– 120 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– 2/4/8K Bytes of In-System Programmable Program Memory Flash
– 128/256/512 Bytes In-System Programmable EEPROM
– 128/256/512 Bytes Internal SRAM
– Programming Lock for Self-Programming Flash Program and EEPROM Data
– 8-bit Timer/Counter with Prescaler and Two PWM Channels
– 8-bit High Speed Timer/Counter with Separate Prescaler
– USI – Universal Serial Interface with Start Condition Detector
– 10-bit ADC
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– debugWIRE On-chip Debug System
– In-System Programmable via SPI Port
– External and Internal Interrupt Sources
– Low Power Idle, ADC Noise Reduction, and Power-down Modes
– Enhanced Power-on Reset Circuit
– Programmable Brown-out Detection Circuit
– Internal Calibrated Oscillator
– Six Programmable I/O Lines
– 8-pin PDIP, 8-pin SOIC, 20-pad QFN/MLF, and 8-pin TSSOP (only ATtiny45/V)
– 1.8 - 5.5V for ATtiny25V/45V/85V
– 2.7 - 5.5V for ATtiny25/45/85
– ATtiny25V/45V/85V: 0 – 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V
– ATtiny25/45/85: 0 – 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V
– Active Mode:
– Power-down Mode:
Security
• Endurance: 10,000 Write/Erase Cycles
• Endurance: 100,000 Write/Erase Cycles
• 2 High Frequency PWM Outputs with Separate Output Compare Registers
• Programmable Dead Time Generator
• 4 Single Ended Channels
• 2 Differential ADC Channel Pairs with Programmable Gain (1x, 20x)
• Temperature Measurement
• 1 MHz, 1.8V: 300 µA
• 0.1 µA at 1.8V
®
8-Bit Microcontroller
8-bit
Microcontroller
with 2/4/8K
Bytes In-System
Programmable
Flash
ATtiny25/V
ATtiny45/V
ATtiny85/V *
* Preliminary
Rev. 2586M–AVR–07/10

Related parts for ATTINY25-20SUR

ATTINY25-20SUR Summary of contents

Page 1

... ATtiny25V/45V/85V – 2.7 - 5.5V for ATtiny25/45/85 • Speed Grade – ATtiny25V/45V/85V: 0 – 4 MHz @ 1.8 - 5.5V MHz @ 2.7 - 5.5V – ATtiny25/45/85: 0 – 10 MHz @ 2.7 - 5.5V MHz @ 4.5 - 5.5V • Industrial Temperature Range • Low Power Consumption – Active Mode: • ...

Page 2

... Pin Configurations Figure 1-1. Pinout ATtiny25/45/85 (PCINT5/RESET/ADC0/dW) PB5 (PCINT3/XTAL1/CLKI/OC1B/ADC3) PB3 (PCINT4/XTAL2/CLKO/OC1B/ADC2) PB4 (PCINT5/RESET/ADC0/dW) PB5 (PCINT3/XTAL1/CLKI/OC1B/ADC3) PB3 (PCINT4/XTAL2/CLKO/OC1B/ADC2) PB4 NOTE: Bottom pad should be soldered to ground. DNC: Do Not Connect 1.1 Pin Descriptions 1.1.1 VCC Supply voltage. 1.1.2 GND Ground. 1.1.3 Port B (PB5:PB0) Port 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability ...

Page 3

... Port B also serves the functions of various special features of the ATtiny25/45/85 as listed in “Alternate Functions of Port B” on page On ATtiny25, the programmable I/O ports PB3 and PB4 (pins 2 and 3) are exchanged in ATtiny15 Compatibility Mode for supporting the backward compatibility with ATtiny15. 1.1.4 RESET Reset input ...

Page 4

... Overview The ATtiny25/45/ low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny25/45/85 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1 ...

Page 5

... On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI serial interface conventional non-volatile memory programmer On-chip boot code running on the AVR core. The ATtiny25/45/85 AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators and Evaluation kits. 2586M–AVR–07/10 ...

Page 6

... Note that not all AVR devices include an extended I/O map. 3.3 Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. ATtiny25/45/85 6 2586M–AVR–07/10 ...

Page 7

AVR CPU Core 4.1 Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control ...

Page 8

... Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. ATtiny25/45/85 8 2586M–AVR–07/10 ...

Page 9

SREG – AVR Status Register The AVR Status Register – SREG – is defined as: Bit 0x3F Read/Write Initial Value • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts ...

Page 10

... The registers R26..R31 have some added functions to their general purpose usage. These reg- isters are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in ATtiny25/45/85 10 shows the structure of the 32 general purpose working registers in the CPU. ...

Page 11

Figure 4-3. X-register Y-register Z-register In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 4.6 Stack Pointer The Stack is mainly used for storing ...

Page 12

... Interrupt Vectors. The complete list of vectors is shown in determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. ATtiny25/45/ directly generated from the selected clock source for the CPU ...

Page 13

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis- abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt ...

Page 14

... A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. ATtiny25/45/ set Global Interrupt Enable 2586M–AVR–07/10 ...

Page 15

... The ATtiny25/45/85 contains 2/4/8K bytes On-chip In-System Reprogrammable Flash memory for program storage. Since all AVR instructions are bits wide, the Flash is organized as 1024/2048/4096 x 16. The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATtiny25/45/85 Program Counter (PC) is 10/11/12 bits wide, thus addressing the 1024/2048/4096 Program memory locations. ...

Page 16

... When using register indirect addressing modes with automatic pre-decrement and post-incre- ment, the address registers X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, and the 128/256/512 bytes of inter- nal data SRAM in the ATtiny25/45/85 are all accessible through all these addressing modes. The Register File is described in Figure 5-2. ...

Page 17

EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space. The write access times for the EEPROM are given in tion, however, lets the user software detect when the next byte can be written. If the ...

Page 18

... Set up address and data registers */ EEAR = ucAddress; EEDR = ucData; /* Write logical one to EEMPE */ EECR |= (1<<EEMPE); /* Start eeprom write by setting EEPE */ EECR |= (1<<EEPE); } ATtiny25/45/85 18 r16, (0<<EEPM1)|(0<<EEPM0) EECR, r16 ; “OSCCAL – Oscillator Calibration Register” on 2586M–AVR–07/10 ...

Page 19

The next code examples show assembly and C functions for reading the EEPROM. The exam- ples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. Assembly Code Example EEPROM_read: C Code Example unsigned ...

Page 20

... I/O Memory The I/O space definition of the ATtiny25/45/85 is shown in All ATtiny25/45/85 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions ...

Page 21

... Initial Value • Bit 7 – Res: Reserved Bit This bit is reserved for future use and will always read ATtiny25/45/85. For compatibility with future AVR devices, always write this bit to zero. After reading, mask out this bit. • Bit 6 – Res: Reserved Bit This bit is reserved in the ATtiny25/45/85 and will always read as zero. • ...

Page 22

... When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEPE bit before starting the read opera- tion write operation is in progress neither possible to read the EEPROM, nor to change the EEAR Register. ATtiny25/45/85 22 2586M–AVR–07/10 ...

Page 23

System Clock and Clock Options 6.1 Clock Systems and their Distribution Figure 6-1 need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using ...

Page 24

... Internal PLL for Fast Peripheral Clock Generation - clk The internal PLL in ATtiny25/45/85 generates a clock frequency that is 8x multiplied from a source input. By default, the PLL uses the output of the internal, 8.0 MHz RC oscillator as source. Alternatively, if bit LSM of PLLCSR is set the PLL will use the output of the RC oscillator divided by two ...

Page 25

In the ATtiny15 compatibility mode the frequency of the internal RC oscillator is calibrated down to 6.4 MHz and the multiplication factor of the PLL is set to 4x. See adjustments the clocking system is ATtiny15-compatible and the resulting fast ...

Page 26

... High Frequency PLL Clock There is an internal PLL that provides nominally 64 MHz clock rate locked to the RC Oscillator for the use of the Peripheral Timer/Counter1 and for the system clock source. When selected as ATtiny25/45/85 26 Number of Watchdog Oscillator Cycles Typ Time-out 4 ms ...

Page 27

CKSEL fuses to ‘0001’ divided by four like shown in Table 6-4. When this clock source is selected, start-up times are determined by the SUT fuses as shown in Table 6-5. ...

Page 28

... In summary, more information on ATtiny15 Compatibility Mode can be found in sections (PB5:PB0)” on page Timer/Counter1 in ATtiny15 Mode” on page bration Bytes” on page 154 ATtiny25/45/85 28 98). Note that in this mode of operation the 6.4 MHz clock signal is always Internal Calibrated RC Oscillator Operating Modes CKSEL[3:0] ...

Page 29

... Note: The Low-frequency Crystal Oscillator provides an internal load capacitance, see each TOSC pin. Table 6-11. ATtiny25/45/85 2586M–AVR–07/10 Start-up Times for the 128 kHz Internal Oscillator Start-up Time from Power-down the RSTDISBL fuse is programmed, this start-up time will be increased to 14CK + ensure programming mode can be entered ...

Page 30

... The Oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL[3:1] as shown in The CKSEL0 Fuse together with the SUT[1:0] Fuses select the start-up times as shown in 6-13. Table 6-13. CKSEL0 ATtiny25/45/85 30 Crystal Oscillator Connections C2 C1 Table 6-12 Crystal Oscillator Operating Modes Frequency Range (MHz) (1) ...

Page 31

... High-voltage Programmer. 6.3 System Clock Prescaler The ATtiny25/45/85 system clock can be divided by setting the ter” on page requirement for processing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals. clk and clk 6 ...

Page 32

... Changes in OSCCAL should not exceed 0x20 for each calibration required to ensure that the MCU is kept in Reset during such changes in the clock frequency Table 6-14. OSCCAL Value 0x00 0x3F 0x7F ATtiny25/45/ CAL7 CAL6 ...

Page 33

... CLKPCE bit. • Bits 6:4 – Res: Reserved Bits These bits are reserved bits in the ATtiny25/45/85 and will always read as zero. • Bits 3:0 – CLKPS[3:0]: Clock Prescaler Select Bits These bits define the division factor between the selected clock source and the internal system clock ...

Page 34

... The device is shipped with the CKDIV8 Fuse programmed. Table 6-15. CLKPS3 Note: ATtiny25/45/85 34 Clock Prescaler Select CLKPS2 CLKPS1 The prescaler is disabled in ATtiny15 compatibility mode and neither writing to CLKPR, nor pro- gramming the CKDIV8 fuse has any effect on the system clock (which will always be 1.6 MHz). ...

Page 35

... MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. 7.1 Sleep Modes Figure 6-1 on page 23 ATtiny25/45/85. The figure is helpful in selecting an appropriate sleep mode. the different sleep modes and their wake up sources. Table 7-1. Sleep Mode Idle ...

Page 36

... BOD active. The default setting is zero, i.e. BOD active. Writing to the BODS bit is controlled by a timed sequence and an enable bit, see MCU Control Register” on page ATtiny25/45/85 36 124. This will reduce power consumption in Idle level has dropped during the sleep period. ...

Page 37

... Limitations BOD disable functionality has been implemented in the following devices, only: • ATtiny25, revision E, and newer • ATtiny45, all revisions • ATtiny85, revision C, and newer Revisions are marked on the device package and can be located as follows: • Bottom side of packages 8P3 and 8S2 • ...

Page 38

... Bit 7 – BODS: BOD Sleep BOD disable functionality is available in some devices, only. See In order to disable BOD during sleep (see logic one. This is controlled by a timed sequence and the enable bit, BODSE in MCUCR. First, ATtiny25/45/85 38 “Brown-out Detection” on page 43 for details on how to configure the Brown-out Detector. ...

Page 39

... Initial Value • Bits 7:4 – Res: Reserved Bits These bits are reserved bits in the ATtiny25/45/85 and will always read as zero. • Bit 3 – PRTIM1: Power Reduction Timer/Counter1 Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1 is enabled, operation will continue like before the shutdown. 2586M– ...

Page 40

... Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down. Note that the ADC clock is also used by some parts of the analog comparator, which means that the analogue comparator can not be used when this bit is high. ATtiny25/45/85 40 2586M–AVR–07/10 ...

Page 41

... Reset Sources The ATtiny25/45/85 has four sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length. • ...

Page 42

... Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage – V edge, the delay counter starts the MCU after the Time-out period – t ATtiny25/45/85 42 “System and Reset Characteristics” on page rise ...

Page 43

... Figure 8-4. 8.2.3 Brown-out Detection ATtiny25/45/85 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V during operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as V ...

Page 44

... Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs. Ten different clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog Reset, the ATtiny25/45/85 resets and executes from the Reset Vec- tor. For timing details on the Watchdog Reset, refer to The Wathdog Timer can also be configured to generate an interrupt instead of a reset ...

Page 45

Sequences for Changing the Configuration of the Watchdog Timer” on page 45 details. Table 8-1. WDTON Unprogrammed Programmed Figure 8-7. 8.4.1 Timed Sequences for Changing the Configuration of the Watchdog Timer The sequence for changing configuration differs slightly between ...

Page 46

... Clear WDRF in MCUSR */ MCUSR = 0x00 /* Write logical one to WDCE and WDE */ WDTCR |= (1<<WDCE) | (1<<WDE); /* Turn off WDT */ WDTCR = 0x00; } Note: ATtiny25/45/85 46 (1) r16, (0<<WDRF) MCUSR, r16 r16, WDTCR (1) 1. See “Code Examples” on page 6. 2586M–AVR–07/10 ...

Page 47

... Initial Value • Bits 7:4 – Res: Reserved Bits These bits are reserved bits in the ATtiny25/45/85 and will always read as zero. • Bit 3 – WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset writing a logic zero to the flag. • ...

Page 48

... To clear WDE, WDRF must be cleared before disabling the Watchdog with the procedure described above. This feature ensures multiple resets during conditions causing failure, and a safe start-up after the failure. Note: ATtiny25/45/85 48 Watchdog Timer Configuration WDIE Watchdog Timer State ...

Page 49

Bits 5, 2:0 – WDP[3:0]: Watchdog Timer Prescaler and 0 The WDP[3:0] bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. The different prescaling values and their corresponding Timeout Periods are shown in ...

Page 50

... If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATtiny25/45/85 is shown in the program example below. Address Labels Code ...

Page 51

External Interrupts The External Interrupts are triggered by the INT0 pin or any of the PCINT[5:0] pins. Observe that, if enabled, the interrupts will trigger even if ...

Page 52

... The level and edges on the external INT0 pin that activate the interrupt are defined in If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is ATtiny25/45/85 52 Timing of pin change interrupts pin_lat ...

Page 53

... Initial Value • Bits 7, 4:0 – Res: Reserved Bits These bits are reserved bits in the ATtiny25/45/85 and will always read as zero. • Bit 6 – INTF0: External Interrupt Flag 0 When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set (one) ...

Page 54

... Initial Value • Bits 7:6 – Res: Reserved Bits These bits are reserved bits in the ATtiny25/45/85 and will always read as zero. • Bits 5:0 – PCINT[5:0]: Pin Change Enable Mask 5:0 Each PCINT[5:0] bit selects whether pin change interrupt is enabled on the corresponding I/O pin ...

Page 55

I/O Ports 10.1 Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin ...

Page 56

... If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). ATtiny25/45/85 56 (1) Pxn ...

Page 57

Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port. 10.2.3 Switching Between ...

Page 58

... Define directions for port pins ldi ldi out out ; Insert nop for synchronization nop ; Read port pins in ... Note: ATtiny25/45/85 58 Figure 10-4. The out instruction sets the “SYNC LATCH” signal at the positive edge of SYSTEM CLK r16 INSTRUCTIONS out PORTx, r16 SYNC LATCH PINxn r17 (1) r16,(1< ...

Page 59

C Code Example unsigned char i; 10.2.5 Digital Input Enable and Sleep Modes As shown in schmitt-trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-down mode to avoid high power consumption if ...

Page 60

... AVR microcontroller family. Figure 10-5. Alternate Port Functions Pxn PUOExn: PUOVxn: DDOExn: DDOVxn: PVOExn: PVOVxn: DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE SLEEP: PTOExn: Note: ATtiny25/45/85 60 (1) PUOExn PUOVxn 1 0 DDOExn DDOVxn 1 0 PVOExn PVOVxn 1 ...

Page 61

Table 10-2 ure 10-5 in the modules having the alternate function. Table 10-2. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 2586M–AVR–07/10 summarizes the function of the overriding signals. The pin and port indexes from ...

Page 62

... RSTDISBL Fuse. Pullup is activated and output driver and digital input are deactivated when the pin is used as the RESET pin. • dW: When the debugWIRE Enable (DWEN) Fuse is programmed and Lock bits are unprogrammed, the debugWIRE system within the target device is activated. The RESET ATtiny25/45/85 62 Port B Pins Alternate Functions Port Pin ...

Page 63

I/O pin with pull-up enabled and becomes the communication gateway between target and emulator. • ADC0: Analog to Digital Converter, Channel 0 • PCINT5: Pin Change Interrupt source 5. • Port ...

Page 64

... Internal Voltage Reference with external capacitor at the AREF pin. • DI: Data Input in USI Three-wire mode. USI Three-wire mode does not override normal port functions, so pin must be configure as an input for DI function. • PCINT0: Pin Change Interrupt source 0. ATtiny25/45/85 64 2586M–AVR–07/10 ...

Page 65

Table 10-4 shown in Table 10-4. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Note: Table 10-5. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 2586M–AVR–07/10 and Table 10-5 relate ...

Page 66

... PORTB – Port B Data Register Bit 0x18 Read/Write Initial Value 10.4.3 DDRB – Port B Data Direction Register Bit 0x17 Read/Write Initial Value 10.4.4 PINB – Port B Input Pins Address Bit 0x16 Read/Write Initial Value ATtiny25/45/ BODS PUD SE SM1 R R/W R/W R for more details about this feature ...

Page 67

... I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit loca- tions are listed in the Figure 11-1. 8-bit Timer/Counter Block Diagram 2586M–AVR–07/10 “Pinout ATtiny25/45/85” on page “Register Description” on page Count Clear Control Logic ...

Page 68

... Prescaler Reset The prescaler is free running, i.e. it operates independently of the Clock Select logic of Timer/Counter0. Since the prescaler is not affected by the timer/counter’s clock select, the state ATtiny25/45/85 68 See “Output Compare Unit” on page 71. Table 11-1 are also used extensively throughout the document. ...

Page 69

One exam- ple of a prescaling artifact is when the timer/counter is enabled and clocked by the prescaler (6 > CS0[2:0] > 1). The number of ...

Page 70

... The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. 11-4 shows a block diagram of the counter and its surroundings. Figure 11-4. Counter Unit Block Diagram Signal description (internal signals): count direction clear clk top bottom ATtiny25/45/85 70 Clear Synchronization DATA BUS count clear TCNTn Control Logic direction bottom Increment or decrement TCNT0 by 1 ...

Page 71

Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk selected by the Clock Select bits (CS0[2:0]). When no clock source is selected (CS0[2: the timer is stopped. However, ...

Page 72

... PORT) that are affected by the COM0x[1:0] bits are shown. When referring to the OC0x state, the reference is for the internal OC0x Register, not the OC0x pin system reset occur, the OC0x Register is reset to “0”. ATtiny25/45/85 72 Figure 11-6 shows a sim- ...

Page 73

Figure 11-6. Compare Match Output Unit, Schematic COMnx1 COMnx0 FOCn clk I/O The general I/O port function is overridden by the Output Compare (OC0x) from the Waveform Generator if either of the COM0x[1:0] bits are set. However, the OC0x pin ...

Page 74

... The timing diagram for the CTC mode is shown in increases until a Compare Match occurs between TCNT0 and OCR0A, and then counter (TCNT0) is cleared. Figure 11-7. CTC Mode, Timing Diagram TCNTn OCn (Toggle) Period ATtiny25/45/85 74 (See “Compare Match Output Unit” on page Figure 11-10, Figure 78. Figure ...

Page 75

An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing TOP to ...

Page 76

... OC0x to toggle its logical level on each Compare Match (COM0x[1:0] = 1). The waveform generated will have a maximum frequency of f feature is similar to the OC0A toggle in CTC mode, except the double buffer feature of the Out- put Compare unit is enabled in the fast PWM mode. ATtiny25/45/ ...

Page 77

Phase Correct PWM Mode The phase correct PWM mode (WGM0[2: provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly ...

Page 78

... Figure 11-10. Timer/Counter Timing Diagram, no Prescaling clk I/O clk Tn (clk /1) I/O TCNTn TOVn Figure 11-11 ATtiny25/45/85 78 Table 11-4 on page f OCnxPCPWM Figure 11-9 OCn has a transition from high to low even though Figure Figure 11-10 contains timing data for basic Timer/Counter operation. The figure MAX - 1 MAX shows the same timing data, but with the prescaler enabled ...

Page 79

Figure 11-11. Timer/Counter Timing Diagram, with Prescaler (f clk I/O clk Tn (clk /8) I/O TCNTn TOVn Figure 11-12 mode and PWM mode, where OCR0A is TOP. Figure 11-12. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (f clk I/O ...

Page 80

... When OC0A/OC0B is connected to the I/O pin, the function of the COM0A[1:0]/COM0B[1:0] bits depend on the WGM0[2:0] bit setting. the WGM0[2:0] bits are set to a normal or CTC mode (non-PWM). Table 11-2. COM0A1 COM0B1 ATtiny25/45/ TSM PWM1B COM1B1 COM1B0 R/W ...

Page 81

... Note: • Bits 3:2 – Res: Reserved Bits These bits are reserved bits in the ATtiny25/45/85 and will always read as zero. • Bits 1:0 – WGM0[1:0]: Waveform Generation Mode Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting ...

Page 82

... Therefore it is the value present in the COM0B[1:0] bits that determines the effect of the forced compare. A FOC0B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0B as TOP. ATtiny25/45/85 82 Waveform Generation Mode Bit Description WGM WGM ...

Page 83

... The FOC0B bit is always read as zero. • Bits 5:4 – Res: Reserved Bits These bits are reserved bits in the ATtiny25/45/85 and will always read as zero. • Bit 3 – WGM02: Waveform Generation Mode See the description in the • Bits 2:0 – CS0[2:0]: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter ...

Page 84

... Bit 4 – OCF0A: Output Compare Flag 0 A The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 and the data in OCR0A – Output Compare Register0. OCF0A is cleared by hardware when executing the cor- responding interrupt handling vector. Alternatively, OCF0A is cleared by writing a logic one to ATtiny25/45/ ...

Page 85

When the I-bit in SREG, OCIE0A (Timer/Counter0 Compare Match Interrupt Enable), and OCF0A are set, the Timer/Counter0 Compare Match Interrupt is executed. • Bit 3 – OCF0B: Output Compare Flag 0 B The OCF0B bit is set when ...

Page 86

... The Timer/Counter1 features a high resolution and a high accuracy usage with the lower pres- caling opportunities. It can also support two accurate, high speed, 8-bit Pulse Width Modulators using clock speeds MHz (or 32 MHz in Low Speed Mode). In this mode, ATtiny25/45/85 86 shows the Timer/Counter1 prescaler that supports two clocking modes, a synchro- ...

Page 87

Timer/Counter1 and the output compare registers serve as dual stand-alone PWMs with non- overlapping non-inverted and inverted outputs. Refer to this function. Similarly, the high prescaling opportunities make this unit useful for lower speed functions or exact timing functions with ...

Page 88

... In PWM mode, the Timer Counter counts up to the value specified in the output com- pare register OCR1C and starts again from $00. This feature allows limiting the counter “full” value to a specified value, lower than $FF. Together with the many prescaler options, flexible PWM frequency selection is provided. ATtiny25/45/85 88 T/C1 OVER- T/C1 COMPARE ...

Page 89

PWM frequencies from 20 kHz to 250 kHz in 10 kHz steps and from 250 kHz to 500 kHz in 50 kHz steps. Higher PWM frequencies can be obtained at the expense of resolution. 12.2.1 Timer/Counter1 Initialization ...

Page 90

... The frequency of the PWM will be Timer Clock 1 Frequency divided by (OCR1C value + 1). See the following equation: Resolution shows how many bits are required to express the value in the OCR1C register and can be calculated using the following equation: ATtiny25/45/85 90 Synchronized OC1x Latch Unsynchronized OC1x Latch Table 12-2 ...

Page 91

Table 12-3. PWM Frequency 20 kHz 30 kHz 40 kHz 50 kHz 60 kHz 70 kHz 80 kHz 90 kHz 100 kHz 110 kHz 120 kHz 130 kHz 140 kHz 150 kHz 160 kHz 170 kHz 180 kHz 190 kHz ...

Page 92

... In Normal mode, the COM1A1 and COM1A0 control bits determine the output pin actions that affect pin PB1 (OC1A) as described in mode. Table 12-4. COM1A1 PWM mode, these bits have different functions. Refer to description. ATtiny25/45/ CTC1 PWM1A COM1A1 COM1A0 R/W R/W ...

Page 93

Bits 3:0 - CS1[3:0]: Clock Select Bits and 0 The Clock Select bits and 0 define the prescaling source of Timer/Counter1. Table 12-5. CS13 ...

Page 94

... Timer/Counter1 is realized counter with read and write access. Due to synchronization of the CPU, Timer/Counter1 data written into Timer/Counter1 is delayed by one and half CPU clock cycles in synchronous mode and at most one CPU clock cycles for asynchronous mode. ATtiny25/45/85 94 Table 12-6. Note that OC1B is not connected in normal ...

Page 95

OCR1A –Timer/Counter1 Output Compare RegisterA Bit 0x2E Read/Write Initial value The output compare register 8-bit read/write register. The Timer/Counter Output Compare Register A contains data to be continuously compared with Timer/Counter1. Actions on compare matches are ...

Page 96

... Read/Write Initial value • Bit 7 – Res: Reserved Bit This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero. • Bit 6 – OCF1A: Output Compare Flag 1A The OCF1A bit is set (one) when compare match occurs between Timer/Counter1 and the data value in OCR1A - Output Compare Register 1A ...

Page 97

... When the SREG I-bit, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the Timer/Counter1 Overflow interrupt is executed. • Bit 0 – Res: Reserved Bit This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero. 12.3.9 PLLCSR – PLL Control and Status Register ...

Page 98

... It can also support an accurate, high speed, 8-bit Pulse Width Modulator (PWM) using clock speeds up to 25.6 MHz. In this mode, Timer/Counter1 and the Output Com- pare Registers serve as a stand-alone PWM. Refer to ATtiny25/45/85 98 shows an ATtiny15 compatible prescaler. It has two prescaler units, a 10-bit pres- ...

Page 99

Similarly, the high prescaling opportunities make this unit useful for lower speed functions or exact timing functions with infrequent actions. Figure 13-2. Timer/Counter 1 Synchronization Register Block Diagram. IO-registers PCKE CK PCK ...

Page 100

... Together with the many prescaler options, flexible PWM frequency selection is provided. 12-3 on page 91 20 kHz to 250 kHz in 10 kHz steps and from 250 kHz to 500 kHz in 50 kHz steps. Higher PWM frequencies can be obtained at the expense of resolution. ATtiny25/45/85 100 T/C1 OVER- T/C1 COMPARE ...

Page 101

Timer/Counter1 in PWM Mode When the PWM mode is selected, Timer/Counter1 and the Output Compare Register A - OCR1A form an 8-bit, free-running and glitch-free PWM generator with output on the PB1(OC1A). When the counter value match the content ...

Page 102

... The duty cycle of the PWM waveform can be calculated using the following equation: ...where T Resolution indicates how many bits are required to express the value in the OCR1C register. It can be calculated using the following equation: Table 13-3. PWM Frequency ATtiny25/45/85 102 PWM Outputs OCR1A = $00 or OCR1C COM1A0 0 1 ...

Page 103

Table 13-3. PWM Frequency 13.3 Register Description 13.3.1 TCCR1 – Timer/Counter1 Control Register Bit 0x30 Read/Write Initial value • Bit 7 – CTC1 : Clear Timer/Counter on Compare Match When the CTC1 control bit is set (one), Timer/Counter1 is reset ...

Page 104

... Bits 3:0 – CS1[3:0]: Clock Select Bits and 0 The Clock Select bits and 0 define the prescaling source of Timer/Counter1. Table 13-5. CS13 The Stop condition provides a Timer Enable/Disable function. ATtiny25/45/85 104 Comparator A Mode Select COM1A0 Description 0 Timer/Counter Comparator A disconnected from output pin OC1A. ...

Page 105

GTCCR – General Timer/Counter1 Control Register Bit 0x2C Read/Write Initial value • Bit 2 – FOC1A: Force Output Compare Match 1A Writing a logical one to this bit forces a change in the compare match output pin PB1 (OC1A) ...

Page 106

... This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero. 13.3.7 TIFR – Timer/Counter Interrupt Flag Register Bit 0x38 Read/Write Initial value • Bit 7 – Res: Reserved Bit This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero. ATtiny25/45/85 106 MSB ...

Page 107

... TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the Timer/Counter1 Overflow interrupt is executed. • Bit 0 – Res: Reserved Bit This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero. 13.3.8 PLLCSR – PLL Control and Status Register ...

Page 108

... The counter is loaded with a 4-bit DT1xH or DT1xL value from DT1x I/O register, depending on the edge of the PWM generator output when the dead time insertion is started. Figure 14-2. Dead Time Generator T/C1 CLOCK PWM1x ATtiny25/45/85 108 PCKE TIMER/COUNTER1 T15M CK ...

Page 109

The length of the counting period is user adjustable by selecting the dead time prescaler setting in 0x23 register, and selecting then the dead time value in I/O register DT1x. The DT1x register consists of two 4-bit fields, DT1xH and ...

Page 110

... Bits 3:0 – DT1BL[3:0]: Dead Time Value for OC1B Output The dead time value for the OC1B output. The dead time delay is set as a number of the pres- caled timer/counter clocks. The minimum dead time is zero and the maximum dead time is the prescaled time/counter clock period multiplied by 15. ATtiny25/45/85 110 7 6 ...

Page 111

... The most significant bit of the USI Data Register is connected to one of two output pins (depend- ing on the mode configuration, see transparent latch between the output of the USI Data Register and the output pin, which delays 2586M–AVR–07/10 “Pinout ATtiny25/45/85” on page “Register Descriptions” on page 3 2 ...

Page 112

... The same clock also increments the USI’s 4-bit counter. The Counter Overflow (interrupt) Flag, or USIOIF, can therefore be used to determine when a transfer is completed. The clock is generated by the Master device software by toggling the USCK pin via the PORTB register or by writing a one to bit USITC bit in USICR. ATtiny25/45/85 112 Bit7 Bit6 ...

Page 113

Figure 15-3. Three-Wire Mode, Timing Diagram CYCLE USCK USCK The three-wire mode timing is shown in erence. One bit is shifted into the USI Data Register (USIDR) for each of these cycles. The USCK timing is shown for both external ...

Page 114

... The following code demonstrates how to use the USI as an SPI master with maximum speed ( SCK SPITransfer_Fast: ret 15.3.3 SPI Slave Operation Example The following code demonstrates how to use the USI as an SPI slave: init: ATtiny25/45/85 114 sbrs r16, USIOIF rjmp SPITransfer_loop in r16,USIDR ret /2): ...

Page 115

SlaveSPITransfer: SlaveSPITransfer_loop: The code is size optimized using only eight instructions (plus return). The code example assumes that the DO and USCK pins have been enabled as outputs in DDRB. The value stored in register r16 prior to the ...

Page 116

... SCL line low again (i.e., the USI Counter Register must be set to 14 before releasing SCL at (D)). Depending on the R/W bit the master or slave ATtiny25/45/85 116 shows two USI units operating in two-wire mode, one as master and one as slave. It ...

Page 117

If the bit is set, a master read operation is in progress (i.e., the slave drives the SDA line) The slave can hold the SCL line low after the acknowledge (E). 6. Multiple bytes can now be ...

Page 118

... USI less time critical and gives the CPU more time to handle other pro- gram tasks. USI flags as set similarly as when reading the USIDR register. The content of the USI Data Register is loaded to the USI Buffer Register when the transfer has been completed. ATtiny25/45/85 118 7 6 ...

Page 119

USISR – USI Status Register Bit 0x0E Read/Write Initial Value The Status Register contains interrupt flags, line status flags and the counter value. • Bit 7 – USISIF: Start Condition Interrupt Flag When two-wire mode is selected, the USISIF ...

Page 120

... USIOIE and the Global Interrupt Enable Flag are set to one the interrupt will be executed imme- diately. Refer to the USIOIF bit description on • Bits 5:4 – USIWM[1:0]: Wire Mode These bits set the type of wire mode to be used, as shown in Table 15-1. USIWM1 Note: ATtiny25/45/85 120 USISIE USIOIE USIWM1 R/W R/W R/W ...

Page 121

Basically only the function of the outputs are affected by these bits. Data and clock inputs are not affected by the mode selected and will always have the same function. The counter and USI Data Register can therefore be clocked ...

Page 122

... When an external clock source is selected (USICS1 = 1) and the USICLK bit is set to one, writ- ing to the USITC strobe bit will directly clock the 4-bit counter. This allows an early detection of when the transfer is done when operating as a master device. The bit will read as zero. ATtiny25/45/85 122 2586M–AVR–07/10 ...

Page 123

Analog Comparator The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator ...

Page 124

... When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Analog Com- parator interrupt is activated. When written logic zero, the interrupt is disabled. • Bit 2 – Res: Reserved Bit This bit is a reserved bit in the ATtiny25/45/85 and will always read as zero. ATtiny25/45/85 124 ...

Page 125

Bits 1:0 – ACIS[1:0]: Analog Comparator Interrupt Mode Select These bits determine which comparator events that trigger the Analog Comparator interrupt. The different settings are shown in Table 16-2. ACIS1 When changing the ACIS1/ACIS0 bits, ...

Page 126

... Input Polarity Reversal Mode 17.2 Overview The ATtiny25/45/85 features a 10-bit successive approximation Analog to Digital Converter (ADC). The ADC is connected to a 4-channel Analog Multiplexer which allows one differential voltage input and four single-ended voltage inputs constructed from the pins of Port B. The dif- ferential input (PB3, PB4 or PB2, PB5) is equipped with a programmable gain stage, providing amplification step (20x) on the differential input voltage before the A/D conversion ...

Page 127

Figure 17-1. Analog to Digital Converter Block Schematic V CC AREF ADC3 ADC2 ADC1 ADC0 17.3 Operation The ADC converts an analog input voltage to a 10-bit digital value through successive approxi- mation. The minimum value represents GND and the ...

Page 128

... ADC Data Register. The first conversion must be started by writing a logical one to the ADSC bit in ADCSRA. In this mode the ADC will perform successive conversions independently of whether the ADC Interrupt Flag, ADIF is cleared or not. ATtiny25/45/85 128 2586M–AVR–07/10 ...

Page 129

Figure 17-2. ADC Auto Trigger Logic If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to one. ADSC can also be used to determine if a conversion is in progress. The ADSC bit will ...

Page 130

... In this mode, the sample-and-hold takes place two ADC clock cycles after the rising edge on the trigger source signal. Three addi- tional CPU clock cycles are used for synchronization logic. ATtiny25/45/85 130 Figure 17-4 below ...

Page 131

Figure 17-6. ADC Timing Diagram, Auto Triggered Conversion Cycle Number ADC Clock Trigger Source ADATE ADIF ADCH ADCL In Free Running mode, a new conversion will be started immediately after the conversion com- pletes, while ADSC remains high. Figure 17-7. ...

Page 132

... ADC Noise Canceler The ADC features a noise canceler that enables conversion during sleep mode to reduce noise induced from the CPU core and other I/O peripherals. The noise canceler can be used with ADC ATtiny25/45/85 132 ) indicates the conversion range for the ADC. Single REF will result in codes close to 0x3FF ...

Page 133

Noise Reduction and Idle mode. To make use of this feature, the following procedure should be used: • Make sure that the ADC is enabled and is not busy converting. Single Conversion mode must be selected and the ADC conversion ...

Page 134

... Several parameters describe the deviation from the ideal behavior, as follows: • Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5 LSB). Ideal value: 0 LSB. Figure 17-9. Offset Error Output Code ATtiny25/45/85 134 and GND pins as possible. CC Section 17.7 on page 132 ...

Page 135

Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB Figure 17-10. Gain Error ...

Page 136

... Single Ended Conversion For single ended conversion, the result is where V Table 17-3 on page 138 0x3FF represents the selected voltage reference minus one LSB. The result is presented in one- sided form, from 0x3FF to 0x000. ATtiny25/45/85 136 Output Code 0x3FF 1 LSB 0x000 0 ADC ...

Page 137

Unipolar Differential Conversion If differential channels and an unipolar input mode are used, the result is where V and V REF 139). The voltage on the positive pin must always be larger than the voltage on the negative pin ...

Page 138

... ADC clock cycles. When differential channels and gain are used, using V external AREF higher than (V affect the ADC accuracy. Table 17-3. REFS2 Note: ATtiny25/45/85 138 Temperature vs. Sensor Output Voltage (Typical Case) ° -40 C 230 LSB Table 17-2 are typical values. However, due to process variation the ...

Page 139

Bit 5 – ADLAR: ADC Left Adjust Result The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register. Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted. ...

Page 140

... When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Complete Inter- rupt is activated. • Bits 2:0 – ADPS[2:0]: ADC Prescaler Select Bits These bits determine the division factor between the system clock frequency and the input clock to the ADC. Table 17-5. ADPS2 ATtiny25/45/85 140 ADEN ADSC ...

Page 141

Table 17-5. ADPS2 17.13.3 ADCL and ADCH – The ADC Data Register 17.13.3.1 ADLAR = 0 Bit 0x05 0x04 Read/Write Initial Value 17.13.3.2 ADLAR = 1 Bit 0x05 0x04 Read/Write Initial Value When an ADC conversion is complete, the result ...

Page 142

... Bits 4:3 – Res: Reserved Bits These bits are reserved bits in the ATtiny25/45/85 and will always read as zero. • Bits 2:0 – ADTS[2:0]: ADC Auto Trigger Source If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger an ADC conversion ...

Page 143

On-chip Debug System 18.1 Features • Complete Program Flow Control • Emulates All On-chip Functions, Both Digital and Analog , except RESET Pin • Real-time Operation • Symbolic Debugging Support (Both at C and Assembler Source Level, or ...

Page 144

... Read/Write Initial Value The DWDR Register provides a communication channel from the running program in the MCU to the debugger. This register is only accessible by the debugWIRE and can therefore not be used as a general purpose register in the normal operations. ATtiny25/45/85 144 will not work. CC ® ...

Page 145

Self-Programming the Flash The device provides a Self-Programming mechanism for downloading and uploading program code by the MCU itself. The Self-Programming can use any available data interface and associ- ated protocol to read code and write (program) that code ...

Page 146

... The LPM instruction uses the Z-pointer to store the address. Since this instruction addresses the Flash byte-by-byte, also the LSB (bit Z0) of the Z-pointer is used. Figure 19-1. Addressing the Flash During SPM Z - REGISTER Note: ATtiny25/45/85 146 The CPU is halted during the Page Write operation ...

Page 147

EEPROM Write Prevents Writing to SPMCSR Note that an EEPROM write operation will block all software programming to Flash. Reading the Fuses and Lock bits from software will also be prevented during the EEPROM write operation recommended ...

Page 148

... Preload SPMCSR bits into R16, then write to SPMCSR ldi out SPMCSR, r16 ; Issue LPM. Table data will be returned into r17 lpm r17, Z ret Note: If successful, the contents of the destination register are as described in section ture Imprint Table” on page ATtiny25/45/85 148 FHB7 FHB6 FHB5 Table 20-4 on page 152 for detailed description and mapping of the Fuse High Byte ...

Page 149

... Initial Value • Bits 7:6 – Res: Reserved Bits These bits are reserved bits in the ATtiny25/45/85 and always read as zero. • Bit 5 – RSIG: Read Device Signature Imprint Table Issuing an LPM instruction within three cycles after RSIG and SPMEN bits have been set in SPMCSR will return the selected data (depending on Z-pointer value) from the device signature imprint table into the destination register ...

Page 150

... SPM instruction SPM instruction is executed within four clock cycles. During Page Erase and Page Write, the SPMEN bit remains high until the operation is completed. ATtiny25/45/85 150 “EEPROM Write Prevents Writing to SPMCSR” on page 147 for details. ...

Page 151

... This section describes the different methods for Programming the ATtiny25/45/85 memories. 20.1 Program And Data Memory Lock Bits ATtiny25/45/85 provides two Lock bits which can be left unprogrammed (“1”) or can be pro- grammed (“0”) to obtain the additional security listed in “1” with the Chip Erase command, only. ...

Page 152

... Fuse Bytes ATtiny25/45/85 has three fuse bytes, as described in Note that fuses are read as logical zero, “0”, when programmed. Table 20-3. Fuse High Byte SELFPRGEN Notes: Table 20-4. Fuse High Byte RSTDISBL DWEN SPIEN WDTON EESAVE BODLEVEL2 BODLEVEL1 BODLEVEL0 Notes: ...

Page 153

Table 20-5. Fuse Low Byte CKDIV8 CKOUT SUT1 SUT0 CKSEL3 CKSEL2 CKSEL1 CKSEL0 Notes: Note that fuse bits are locked if Lock Bit 1 (LB1) is programmed. Fuse bits should be pro- grammed before lock bits. The status of fuse ...

Page 154

... ATtiny85 20.3.2 Calibration Bytes The device signature imprint table of ATtiny25/45/85 contains two bytes of calibration data for the internal RC Oscillator, as shown in calibration data for 8 MHz operation is automatically fetched and written to the OSCCAL register during reset. In ATtiny15 compatibility mode the calibration data for 6.4 MHz operation is used instead ...

Page 155

Serial Downloading Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (out- put). See below. Figure ...

Page 156

... Serial Programming Algorithm When writing serial data to the ATtiny25/45/85, data is clocked on the rising edge of SCK. When reading data from the ATtiny25/45/85, data is clocked on the falling edge of SCK. See Figure 21-4 To program and verify the ATtiny25/45/85 in the Serial Programming mode, the following sequence is recommended (see four byte instruction formats in 1 ...

Page 157

Serial Programming Instruction set Table 20-11. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location Symbol t WD_FLASH t WD_EEPROM t WD_ERASE t WD_FUSE Table 20-12 on page 157 Table 20-12. Serial Programming Instruction Set Instruction/Operation Programming ...

Page 158

... Adr Adr MSB Bit 15 B 20.6 High-voltage Serial Programming This section describes how to program and verify Flash Program memory, EEPROM Data mem- ory, Lock bits and Fuse bits in the ATtiny25/45/85. ATtiny25/45/85 158 Serial Programming Instruction Byte 4 Byte 1 Adr LSB 0 Page Buffer ...

Page 159

... SII SDO 20.7 High-voltage Serial Programming Algorithm To program and verify the ATtiny25/45/85 in the High-voltage Serial Programming mode, the fol- lowing sequence is recommended (See instruction formats in 20.7.1 Enter High-voltage Serial Programming Mode The following algorithm puts the device in High-voltage Serial Programming mode: 1 ...

Page 160

... Chip Erase The Chip Erase will erase the Flash and EEPROM not reset until the Program memory has been completely erased. The Fuse bits are not ATtiny25/45/85 160 is unable to fulfill the requirements listed above, the following alterna- CC Table 20-14 to “ ...

Page 161

... Repeat 2 through 3 until the entire Flash is programmed or until all data has been programmed. 5. End Page Programming by Loading Command “No Operation”. When writing or reading serial data to the ATtiny25/45/85, data is clocked on the rising edge of the serial clock, see Figure 20-4. Addressing the Flash which is Organized in Pages 2586M– ...

Page 162

... The algorithms for programming and reading the Fuse Low/High bits and Lock bits are shown in Table 20-16. 20.7.9 Reading the Signature Bytes and Calibration Byte The algorithms for reading the Signature bytes and Calibration byte are shown in 20.7.10 Power-off sequence Set SCI to “0”. Set RESET to “1”. Turn V ATtiny25/45/85 162 Table 20-16): ...

Page 163

... Table 20-16. High-voltage Serial Programming Instruction Set for ATtiny25/45/85 Instruction Instr.1/5 SDI 0_1000_0000_00 Chip Erase SII 0_0100_1100_00 SDO x_xxxx_xxxx_xx SDI 0_0001_0000_00 Load “Write Flash” SII 0_0100_1100_00 Command SDO x_xxxx_xxxx_xx SDI 0_bbbb_bbbb _00 SII 0_0000_1100_00 SDO x_xxxx_xxxx_xx Load Flash Page Buffer ...

Page 164

... Table 20-16. High-voltage Serial Programming Instruction Set for ATtiny25/45/85 (Continued) Instruction Instr.1/5 SDI 0_bbbb_bbbb_00 SII 0_0000_1100_00 Write SDO x_xxxx_xxxx_xx EEPROM SDI 0_0000_0000_00 Byte SII 0_0110_0100_00 SDO x_xxxx_xxxx_xx SDI 0_0000_0011_00 Load “Read EEPROM” SII 0_0100_1100_00 Command SDO x_xxxx_xxxx_xx SDI 0_bbbb_bbbb_00 Read ...

Page 165

Notes address high bits address low bits data in high bits data in low bits data out high bits data out low bits don’t care, ...

Page 166

... Input High-voltage, V IH3 RESET pin as I/O (4) Output Low-voltage (6) Port B (except RESET) (5) Output High-voltage (6) Port B (except RESET) Input Leakage I IL Current I/O Pin Input Leakage I IH Current I/O Pin ATtiny25/45/85 166 *NOTICE: +0. -40°C to +85°C A Condition V = 1. 2. 1. 2. 1. ...

Page 167

Table 21-1. DC Characteristics. T Symbol Parameter R Reset Pull-up Resistor RST R I/O Pin Pull-up Resistor pu (7) Power Supply Current I CC (8) Power-down mode Notes: 1. Typical values at 25°C. 2. “Min” means the lowest value where ...

Page 168

... Speed Figure 21-1. Maximum Frequency vs MHz 4 MHz 1.8V Figure 21-2. Maximum Frequency vs MHz 10 MHz ATtiny25/45/85 168 CC Safe Operating Area 2.7V CC Safe Operating Area 2.7V 4.5V 5.5V 5.5V 2586M–AVR–07/10 ...

Page 169

... V CC (2) 3V Fixed voltage within: (3) 1.8V - 5.5V (4) 2.7V - 5.5V 1. Accuracy of oscillator frequency at calibration point (fixed temperature and fixed voltage). 2. ATtiny25/V, only: 6.4 MHz in ATtiny15 Compatibility Mode. 3. Voltage range for ATtiny25V/45V/85V. 4. Voltage range for ATtiny25/45/85. V IH1 V = 1.8 - 5.5V CC Min. 0 250 100 ...

Page 170

... Two versions of power-on reset have been implemented, as follows. 21.5.1 Standard Power-On Reset This implementation of power-on reset existed in early versions of ATtiny25/45/85. The table below describes the characteristics of this power-on reset and it is valid for the following devices, only: • ATtiny25, revision D, and older • ...

Page 171

... Enhanced Power-On Reset This implementation of power-on reset exists in newer versions of ATtiny25/45/85. The table below describes the characteristics of this power-on reset and it is valid for the following devices, only: • ATtiny25, revision E, and newer • ATtiny45, revision G, and newer • ATtiny85, revision C, and newer Table 21-6 ...

Page 172

... IN Input Bandwidth AREF External Reference Voltage Internal Voltage Reference V INT Internal 2.56V Reference R REF R Analog Input Resistance AIN ADC Output Note: 1. Values are guidelines only. ATtiny25/45/85 172 = -40°C to +85°C A Condition 4V, REF CC ADC clock = 200 kHz 4V, REF CC ADC clock = 1 MHz ...

Page 173

Table 21-9. ADC Characteristics, Differential Channels (Unipolar Mode). T Symbol Parameter Resolution Absolute accuracy (Including INL, DNL, and Quantization, Gain and Offset Errors) Integral Non-Linearity (INL) (Accuracy after Offset and Gain Calibration) Gain Error Offset Error Conversion Time Clock Frequency ...

Page 174

... External Reference Voltage Internal Voltage Reference V INT Internal 2.56V Reference R Reference Input Resistance REF R Analog Input Resistance AIN ADC Conversion Output Note: 1. Values are guidelines only. ATtiny25/45/85 174 Condition Gain = 1x Gain = 20x Gain = 4V REF CC ADC clock = 50 - 200 kHz Gain = 20x V = 4V, V ...

Page 175

Serial Programming Characteristics Figure 21-4. Serial Programming Waveforms SERIAL DATA OUTPUT SERIAL CLOCK INPUT Figure 21-5. Serial Programming Timing Table 21-11. Serial Programming Characteristics, T Symbol 1/t CLCL t CLCL 1/t CLCL t CLCL 1/t CLCL t CLCL t ...

Page 176

... SHSL t SLSH t IVSH t SHIX t SHOV t WLWH_PFB ATtiny25/45/85 176 t IVSH SCI (PB3) SDO (PB2) 10% (Unless otherwise noted) Parameter SCI (PB3) Pulse Width High SCI (PB3) Pulse Width Low SDI (PB0), SII (PB1) Valid to SCI (PB3) High SDI (PB0), SII (PB1) Hold after SCI (PB3) High SCI (PB3) High to SDO (PB2) Valid Wait after Instr ...

Page 177

Typical Characteristics The data contained in this section is largely based on simulations and characterization of similar devices in the same process and design methods. Thus, the data should be treated as indica- tions of how the part will ...

Page 178

... Figure 22-2. Active Supply Current vs. Frequency ( MHz) Figure 22-3. Active Supply Current vs. V ATtiny25/45/85 178 ACTIVE SUPPLY CURRENT vs. FREQUENCY MHz 1. Frequency (MHz) (Internal RC oscillator, 8 MHz) CC ACTIVE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 8 MHz 1 4.0V 3.3V 2. 3,5 4 4,5 5 5,5 ( ...

Page 179

Figure 22-4. Active Supply Current vs. V Figure 22-5. Active Supply Current vs. V 2586M–AVR–07/10 CC ACTIVE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 1 MHz 1,6 1,4 1,2 1 0,8 0,6 0,4 0,2 0 1 ...

Page 180

... Idle Supply Current Figure 22-6. Idle Supply Current vs. low Frequency (0.1 - 1.0 MHz) Figure 22-7. Idle Supply Current vs. Frequency ( MHz) ATtiny25/45/85 180 IDLE SUPPLY CURRENT vs. LOW FREQUENCY 0.1 - 1.0 MHz 0,25 0,2 0,15 0,1 0, 0,1 0,2 0,3 0,4 Frequency (MHz) IDLE SUPPLY CURRENT vs ...

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Figure 22-8. Idle Supply Current vs. V Figure 22-9. Idle Supply Current vs. V 2586M–AVR–07/10 (Internal RC Oscillator, 8 MHz)I CC IDLE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 8 MHz 1,8 1,6 1,4 1,2 1 0,8 0,6 0,4 0,2 ...

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... Power Reduction Register. See page 39 Table 22-1. PRR bit PRTIM1 PRTIM0 PRUSI PRADC Table 22-2. PRR bit PRTIM1 PRTIM0 PRUSI PRADC ATtiny25/45/85 182 (Internal RC Oscillator, 128 kHz) CC IDLE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 128 kHz 0,1 0,09 0,08 0,07 0,06 0,05 0,04 0,03 ...

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It is possible to calculate the typical current consumption based on the numbers from for other V 22.3.1 Example Calculate the expected current consumption in idle mode with USI, TIMER0, and ADC enabled add 10% for ...

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... Figure 22-12. Power-down Supply Current vs. V 22.5 Pin Pull-up Figure 22-13. I/O Pin Pull-up Resistor Current vs. Input Voltage (V ATtiny25/45/85 184 POWER-DOWN SUPPLY CURRENT vs. V WATCHDOG TIMER ENABLED 1 I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE 0,2 0,4 0,6 0,8 V (Watchdog Timer Enabled) ...

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Figure 22-14. I/O Pin Pull-up Resistor Current vs. Input Voltage (V Figure 22-15. I/O Pin Pull-up Resistor Current vs. Input Voltage (V 2586M–AVR–07/10 I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE ...

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... Figure 22-16. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V Figure 22-17. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V ATtiny25/45/85 186 RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE 0,2 0,4 0,6 0,8 V RESET RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE 0 RESET = 1.8V ...

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Figure 22-18. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V 22.6 Pin Driver Strength Figure 22-19. I/O Pin Output Voltage vs. Sink Current (V 2586M–AVR–07/10 RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE 120 100 ...

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... Figure 22-20. I/O Pin Output Voltage vs. Sink Current (V Figure 22-21. I/O Pin Output Voltage vs. Source Current (V ATtiny25/45/85 188 I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT V CC 0,6 0,5 0,4 0,3 0,2 0 I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT V CC 3,5 3 2,5 2 1,5 1 0,5 ...

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Figure 22-22. I/O Pin Output Voltage vs. Source Current (V Figure 22-23. Reset Pin Output Voltage vs. Sink Current (V 2586M–AVR–07/10 I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT V 5,1 5 4,9 4,8 4,7 4,6 4,5 4 ...

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... Figure 22-24. Reset Pin Output Voltage vs. Sink Current (V Figure 22-25. Reset Pin Output Voltage vs. Source Current (V ATtiny25/45/85 190 RESET AS I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT 1 0.8 0.6 0.4 0 0 RESET AS I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT 3.5 3 2.5 2 1.5 1 0.5 ...

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Figure 22-26. Reset Pin Output Voltage vs. Source Current (V 22.7 Pin Threshold and Hysteresis Figure 22-27. I/O Pin Input Threshold Voltage vs. V 2586M–AVR–07/10 RESET AS I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT 5 4.5 4 3.5 3 2.5 ...

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... Figure 22-28. I/O Pin Input Threshold Voltage vs. V Figure 22-29. I/O Pin Input Hysteresis vs. V ATtiny25/45/85 192 I/O PIN INPUT THRESHOLD VOLTAGE vs. V VIL, IO PIN READ AS '0' 3 2,5 2 1,5 1 0,5 0 1 I/O PIN INPUT HYSTERESIS vs. VCC 0,6 0,5 0,4 0,3 ...

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Figure 22-30. Reset Input Threshold Voltage vs. V Figure 22-31. Reset Input Threshold Voltage vs. V 2586M–AVR–07/10 RESET INPUT THRESHOLD VOLTAGE vs. VCC VIH, IO PIN READ AS '1' 2,5 2 1,5 1 0,5 0 1,5 2 2,5 3 VCC ...

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... Figure 22-32. Reset Pin Input Hysteresis vs. V 22.8 BOD Threshold Figure 22-33. BOD Threshold vs. Temperature (BOD Level is 4.3V) ATtiny25/45/85 194 RESET PIN INPUT HYSTERESIS vs. VCC 0,5 0,45 0,4 0,35 0,3 0,25 0,2 0,15 0,1 0,05 0 1,5 2 2,5 3 BOD THRESHOLDS vs. TEMPERATURE 4,4 ...

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Figure 22-34. BOD Threshold vs. Temperature (BOD Level is 2.7V) Figure 22-35. BOD Threshold vs. Temperature (BOD Level is 1.8V) 2586M–AVR–07/10 BOD THRESHOLDS vs. TEMPERATURE 2,8 2,78 2,76 2,74 2,72 2,7 2,68 -50 -40 -30 -20 - Temperature ...

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... Figure 22-37. Bandgap Voltage vs. Temperature 1,2 1,18 1,16 1,14 1,12 1,1 1,08 1,06 1,04 1,02 1 ATtiny25/45/85 196 BANDGAP VOLTAGE vs. V 1,5 2 2,5 3 BANDGAP VOLTAGE vs. Temperature -40 - 3,5 4 4,5 5 Vcc ( Temperature 85 °C 25 °C -40 ° ...

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Internal Oscillator Speed Figure 22-38. Watchdog Oscillator Frequency vs. V Figure 22-39. Watchdog Oscillator Frequency vs. Temperature 2586M–AVR–07/10 WATCHDOG OSCILLATOR FREQUENCY vs. V 0,128 0,126 0,124 0,122 0,12 0,118 0,116 0,114 0,112 2 2,5 3 3,5 WATCHDOG OSCILLATOR FREQUENCY ...

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... Figure 22-40. Calibrated 8 MHz RC Oscillator Frequency vs. V Figure 22-41. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature ATtiny25/45/85 198 CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. V 8,2 8,1 8 7,9 7,8 7,7 7,6 7,5 1,5 2 2,5 3 CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 8,15 8,1 8,05 8 7,95 7,9 7,85 ...

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Figure 22-42. Calibrated 8 MHz RC Oscillator Frequency vs. OSCCAL Value Figure 22-43. Calibrated 1.6 MHz RC Oscillator Frequency vs. V 2586M–AVR–07/10 CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE ...

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... Figure 22-44. Calibrated 1.6 MHz RC Oscillator Frequency vs. Temperature Figure 22-45. Calibrated 1.6 MHz RC Oscillator Frequency vs. OSCCAL Value ATtiny25/45/85 200 CALIBRATED 1.6MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 1,64 1,62 1,6 1,58 1,56 1,54 1,52 1,5 -60 -40 -20 0 Temperature CALIBRATED 1.6 MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE ...

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