ATTINY48-MMU Atmel, ATTINY48-MMU Datasheet



Manufacturer Part Number
AVR® ATtinyr

Specifications of ATTINY48-MMU

Core Processor
Core Size
Brown-out Detect/Reset, POR, WDT
Number Of I /o
Program Memory Size
4KB (2K x 16)
Program Memory Type
Eeprom Size
64 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Processor Series
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
2-Wire, I2S, SPI
Maximum Clock Frequency
12 MHz
Number Of Programmable I/os
Number Of Timers
Maximum Operating Temperature
+ 85 C
Mounting Style
3rd Party Development Tools
Development Tools By Supplier
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
Device Core
Family Name
Maximum Speed
12 MHz
Operating Supply Voltage
2.5|3.3|5 V
For Use With
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
High Performance, Low Power AVR
Advanced RISC Architecture
High Endurance Non-volatile Memory Segments
Peripheral Features
Special Microcontroller Features
I/O and Packages
Operating Voltage:
Temperature Range:
Speed Grade:
Low Power Consumption
– 123 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– 4K/8K Bytes of In-System Self-Programmable Flash Program Memory
– 64/64 Bytes EEPROM
– 256/512 Bytes Internal SRAM
– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
– Data Retention: 20 years at 85°C / 100 years at 25°C
– Programming Lock for Software Security
– One 8-bit Timer/Counter with Separate Prescaler and Compare Mode
– One 16-bit Timer/Counter with Prescaler, and Compare and Capture Modes
– 6- or 8-channel 10-bit ADC
– Master/Slave SPI Serial Interface
– Byte-oriented 2-wire Serial Interface (Philips I
– Programmable Watchdog Timer with Separate On-Chip Oscillator
– On-Chip Analog Comparator
– Interrupt and Wake-up on Pin Change
– debugWIRE On-Chip Debug System
– In-System Programmable via SPI Port
– Power-On Reset and Programmable Brown-Out Detection
– Internal Calibrated Oscillator
– External and Internal Interrupt Sources
– Three Sleep Modes: Idle, ADC Noise Reduction and Power-Down
– On-Chip Temperature Sensor
– 24 Programmable I/O Lines:
– 28 Programmable I/O Lines:
– 1.8
– -40
– 0
– 0
– 0
– Active Mode: 1 MHz, 1.8V: 240 µA
– Power-Down Mode: 0.1 µA at 1.8V
• 28-pin PDIP
• 28-pad QFN/MLF
• 32-lead TQFP
• 32-pad QFN/MLF
• 32-ball UFBGA
4 MHz @ 1.8
8 MHz @ 2.7
12 MHz @ 4.5
C to +85
8-Bit Microcontroller
C Compatible)
with 4/8K Bytes
Rev. 8008FS–AVR–06/10

Related parts for ATTINY48-MMU

ATTINY48-MMU Summary of contents

Page 1

... MHz @ 4.5 5.5V • Low Power Consumption – Active Mode: 1 MHz, 1.8V: 240 µA – Power-Down Mode: 0.1 µA at 1.8V ® 8-Bit Microcontroller 2 C Compatible) 8-bit Microcontroller with 4/8K Bytes In-System Programmable Flash ATtiny48/88 Preliminary Summary Rev. 8008FS–AVR–06/10 ...

Page 2

... PC1 (ADC1/PCINT9) 19 PC0 (ADC0/PCINT8 GND (PCINT27) PA3 5 17 PC7 (PCI NT15) (PCINT6/CLKI) PB6 6 16 AVCC PB5 (SCK/PCINT5 NOTE: Bottom pad should be soldered to ground. 32UFBGA - Pinout ATtiny48/ PD2 PD1 PC6 PC4 PD3 PD4 PD0 PC5 GND PA2 VDD PA3 PB6 PD6 PB0 ...

Page 3

Pin Descriptions 1.1.1 VCC Digital supply voltage. 1.1.2 GND Ground. 1.1.3 Port A (PA3:0) (in 32-lead TQFP and 32-pad QFN/MLF packages, only) Port 4-bit bi-directional I/O port with internal pull-up resistors (selected for each bit) in ...

Page 4

... V Canceling Techniques” on page The following pins receive their supply voltage from AV ages) PA[1:0]. All other I/O pins take their supply voltage from V ATtiny48/88 4 “Alternate Functions of Port D” on page even if the ADC is not used. If the ADC is used recom- ...

Page 5

... Overview The ATtiny48/ low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny48/88 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power con- sumption versus processing speed. 2.1 Block Diagram Figure 2-1 ...

Page 6

... Programmable Flash on a monolithic chip, the Atmel ATtiny48/ powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATtiny48/88 AVR is supported by a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators and evaluation kits. ...

Page 7

... General Information 3.1 Resources A comprehensive set of development tools, application notes and datasheets are available for download at 3.2 About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation ...

Page 8

... Reserved – (0xC4) Reserved – (0xC3) Reserved – (0xC2) Reserved – (0xC1) Reserved – (0xC0) Reserved – (0xBF) Reserved – ATtiny48/88 8 Bit 6 Bit 5 Bit 4 Bit 3 – – – – – – – – – – – – – – – ...

Page 9

Address Name Bit 7 (0xBE) TWHSR – (0xBD) TWAMR TWAM6 (0xBC) TWCR TWINT (0xBB) TWDR (0xBA) TWAR TWA6 (0xB9) TWSR TWS7 (0xB8) TWBR (0xB7) Reserved – (0xB6) Reserved – (0xB5) Reserved – (0xB4) Reserved – (0xB3) Reserved – (0xB2) Reserved ...

Page 10

... EEARL 0x20 (0x40) EEDR 0x1F (0x3F) EECR – 0x1E (0x3E) GPIOR0 0x1D (0x3D) EIMSK – 0x1C (0x3C) EIFR – 0x1B (0x3B) PCIFR – ATtiny48/88 10 Bit 6 Bit 5 Bit 4 Bit 3 REFS0 ADLAR – MUX3 ACME – – ADSC ADATE ADIF ADIE ADC Data Register High byte ADC Data Register Low byte – ...

Page 11

... When using the I/O specific commands IN and OUT, the I/O addresses 0x00 Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The ATtiny48/ com- plex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions ...

Page 12

... Clear Bit in I/O Register LSL Rd Logical Shift Left LSR Rd Logical Shift Right ROL Rd Rotate Left Through Carry ROR Rd Rotate Right Through Carry ATtiny48/88 12 Description Rd ← ← Rdh:Rdl ← Rdh:Rdl + K Rd ← ← ← ← Rdh:Rdl ← Rdh:Rdl - K Rd ← Rd • ← Rd • ← ...

Page 13

Mnemonics Operands ASR Rd Arithmetic Shift Right SWAP Rd Swap Nibbles BSET s Flag Set BCLR s Flag Clear BST Rr, b Bit Store from Register to T BLD Rd, b Bit load from T to Register SEC Set Carry ...

Page 14

... Array), 0.50 mm Pitch 0.6 mm, Ultra Thin, Fine-Pitch Ball Grid Array Package (UFBGA) 32M1-A 32-pad 1.0 body, Lead Pitch 0.50 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) ATtiny48/88 14 (1) Ordering Code Package ATtiny48-MMU 28M1 ATtiny48-MMH 28M1 ATtiny48-MMHR 28M1 ATtiny48-PU 28P3 ATtiny48-AU ...

Page 15

... All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazard- ous Substances (RoHS). 3. These devices can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering informa- tion and minimum quantities. ...

Page 16

... Pin TOP VIEW 0.20 b 0.4 Ref BOTTOM VIEW (4x) The terminal # Laser-marked Feature. Note: Package Drawing Contact: ATtiny48/ 0. TITLE 28M1, 28-pad 1.0 mm Body, Lead Pitch 0.45 mm, 2.4 x 2.4 mm Exposed Pad, Thermally Enhanced Plastic Very Thin Quad Flat No Lead Package (VQFN) C SIDE VIEW ...

Page 17

A SEATING PLANE Note: 1. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). 2325 Orchard Parkway San Jose, CA 95131 R 8008F–AVR–06/10 ...

Page 18

... This package conforms to JEDEC reference MS-026, Variation ABA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. 2325 Orchard Parkway San Jose, CA 95131 R ATtiny48/ PIN 1 IDENTIFIER ...

Page 19

... A1 BALL CORNER Note1: Dimension “b” is measured at the maximum ball dia plane parallel to the seating plane. Note2: Dimension “b1” is the solderable surface defined by the opening of the solder resist layer. Package Drawing Contact: 8008F–AVR–06/10 Pin TOP VIEW E1 e 32-Øb ...

Page 20

... Pin TOP VIEW Pin #1 Notch (0. BOTTOM VIEW Note: JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2. 2325 Orchard Parkway San Jose, CA 95131 R ATtiny48/ TITLE 32M1-A, 32-pad 1.0 mm Body, Lead Pitch 0.50 mm, 3.10 mm Exposed Pad, Micro Lead Frame Package (MLF) SIDE VIEW ...

Page 21

... Errata 8.1 ATtiny48 8.1.1 Rev known errata. 8.1.2 Rev. B Not sampled. 8.1.3 Rev. A Not sampled. 8008F–AVR–06/10 21 ...

Page 22

... ATtiny88 8.2.1 Rev known errata. 8.2.2 Rev known errata. 8.2.3 Rev. A Not sampled. ATtiny48/88 22 8008F–AVR–06/10 ...

Page 23

Datasheet Revision History Please note that page references in this section refer to the current revision of this document. 9.1 Rev. 8008F - 06/10 1. Updated notes 1 and 10 in table in 2. Updated package drawing in 3. ...

Page 24

... Rev. 8008B - 06/08 1. Updated introduction of 2. Updated 3. Added 9.6 Rev. 8008A - 06/08 1. Initial revision. ATtiny48/88 24 “Programming the Lock Bits” on page 198 “Absolute Maximum Ratings*” on page 204 “DC Characteristics” on page 204 “Speed” on page 206 “Register Summary” on page 8 “ ...

Page 25

8008F–AVR–06/10 25 ...

Page 26

... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...

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