ATMEGA48V-10MMU Atmel, ATMEGA48V-10MMU Datasheet - Page 19

MCU AVR 4K FLASH 10MHZ 28-QFN

ATMEGA48V-10MMU

Manufacturer Part Number
ATMEGA48V-10MMU
Description
MCU AVR 4K FLASH 10MHZ 28-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA48V-10MMU

Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Processor Series
ATMEGA48x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
2-Wire, SPI, USART, Serial
Maximum Clock Frequency
10 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
28MLF EP
Device Core
AVR
Family Name
ATmega
Maximum Speed
10 MHz
Operating Supply Voltage
2.5|3.3|5 V
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVR
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA48V-10MMU
Manufacturer:
ZILOG
Quantity:
1
7.4
7.4.1
7.4.2
2545S–AVR–07/10
EEPROM Data Memory
EEPROM Read/Write Access
Preventing EEPROM Corruption
Figure 7-4.
The ATmega48/88/168 contains 256/512/512 bytes of data EEPROM memory. It is organized
as a separate data space, in which single bytes can be read and written. The EEPROM has an
endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the
CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM
Data Register, and the EEPROM Control Register.
“Memory Programming” on page 284
in SPI or Parallel Programming mode.
The EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in
lets the user software detect when the next byte can be written. If the user code contains instruc-
tions that write the EEPROM, some precautions must be taken. In heavily filtered power
supplies, V
period of time to run at a voltage lower than specified as minimum for the clock frequency used.
See
situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed.
During periods of low V
too low for the CPU and the EEPROM to operate properly. These issues are the same as for
board level systems using EEPROM, and the same design solutions should be applied.
“Preventing EEPROM Corruption” on page 19
CC
Address
clk
is likely to rise or fall slowly on power-up/down. This causes the device for some
On-chip Data SRAM Access Cycles
Data
Data
WR
CPU
RD
CC,
the EEPROM data can be corrupted because the supply voltage is
Compute Address
T1
Memory Access Instruction
contains a detailed description on EEPROM Programming
Address valid
for details on how to avoid problems in these
T2
Table
7-2. A self-timing function, however,
ATmega48/88/168
Next Instruction
T3
19

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