ATMEGA48V-10MMU Atmel, ATMEGA48V-10MMU Datasheet - Page 276

MCU AVR 4K FLASH 10MHZ 28-QFN

ATMEGA48V-10MMU

Manufacturer Part Number
ATMEGA48V-10MMU
Description
MCU AVR 4K FLASH 10MHZ 28-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA48V-10MMU

Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Processor Series
ATMEGA48x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
2-Wire, SPI, USART, Serial
Maximum Clock Frequency
10 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
28MLF EP
Device Core
AVR
Family Name
ATmega
Maximum Speed
10 MHz
Operating Supply Voltage
2.5|3.3|5 V
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVR
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA48V-10MMU
Manufacturer:
ZILOG
Quantity:
1
26.8.7
26.8.8
26.8.9
276
ATmega48/88/168
Setting the Boot Loader Lock Bits by SPM
EEPROM Write Prevents Writing to SPMCSR
Reading the Fuse and Lock Bits from Software
RWWSB by writing the RWWSRE. See
page 278
To set the Boot Loader Lock bits and general lock bits, write the desired data to R0, write
“X0001001” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR.
See
Flash access.
If bits 5..0 in R0 are cleared (zero), the corresponding Boot Lock bit and general lock bit will be
programmed if an SPM instruction is executed within four cycles after BLBSET and SELFPR-
GEN are set in SPMCSR. The Z-pointer is don’t care during this operation, but for future
compatibility it is recommended to load the Z-pointer with 0x0001 (same as used for reading the
lO
writing the Lock bits. When programming the Lock bits the entire Flash can be read during the
operation.
Note that an EEPROM write operation will block all software programming to Flash. Reading the
Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It
is recommended that the user checks the status bit (EEPE) in the EECR Register and verifies
that the bit is cleared before writing to the SPMCSR Register.
It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the
Z-pointer with 0x0001 and set the BLBSET and SELFPRGEN bits in SPMCSR. When an LPM
instruction is executed within three CPU cycles after the BLBSET and SELFPRGEN bits are set
in SPMCSR, the value of the Lock bits will be loaded in the destination register. The BLBSET
and SELFPRGEN bits will auto-clear upon completion of reading the Lock bits or if no LPM
instruction is executed within three CPU cycles or no SPM instruction is executed within four
CPU cycles. When BLBSET and SELFPRGEN are cleared, LPM will work as described in the
Instruction set Manual.
The algorithm for reading the Fuse Low byte is similar to the one described above for reading
the Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and set the BLBSET
and SELFPRGEN bits in SPMCSR. When an LPM instruction is executed within three cycles
after the BLBSET and SELFPRGEN bits are set in the SPMCSR, the value of the Fuse Low byte
(FLB) will be loaded in the destination register as shown below. Refer to
for a detailed description and mapping of the Fuse Low byte.
Similarly, when reading the Fuse High byte, load 0x0003 in the Z-pointer. When an LPM instruc-
tion is executed within three cycles after the BLBSET and SELFPRGEN bits are set in the
SPMCSR, the value of the Fuse High byte (FHB) will be loaded in the destination register as
Bit
R0
Bit
Rd
Bit
Rd
ck
bits). For future compatibility it is also recommended to set bits 7 and 6 in R0 to “1” when
Table 26-2
for an example.
FLB7
and
7
1
7
7
Table 26-3
FLB6
6
1
6
6
for how the different settings of the Boot Loader bits affect the
BLB12
BLB12
FLB5
5
5
5
“Simple Assembly Code Example for a Boot Loader” on
BLB11
BLB11
FLB4
4
4
4
BLB02
BLB02
FLB3
3
3
3
BLB01
BLB01
FLB2
2
2
2
FLB1
LB2
LB2
Table 27-5 on page 286
1
1
1
FLB0
LB1
LB1
0
0
0
2545S–AVR–07/10

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