ATMEGA88A-MMH Atmel, ATMEGA88A-MMH Datasheet - Page 175

• Manufacturer Part Number: ATMEGA88A-MMH
• Description: IC MCU AVR 8K FLASH 28QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA88A-MMH

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

18.5.2
8271C–AVR–08/10
SPSR – SPI Status Register
• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0
These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have
no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency f
shown in the following table:
Table 18-5.
• Bit 7 – SPIF: SPI Interrupt Flag
When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if SPIE in
SPCR is set and global interrupts are enabled. If SS is an input and is driven low when the SPI is
in Master mode, this will also set the SPIF Flag. SPIF is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the
SPI Status Register with SPIF set, then accessing the SPI Data Register (SPDR).
• Bit 6 – WCOL: Write COLlision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The
WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register with WCOL set,
and then accessing the SPI Data Register.
• Bit 5...1 – Reserved
These bits are reserved bits in the ATmega48A/48PA/88A/88PA/168A/168PA/328/328P and will
always read as zero.
• Bit 0 – SPI2X: Double SPI Speed Bit
When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI
is in Master mode (see
clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work at f
or lower.
The SPI interface on the ATmega48A/48PA/88A/88PA/168A/168PA/328/328P is also used for
program memory and EEPROM downloading or uploading. See
ming and verification.
ATmega48A/48PA/88A/88PA/168A/168PA/328/328
Bit
0x2D (0x4D)
Read/Write
Initial Value
SPI2X
0
0
0
0
1
1
1
1
Relationship Between SCK and the Oscillator Frequency
SPIF
R
7
0
Table
WCOL
SPR1
R
6
0
0
0
1
1
0
0
1
1
18-5). This means that the minimum SCK period will be two CPU
R
5
–
0
SPR0
R
4
–
0
0
1
0
1
0
1
0
1
R
3
–
0
SCK Frequency
f
f
f
f
f
f
f
f
osc
osc
osc
osc
osc
osc
osc
osc
/
/
/
/
/
/
/
/
4
16
64
128
2
8
32
64
R
2
–
0
page 311
R
1
–
0
for serial program-
SPI2X
R/W
0
0
SPSR
osc
osc
175
/4
is