AT89LS52-16PU Atmel, AT89LS52-16PU Datasheet
AT89LS52-16PU
Specifications of AT89LS52-16PU
Available stocks
Related parts for AT89LS52-16PU
AT89LS52-16PU Summary of contents
Page 1
... RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89LS52 is designed with static logic for opera- tion down to zero frequency and supports two software selectable power saving modes ...
Page 2
... RST 10 (RXD) P3 (TXD) P3.1 13 (INT0) P3.2 14 (INT1) P3.3 15 (T0) P3.4 16 (T1) P3.5 17 AT89LS52 2 2.3 44-lead TQFP VCC P0.0 (AD0) P0.1 (AD1) P0.2 (AD2) P0.3 (AD3) (MOSI) P1.5 P0.4 (AD4) (MISO) P1.6 (SCK) P1.7 P0.5 (AD5) P0.6 (AD6) (RXD) P3.0 P0.7 (AD7) EA/VPP (TXD) P3 ...
Page 3
... LATCH ACC TMP2 TMP1 ALU INTERRUPT, SERIAL PORT, AND TIMER BLOCKS PSW INSTRUCTION REGISTER WATCH PORT 3 DOG LATCH PORT 3 DRIVERS P3.0 - P3.7 AT89LS52 P2.0 - P2.7 PORT 2 DRIVERS PORT 2 FLASH LATCH PROGRAM STACK ADDRESS POINTER REGISTER BUFFER PC INCREMENTER PROGRAM COUNTER DUAL DPTR ...
Page 4
... DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. AT89LS52 4 ) because of the internal pull-ups. IL ...
Page 5
... As inputs, Port 3 pins that are externally being pulled low will source current (I Port 3 receives some control signals for Flash programming and verification. Port 3 also serves the functions of various special features of the AT89LS52, as shown in the following table. Port Pin P3 ...
Page 6
... T2MOD (shown in Capture/Reload registers for Timer 2 in 16-bit capture mode or 16-bit auto-reload mode. Interrupt Registers: The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the six interrupt sources in the IP register. AT89LS52 6 for internal program executions. CC Table 10-2) for Timer 2 ...
Page 7
... Table 5-1. AT89LS52 SFR Map and Reset Values 0F8H B 0F0H 00000000 0E8H ACC 0E0H 00000000 0D8H PSW 0D0H 00000000 T2CON T2MOD 0C8H 00000000 XXXXXX00 0C0H IP 0B8H XX000000 P3 0B0H 11111111 IE 0A8H 0X000000 P2 0A0H 11111111 SCON SBUF 98H 00000000 XXXXXXXX P1 90H 11111111 TCON ...
Page 8
... Capture/Reload select. CP/RL2 = 1 causes captures to occur on negative transitions at T2EX if EXEN2 = 1. CP/RL2 = 0 CP/RL2 causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX when EXEN2 = 1. When either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow. AT89LS52 8 RCLK TCLK ...
Page 9
... Power Off Flag: The Power Off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR. POF is set to “1” during power up. It can be set and rest under software control and is not affected by reset. 2601C–MICRO–06/08 – – WDIDLE DISRTO AT89LS52 Reset Value = XXX00XX0B – – DISALE ...
Page 10
... Data Memory The AT89LS52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. This means that the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space. ...
Page 11
... WDT continues to count if enabled. The WDT keeps counting during IDLE (WDIDLE bit = 0) as the default state. To prevent the WDT from resetting the AT89LS52 while in IDLE mode, the user should always set up a timer that will periodically exit IDLE, service the WDT, and reenter IDLE mode ...
Page 12
... AT89C52. For further information on the UART operation, please click on the document link below: http://www.atmel.com/dyn/resources/prod_documents/DOC4316.PDF 9. Timer 0 and 1 Timer 0 and Timer 1 in the AT89LS52 operate the same way as Timer 0 and Timer 1 in the AT89C51 and AT89C52. For further information on the timers’ operation, please click on the document link below: http://www.atmel.com/dyn/resources/prod_documents/DOC4316.PDF 10 ...
Page 13
... C/ CONTROL TR2 C/ CAPTURE CONTROL EXEN2 Table 10-2). Upon reset, the DCEN bit is set that timer 2 will default to shows Timer 2 automatically counting up when DCEN=0. In this mode, two options TH2 TL2 TF2 OVERFLOW RCAP2H RCAP2L TIMER 2 INTERRUPT EXF2 Figure AT89LS52 10-2. In this 13 ...
Page 14
... Not Bit Addressable – – Bit 7 6 Symbol Function – Not implemented, reserved for future T2OE Timer 2 Output Enable bit DCEN When set, this bit allows Timer configured as an up/down counter AT89LS52 14 C/ TH2 CONTR OL TR2 C/ RELO AD RCAP2H CONTROL EXEN2 – – – ...
Page 15
... RCAP2H EXF2 CONTROL EXEN2 TOGGLE 0FFH OVERFLOW TL2 TF2 TIMER 2 INTERRUPT COUNT DIRECTION 1=UP 0=DOWN T2EX PIN TIMER 1 OVERFLOW ÷ 2 "0" "1" SMOD1 "1" "0" TL2 RCLK ÷ "1" "0" TCLK RCAP2L ÷ TIMER 2 INTERRUPT AT89LS52 EXF2 Rx CLOCK 16 Tx CLOCK 16 15 ...
Page 16
... The RCAP2 registers may be read but should not be written to, because a write might overlap a reload and cause write and/or reload errors. The timer should be turned off (clear TR2) before accessing the Timer 2 or RCAP2 registers. AT89LS52 16 Timer 2 Overflow Rate Modes 1 and 3 Baud Rates ...
Page 17
... RCAP2H and RCAP2L. 2601C–MICRO–06/08 ÷2 TR2 C/T2 BIT EXF2 EXEN2 Clock-Out Frequency = ------------------------------------------------------------------------------------ - 4 x [65536-(RCAP2H,RCAP2L)] AT89LS52 TL2 TH2 (8-BITS) (8-BITS) RCAP2L RCAP2H ÷2 T2OE (T2MOD.1) TIMER 2 INTERRUPT Figure Oscillator Frequency 11-1 ...
Page 18
... Interrupts The AT89LS52 has a total of six interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. These interrupts are all shown in Figure Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE ...
Page 19
... INT0 IE0 1 TF0 0 INT1 IE1 1 TF1 TI RI TF2 EXF2 Figure AT89LS52 16-1. Either a quartz crystal or Figure 16-2. There are no 19 ...
Page 20
... SFRs but does not change the on-chip RAM. The reset should not be activated before V the oscillator to restart and stabilize. Figure 16-1. Oscillator Connections Note: Figure 16-2. External Clock Drive Configuration AT89LS52 20 is restored to its normal operating level and must be held active long enough to allow C1 ± ...
Page 21
... Table 16-1. Mode Idle Idle Power-down Power-down 17. Program Memory Lock Bits The AT89LS52 has three lock bits that can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in Table 17- When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. ...
Page 22
... Data Polling: The AT89LS52 features Data Polling to indicate the end of a byte write cycle. Dur- ing a write cycle, an attempted read of the last byte written will result in the complement of the written data on P0.7. Once the write cycle has been completed, true data is valid on all outputs, and the next cycle may begin ...
Page 23
... Serial Programming Algorithm To program and verify the AT89LS52 in the serial programming mode, the following sequence is recommended: 1. Power-up sequence: a. Apply power between VCC and GND pins. b. Set RST pin to “H” crystal is not connected across pins XTAL1 and XTAL2, apply a 3 MHz to 16 MHz clock to XTAL1 pin and wait for at least 10 milliseconds ...
Page 24
... H Notes: 1. Each PROG pulse is 200 ns - 500 ns for Chip Erase. 2. Each PROG pulse is 200 ns - 500 ns for Write Code Data. 3. Each PROG pulse is 200 ns - 500 ns for Write Lock Bits. 4. RDY/BSY signal is output on P3.0 during programming don’t care. AT89LS52 24 ALE/ EA/ PROG V P2.6 P2.7 ...
Page 25
... AT89LS52 ADDR. P1.0-P1.7 CC 0000H/1FFFH P0 P2 A12 P2.6 P2.7 ALE SEE FLASH P3.3 PROGRAMMING MODES TABLE P3.6 P3.7 XTAL 2 EA 3-16 MHz XTAL1 RST GND PSEN AT89LS52 4.5V - 5.5V PGM DATA PROG RDY/ BSY V IH 4.5V - 5.5V PGM DATA (USE 10K PULLUPS ...
Page 26
... PROG High to BUSY Low GHBL t Byte Write Cycle Time WC Figure 21-1. Flash Programming and Verification Waveforms – Parallel Mode P1.0 - P1.7 P2.0 - P2.4 PORT 0 ALE/PROG EA/V PP P2.7 (ENABLE) P3.0 (RDY/BSY) AT89LS52 26 PP PROGRAMMING ADDRESS DATA DVGL GHDX t t AVGL GHAX t t SHGL ...
Page 27
... Figure 21-2. Flash Memory Serial Downloading 22. Flash Programming and Verification Waveforms – Serial Mode Figure 22-1. Serial Programming Waveforms 2601C–MICRO–06/08 AT89LS52 INSTRUCTION P1.5/MOSI INPUT P1.6/MISO DATA OUTPUT P1.7/SCK CLOCK IN XTAL2 3-16 MHz XTAL1 GND AT89LS52 RST ...
Page 28
... For Page Read/Write, the data always starts from byte 0 to 255. After the command byte and upper address byte are latched, each byte thereafter is treated as data until all 256 bytes are shifted in/out. Then the next instruction will be ready to be decoded. AT89LS52 28 Instruction Format ...
Page 29
... SCK t SHSL = -40⋅ 85⋅ Min 3 62 CLCL 8 t CLCL t CLCL 2 t CLCL 10 *NOTICE: AT89LS52 t SLSH t SLIV = 2.7V - 4.0V (Unless otherwise noted) CC Typ Max 500 400 CLCL Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and ...
Page 30
... OL Port Ports Maximum total I for all output pins exceeds the test condition than the listed test conditions. 2. Minimum V for Power-down is 2V. CC AT89LS52 30 = -40°C to 85°C and V = 2.7V to 4.0V, unless otherwise noted Condition (Except EA) (Except XTAL1, RST) (XTAL1, RST 0 ...
Page 31
... CLCL 147 350 397 137 239 3t -50 CLCL 122 4t -130 CLCL 13 t -50 CLCL 287 7t -150 CLCL 13 t -50 CLCL 0 23 103 t -40 CLCL AT89LS52 Max Units 16 MHz -100 ns CLCL -105 ns CLCL ns t -25 ns CLCL ns 5t -105 ns CLCL -165 ns CLCL ns 2t ...
Page 32
... External Program Memory Read Cycle ALE PSEN PORT 0 PORT 2 28. External Data Memory Read Cycle ALE PSEN FROM RI OR DPL PORT 0 PORT 2 AT89LS52 32 t LHLL t t AVLL LLIV t LLPL t PLIV t PLAZ t LLAX t PXIX INSTR IN t AVIV A8 - A15 t LHLL t LLDV t RLRH t LLWL ...
Page 33
... LHLL t t LLWL WLWH t LLAX t t QVWX AVLL t QVWH FROM RI OR DPL DATA OUT t AVWL P2 A15 FROM DPH t t CHCX CLCH CLCX Min 0 62 AT89LS52 t WHLH t WHQX FROM PCL INSTR A15 FROM PCH t CHCX t CHCL t CLCL Max Units 16 MHz ...
Page 34
... Timing measurements are made at V (1) 35. Float Waveforms Note: 1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the loaded V AT89LS52 34 = 2.7V to 4.0V and Load Capacitance = 80 pF MHz Osc Min 1 ...
Page 35
... Thin Plastic Gull Wing Quad Flatpack (TQFP) 44J 44-lead, Plastic J-leaded Chip Carrier (PLCC) 40P6 40-pin, 0.600" Wide, Plastic Dual Inline Package (PDIP) 2601C–MICRO–06/08 Ordering Code AT89LS52-16AU AT89LS52-16JU AT89LS52-16PU Package Type Package Operation Range 44A Industrial 44J (-40° 85° C) 40P6 ...
Page 36
... This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. 2325 Orchard Parkway San Jose, CA 95131 R AT89LS52 36 B PIN 1 IDENTIFIER ...
Page 37
... Lead coplanarity is 0.004" (0.102 mm) maximum. 2325 Orchard Parkway San Jose, CA 95131 R 2601C–MICRO–06/08 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER TITLE 44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC) AT89LS52 0.318(0.0125) 0.191(0.0075) D2/ COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX A 4.191 – ...
Page 38
... A SEATING PLANE Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). 2325 Orchard Parkway San Jose, CA 95131 R AT89LS52 38 D PIN 0º ~ 15º REF eB TITLE 40P6, 40-lead (0.600" ...
Page 39
... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...