ATMEGA88PA-CCU Atmel, ATMEGA88PA-CCU Datasheet - Page 40

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ATMEGA88PA-CCU

Manufacturer Part Number
ATMEGA88PA-CCU
Description
IC MCU AVR 8K FLASH 32VQFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA88PA-CCU

Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VFQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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9.2
9.3
9.4
8271C–AVR–08/10
BOD Disable
Idle Mode
ADC Noise Reduction Mode
(1)
When the Brown-out Detector (BOD) is enabled by BODLEVEL fuses - see
298
period. To save power, it is possible to disable the BOD by software for some of the sleep
modes, see
level as when BOD is globally disabled by fuses. If BOD is disabled in software, the BOD func-
tion is turned off immediately after entering the sleep mode. Upon wake-up from sleep, BOD is
automatically enabled again. This ensures safe operation in case the V
ing the sleep period.
When the BOD has been disabled, the wake-up time from sleep mode will be approximately 60
µs to ensure that the BOD is working correctly before the MCU continues executing code.
BOD disable is controlled by bit 6, BODS (BOD Sleep) in the control register MCUCR, see
”MCUCR – MCU Control Register” on page
vant sleep modes, while a zero in this bit keeps BOD active. Default setting keeps BOD active,
i.e. BODS set to zero.
Writing to the BODS bit is controlled by a timed sequence and an enable bit, see
MCU Control Register” on page
Note:
When the SM2...0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle
mode, stopping the CPU but allowing the SPI, USART, Analog Comparator, ADC, 2-wire Serial
Interface, Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep
mode basically halts clk
Idle mode enables the MCU to wake up from external triggered interrupts as well as internal
ones like the Timer Overflow and USART Transmit Complete interrupts. If wake-up from the
Analog Comparator interrupt is not required, the Analog Comparator can be powered down by
setting the ACD bit in the Analog Comparator Control and Status Register – ACSR. This will
reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automati-
cally when this mode is entered.
When the SM2...0 bits are written to 001, the SLEEP instruction makes the MCU enter ADC
Noise Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, the 2-
wire Serial Interface address watch, Timer/Counter2
(if enabled). This sleep mode basically halts clk
clocks to run.
This improves the noise environment for the ADC, enabling higher resolution measurements. If
the ADC is enabled, a conversion starts automatically when this mode is entered. Apart from the
ADC Conversion Complete interrupt, only an External Reset, a Watchdog System Reset, a
Watchdog Interrupt, a Brown-out Reset, a 2-wire Serial Interface address match, a
Timer/Counter2 interrupt, an SPM/EEPROM ready interrupt, an external level interrupt on INT0
or INT1 or a pin change interrupt can wake up the MCU from ADC Noise Reduction mode.
Note:
ATmega48A/48PA/88A/88PA/168A/168PA/328/328
and onwards, the BOD is actively monitoring the power supply voltage during a sleep
1. BOD disable only available in picoPower devices ATmega48PA/88PA/168PA/328P
1. Timer/Counter2 will only keep running in asynchronous mode, see
PWM and Asynchronous Operation” on page 145
Table 9-1 on page
CPU
and clk
39. The sleep mode power consumption will then be at the same
45.
FLASH
, while allowing the other clocks to run.
45. Writing this bit to one turns off the BOD in rele-
I/O
, clk
(1)
CPU
, and the Watchdog to continue operating
for details.
, and clk
FLASH
CC
, while allowing the other
”8-bit Timer/Counter2 with
level has dropped dur-
Table 27-7 on page
”MCUCR –
40

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