ATMEGA8U2-MU Atmel, ATMEGA8U2-MU Datasheet

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ATMEGA8U2-MU

Manufacturer Part Number
ATMEGA8U2-MU
Description
MCU AVR 8K FLASH USB 32-VQFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA8U2-MU

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Processor Series
ATMEGA8x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPI, UART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
22
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, AT90USBKEY, ATEVK525
Minimum Operating Temperature
- 40 C
Package
32QFN EP
Device Core
AVR
Family Name
ATmega
Maximum Speed
16 MHz
Operating Supply Voltage
3.3|5 V
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
 Details
Features
Note:
High Performance, Low Power AVR
Advanced RISC Architecture
Non-volatile Program and Data Memories
USB 2.0 Full-speed Device Module with Interrupt on Transfer Completion
Peripheral Features
On Chip Debug Interface (debugWIRE)
Special Microcontroller Features
I/O and Packages
Operating Voltages
Operating temperature
Maximum Frequency
– 125 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– 8K/16K/32K Bytes of In-System Self-Programmable Flash
– 512/512/1024 EEPROM
– 512/512/1024 Internal SRAM
– Write/Erase Cycles: 10,000 Flash/ 100,000 EEPROM
– Data retention: 20 years at 85°C/ 100 years at 25°C
– Optional Boot Code Section with Independent Lock Bits
– Programming Lock for Software Security
– Complies fully with Universal Serial Bus Specification REV 2.0
– 48 MHz PLL for Full-speed Bus Operation : data transfer rates at 12 Mbit/s
– Fully independant 176 bytes USB DPRAM for endpoint memory allocation
– Endpoint 0 for Control Transfers: from 8 up to 64-bytes
– 4 Programmable Endpoints:
– Suspend/Resume Interrupts
– Microcontroller reset on USB Bus Reset without detach
– USB Bus Disconnection on Microcontroller Request
– One 8-bit Timer/Counters with Separate Prescaler and Compare Mode (two 8-bit
– One 16-bit Timer/Counter with Separate Prescaler, Compare and Capture Mode
– USART with SPI master only mode and hardware flow control (RTS/CTS)
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change
– Power-On Reset and Programmable Brown-out Detection
– Internal Calibrated Oscillator
– External and Internal Interrupt Sources
– Five Sleep Modes: Idle, Power-save, Power-down, Standby, and Extended Standby
– 22 Programmable I/O Lines
– QFN32 (5x5mm) / TQFP32 packages
– 2.7 - 5.5V
– Industrial (-40°C to +85°C)
– 8 MHz at 2.7V - Industrial range
– 16 MHz at 4.5V - Industrial range
PWM channels)
(three 8-bit PWM channels)
1. See
In-System Programming by on-chip Boot Program hardware-activated after
reset
True Read-While-Write Operation
IN or Out Directions
Bulk, Interrupt and IsochronousTransfers
Programmable maximum packet size from 8 to 64 bytes
Programmable single or double buffer
“Data Retention” on page 6
®
8-Bit Microcontroller
for details.
(1)
8-bit
Microcontroller
with
8/16/32K Bytes
of ISP Flash
and USB
Controller
ATmega8U2
ATmega16U2
ATmega32U2
7799D–AVR–11/10

Related parts for ATMEGA8U2-MU

ATMEGA8U2-MU Summary of contents

Page 1

... Industrial (-40°C to +85°C) • Maximum Frequency – 8 MHz at 2.7V - Industrial range – 16 MHz at 4.5V - Industrial range Note: 1. See “Data Retention” on page 6 ® 8-Bit Microcontroller (1) for details. 8-bit Microcontroller with 8/16/32K Bytes of ISP Flash and USB Controller ATmega8U2 ATmega16U2 ATmega32U2 7799D–AVR–11/10 ...

Page 2

... PB3 (PDO / MISO / PCINT3 XTAL1 (PC0) XTAL2 (PCINT11 /AIN2 ) PC2 (OC.0B / INT0) PD0 (AIN0 / INT1) PD1 (RXD1 / AIN1 / INT2) PD2 The large center pad underneath the QFN package should be soldered to ground on the board to ensure good mechanical stability. ATmega8U2/16U2/32U2 Reset (PC1 / dW PC6 (OC.1A / PCINT8) ...

Page 3

... Overview The ATmega8U2/16U2/32U2 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega8U2/16U2/32U2 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1 ...

Page 4

... As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATmega8U2/16U2/32U2 as listed on 7799D–AVR–11/10 page 74 ...

Page 5

... As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port C also serves the functions of various special features of the ATmega8U2/16U2/32U2 as listed on 2.2.6 Port D (PD7 ...

Page 6

... I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR". 5. Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. 7799D–AVR–11/10 ATmega8U2/16U2/32U2 6 ...

Page 7

... The program memory is In-System Reprogrammable Flash memory. 7799D–AVR–11/10 Block Diagram of the AVR Architecture Program Flash Counter Program Memory Instruction Register Instruction Decoder Control Lines ATmega8U2/16U2/32U2 Data Bus 8-bit Status and Control Interrupt Unit General Purpose SPI Registrers Unit Watchdog ...

Page 8

... SPI, and other I/O functions. The I/O Memory can be accessed directly the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the ATmega8U2/16U2/32U2 has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used. ...

Page 9

... Set Description” for detailed information. • Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 7799D–AVR–11/ R/W R/W R/W R ⊕ V ATmega8U2/16U2/32U2 R/W R/W R/W R SREG 9 ...

Page 10

... R13 R14 R15 R16 R17 … R26 R27 R28 R29 R30 R31 Figure 6-2, each register is also assigned a data memory address, mapping them ATmega8U2/16U2/32U2 Addr. 0x00 0x01 0x02 0x0D 0x0E 0x0F 0x10 0x11 0x1A X-register Low Byte 0x1B X-register High Byte ...

Page 11

... Data is pushed onto the stack Return address is pushed onto the stack with a subroutine call or Decremented by 2 interrupt Incremented by 1 Data is popped from the stack Incremented by 2 Return address is popped from the stack with return from subroutine or return from interrupt ATmega8U2/16U2/32U2 R26 (0x1A R28 (0x1C) ...

Page 12

... Instruction Fetch 3rd Instruction Fetch 4th Instruction Fetch shows the internal timing concept for the Register File single clock cycle an ALU Single Cycle ALU Operation T1 clk CPU Total Execution Time Result Write Back ATmega8U2/16U2/32U2 SP12 SP11 SP10 SP9 SP4 SP3 ...

Page 13

... This must be handled by software. When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the 7799D–AVR–11/10 ATmega8U2/16U2/32U2 for details. “Interrupts” on page 64 “Memory Programming” on page “ ...

Page 14

... SREG = cSREG; /* restore SREG value (I-bit) */ When using the SEI instruction to enable interrupts, the instruction following SEI will be exe- cuted before any pending interrupts, as shown in this example. 7799D–AVR–11/10 ; store SREG value ; disable interrupts during timed sequence ; start EEPROM write ; restore SREG value (I-bit) ATmega8U2/16U2/32U2 14 ...

Page 15

... A return from an interrupt handling routine takes five clock cycles. During these five clock cycles, the Program Counter (three bytes) is popped back from the Stack, the Stack Pointer is incre- mented by three, and the I-bit in SREG is set. 7799D–AVR–11/10 ; set Global Interrupt Enable ATmega8U2/16U2/32U2 15 ...

Page 16

... AVR Memories This section describes the different memories in the ATmega8U2/16U2/32U2. The AVR archi- tecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega8U2/16U2/32U2 features an EEPROM Memory for data storage. All three memory spaces are linear and regular. ...

Page 17

... SRAM Data Memory Figure 7-2 The ATmega8U2/16U2/32U2 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from $060 - $0FF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used ...

Page 18

... The 32 general purpose working registers, 64 I/O registers, and the 512/512/1024bytes of inter- nal data SRAM in the ATmega8U2/16U2/32U2 are all accessible through all these addressing modes. The Register File is described in Figure 7-2. 7.2.1 Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk Figure 7-3 ...

Page 19

... The I/O space definition of the ATmega8U2/16U2/32U2 is shown in page 288. All ATmega8U2/16U2/32U2 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions ...

Page 20

... General Purpose I/O Registers The ATmega8U2/16U2/32U2 contains three General Purpose I/O Registers. These registers can be used for storing any information, and they are particularly useful for storing global vari- ables and Status Flags. General Purpose I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions ...

Page 21

... R R R/W R EEPROM Mode Bits Programming EEPM0 Time Operation 0 3.4 ms Erase and Write in one operation (Atomic Operation) 1 1.8 ms Erase Only 0 1.8 ms Write Only 1 – Reserved for future use ATmega8U2/16U2/32U2 EERIE EEMPE EEPE EERE R/W R/W R/W R Table 7-1. While EEPE EECR 21 ...

Page 22

... EEPROM write function must also wait for any ongoing SPM command to finish. 7799D–AVR–11/10 for details about Boot programming. EEPROM Programming Time Number of Calibrated RC Oscillator Cycles 26,368 ATmega8U2/16U2/32U2 “Memory Pro- Table 7-2 lists the typical pro- Typ Programming Time 3.3 ms ...

Page 23

... EECR,EEPE ret (1) /* Wait for completion of previous write */ while(EECR & (1<<EEPE Set up address and Data Registers */ EEAR = uiAddress; EEDR = ucData; /* Write logical one to EEMPE */ EECR |= (1<<EEMPE); /* Start eeprom write by setting EEPE */ EECR |= (1<<EEPE); 1. See “Code Examples” on page 6. ATmega8U2/16U2/32U2 23 ...

Page 24

... Set up address register */ EEAR = uiAddress; /* Start eeprom read by writing EERE */ EECR |= (1<<EERE); /* Return data from Data Register */ return EEDR; 1. See “Code Examples” on page MSB R/W R/W R MSB R/W R/W R ATmega8U2/16U2/32U2 R/W R/W R/W R R/W R/W R/W R LSB GPIOR2 ...

Page 25

... GPIOR0 – General Purpose I/O Register 0 Bit 0x1E (0x3E) Read/Write Initial Value 7799D–AVR–11/ MSB R/W R/W R/W R ATmega8U2/16U2/32U2 LSB R/W R/W R/W R GPIOR0 25 ...

Page 26

... I/O clk USB (48MHz) USB PLL X6 clk Pllin (8MHz) PLL Clock Prescaler clk XTAL (2-16 MHz) Crystal Oscillator ATmega8U2/16U2/32U2 CPU Core RAM clk AVR Clock CPU Control Unit clk FLASH Reset Logic Watchdog Timer Source clock Watchdog clock Watchdog System Clock ...

Page 27

... MHz. The PLL always multiply its input frequency by 6. Thus the PLL clock register should be programmed by software to generate a 8 MHz clock on the PLL input. 8.2 Clock Switch In the ATmega8U2/16U2/32U2 product, the Clock Multiplexer and the System Clock Prescaler can be modified by software. 8.2.1 Exemple of use The modification can occur when the device enters in USB Suspend mode ...

Page 28

... Usb_ack_suspend(); Usb_freeze_clock(); Disable_pll(); Enable_RC_clock(); while (!RC_clock_ready()); Select_RC_clock(); Disable_external_clock(); Usb_ack_wake_up(); Enable_external_clock(); while (!External_clock_ready()); // while (CLKSTA.EXTON != 1); Select_external_clock(); Enable_pll(); Disable_RC_clock(); while (!Pll_ready()); Usb_unfreeze_clock(); ATmega8U2/16U2/32U2 upstream-resume 2 Upstream Resume from device (Suspend (UDINT.SUSPI == 1) // UDINT.SUSPI = 0; // USBCON.FRZCLK = 1; // PLLCSR.PLLE = 0; // CLKSEL0.RCE = 1; // while (CLKSTA.RCON != 1); // CLKSEL0.CLKS = 0; // CLKSEL0.EXTE = (UDINT.WAKEUPI == 1) // UDINT.WAKEUPI = 0; // CKSEL0.EXTE = 1; ...

Page 29

... CC Table 8-2. The frequency of the Watchdog Oscillator is voltage “Typical Characteristics” on page Number of Watchdog Oscillator Cycles = 5.0V) Typ Time-out ( 4 ATmega8U2/16U2/32U2 (1) CKSEL3:0 1111 - 1000 0111 - 0110 0101 - 0100 “On-chip Debug System” on page timed from the Watchdog TOUT 273. = 3.0V) Number of Cycles ...

Page 30

... The frequency ranges are preliminary values. Actual values are TBD. 2. This option should not be used with crystals, only with ceramic resonators. ATmega8U2/16U2/32U2 Figure 8-4. Either a quartz crystal or a XTAL2 XTAL1 GND (3) Recommended Range for Capacitors C1 ...

Page 31

... Start-up times for the internal calibrated RC Oscillator clock selection Start-up Time from Power- down and Power-save Reserved The device is shipped with this option selected. 1. ATmega8U2/16U2/32U2 ), the CKDIV8 CC Additional Delay from Reset (V = 5.0V) CKSEL0 CC (1) 14CK + 4 ...

Page 32

... Power Crystal Oscillator” on page = 2.7 - 5.5 volts. CC Table 1. For ceramic resonators, the capacitor values given by the ATmega8U2/16U2/32U2 Figure 8-4. Either a quartz crystal or a 30. Note that the Full Swing Crystal 32 ...

Page 33

... The device is shipped with the CKDIV8 Fuse programmed. 266. “Calibration Byte” on page Internal Calibrated RC Oscillator Operating Modes (2) Frequency Range (MHz) 7.3 - 8.1 ATmega8U2/16U2/32U2 Additional Delay from Reset (V = 5.0V) CKSEL0 CC (1) 14CK + 4.1 ms ...

Page 34

... Fuse can be programmed in order to divide the internal frequency by 8. 31. Start-up times for the internal calibrated RC Oscillator clock selection Start-up Time from Power- down and Power-save Reserved 1. The device is shipped with this option selected. ATmega8U2/16U2/32U2 ), the CKDIV8 CC Additional Delay from Reset (V = 5.0V 4 SUT1 ...

Page 35

... Oscillator, can be selected when the clock is output on CLKO. If the System Clock Prescaler is used the divided system clock that is output. 8.9 System Clock Prescaler The ATmega8U2/16U2/32U2 has a system clock prescaler, and the system clock can be divided by setting the 7799D–AVR–11/10 External Clock Drive Configuration ...

Page 36

... XTAL1). 8.10.1 Internal PLL for USB interface The internal PLL in ATmega8U2/16U2/32U2 generates a clock frequency that is 6x multiplied from nominally 8 MHz input. The source of the 8 MHz PLL input clock is the output of the internal PLL clock prescaler that generates the 8 MHz. ...

Page 37

... PLL Clocking System PINDIV CKSEL3:0 XTAL OSCILLATOR PLL clock Prescaler RC OSCILLATOR 8 MHz To System Clock Prescaler RCSUT1 RCSUT0 EXSUT1 EXSUT0 R/W R/W R/W R ATmega8U2/16U2/32U2 PLOCK PLLE PLLITM /48 Lock Detector T1 PLL /2 clk 8MHz PDIV3..0 PLLUSB RCE EXTE - R/W R See Bit Description ...

Page 38

... R/W R/W R/W R CAL7 CAL6 CAL5 CAL4 R/W R/W R/W R/W Device Specific Calibration Value Table 26-1 on page 266. The application software can write this register to change ATmega8U2/16U2/32U2 EXCKSE EXCKSE EXCKSE EXCKSE R/W R/W R/W R RCON EXTON See Bit Description CAL3 ...

Page 39

... The device is shipped with the CKDIV8 Fuse programmed. 7799D–AVR–11/10 266. Calibration outside that range is not guaranteed CLKPCE – – R ATmega8U2/16U2/32U2 – CLKPS3 CLKPS2 CLKPS1 CLKPS0 R R/W R/W R/W 0 See Bit Description ...

Page 40

... Read/Write Initial Value • Bit 7:5 – Res: Reserved Bits These bits are reserved bits in the ATmega8U2/16U2/32U2 and always read as zero. • Bit 4 – DIV5 PLL Input Prescaler (1:5) • Bit 3 – DIV3 PLL Input Prescaler (1:3) • Bit 2 – PINDIV PLL Input Prescaler (1:1, 1:2) These bits allow to configure the PLL input prescaler to generate the 8MHz input clock for the PLL from either MHz input ...

Page 41

... Bit 0 – PLOCK: PLL Lock Detector When the PLOCK bit is set, the PLL is locked to the reference clock. After the PLL is enabled, it takes about several ms for the PLL to lock. To clear PLOCK, clear PLLE. 7799D–AVR–11/10 ATmega8U2/16U2/32U2 41 ...

Page 42

... When the SM2:0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing the USB, SPI, USART, Analog Comparator, Timer/Counters, 7799D–AVR–11/10 presents the different clock systems in the ATmega8U2/16U2/32U2, and Active Clock Domains and Wake-up Sources in the Different Sleep Modes. Active Clock ...

Page 43

... I/O registers can not be read or written. Resources used by the peripheral 7799D–AVR–11/10 , while allowing the other clocks to run. FLASH “Clock Sources” on page ATmega8U2/16U2/32U2 “External Interrupts” on page 84 29. “PRR0 – Power Reduction Register 0” for details. The current state of the peripheral ...

Page 44

... Watchdog Timer stopped, the input buffers of the device will be disabled. This ensures that no I/O for details on which pins are enabled. If the input buffer is ATmega8U2/16U2/32U2 for details on how to “Brown-out Detection” on page 50 “Internal Voltage Reference” on “Digital Input ...

Page 45

... Sleep Mode Select SM1 SM0 Standby modes are only recommended for use with external crystals or resonators. ATmega8U2/16U2/32U2 for details – SM2 SM1 SM0 R R/W R/W R Table 9-2. Sleep Mode Idle Reserved Power-down Power-save Reserved Reserved (1) Standby (1) Extended Standby /2, the SMCR ...

Page 46

... Writing a logic one to this bit shuts down the USART1 by stopping the clock to the module. When waking up the USART1 again, the USART1 should be re initialized to ensure proper operation. 7799D–AVR–11/ PRTIM0 – R/W R/W R PRUSB – – – R ATmega8U2/16U2/32U2 PRTIM1 PRSPI - R/W R – – PRUSART1 R R PRR0 0 PRR1 46 ...

Page 47

... Reset Sources The ATmega8U2/16U2/32U2 has five sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length. • ...

Page 48

... Reset Characteristics” on page rise. The RESET signal is activated again, without any delay, CC decreases below the detection level POT RST RESET t TOUT RESET ATmega8U2/16U2/32U2 DATA BUS MCU Status Register (MCUSR) Delay Counters CK TIMEOUT 267. The POR is activated whenever CC 48 ...

Page 49

... MCU after the Time-out period – t Figure 10-4. External Reset During Operation 7799D–AVR–11/10 V POT V CC RESET RESET “System and Reset Characteristics” on page CC ATmega8U2/16U2/32U2 V RST t TOUT 267) will generate a – on its positive edge, the RST – has expired. TOUT 49 ...

Page 50

... Brown-out Detection ATmega8U2/16U2/32U2 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V level during operation by comparing fixed trigger level. The trigger level for the BOD CC can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as V ...

Page 51

... Early warning after one Time-Out period reached, programmable Reset (see operating modes) after 2 Time-Out periods reached. 10.4.2 Overview ATmega8U2/16U2/32U2 has an Enhanced Watchdog Timer (WDT). The WDT is a timer count- ing cycles of a separate on-chip 128 kHz oscillator. The WDT gives a early warning interrupt 7799D–AVR–11/10 CC ...

Page 52

... Within the next four clock cycles, write the WDE and Watchdog prescaler bits (WDP) as desired, but with the WDCE bit cleared. This must be done in one operation. 7799D–AVR–11/10 128kHz OSCILLATOR OSC/1 OSC/3 CLOCK OSC/5 DIVIDER OSC/7 WATCHDOG RESET WDE WDIF WDIE WDEWIE ATmega8U2/16U2/32U2 WDP0 WDP1 WDP2 WDP3 MCU RESET INTERRUPT EARLY WARNING INTERRUPT 52 ...

Page 53

... The following code example shows one assembly and one C function for turning off the Watch- dog Timer. The example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during the execution of these functions. 7799D–AVR–11/10 ATmega8U2/16U2/32U2 53 ...

Page 54

... Clear WDRF in MCUSR */ MCUSR &= ~(1<<WDRF); /* Write logical one to WDCE and WDE */ /* Keep old prescaler setting to prevent unintentional time-out */ WDTCSR |= (1<<WDCE) | (1<<WDE); /* Turn off WDT */ WDTCSR = 0x00; __enable_interrupt(); 1. The example code assumes that the part specific header file is included. ATmega8U2/16U2/32U2 54 ...

Page 55

... Set new prescaler(time-out) value = 64K cycles (~0 WDTCSR = (1<<WDE) | (1<<WDP2) | (1<<WDP0); __enable_interrupt(); 1. The example code assumes that the part specific header file is included – – USBRF ATmega8U2/16U2/32U2 – WDRF BORF EXTRF R/W R/W R/W R/W See Bit Description 0 PORF MCUSR ...

Page 56

... Interrupt and System Reset Mode, WDIE must be set after each interrupt. This should how- ever not be done within the interrupt service routine itself, as this might compromise the safety- 7799D–AVR–11/ WDIF WDIE WDP3 WDCE R/W R/W R/W R ATmega8U2/16U2/32U2 WDE WDP2 WDP1 WDP0 R/W R/W R/W R WDTCSR 56 ...

Page 57

... System Reset Mode Interrupt and System 1 1 Reset Mode x x System Reset Mode 58 WDE- WCLKD2 WIFCM R R R/W R ATmega8U2/16U2/32U2 Action on 2x Time-out None Interrupt Reset Interrupt, then go to System Reset Mode Reset WDEWIF WDEWIE WCLKD1 WCLKD0 R/W R/W R/W R 58. WDTCKD ...

Page 58

... ATmega8U2/16U2/32U2 Mode Clk = Clk 0 WDT 128k Clk = Clk / 3 1 WDT 128k Clk = Clk / 5 0 WDT ...

Page 59

... ATmega8U2/16U2/32U2 Watchdog Early warning Typical Reset/Interrupt Typical Time-out at Time-out 5. Reserved Watchdog Early warning Typical Reset/Interrupt Typical Time-out at Time-out 5. ...

Page 60

... ATmega8U2/16U2/32U2 Watchdog Early warning Typical Reset/Interrupt Typical Time-out at Time-out 5. 160 ms 160 ms 320 ms 320 ms 640 ms 0.625 s 1 ...

Page 61

... ATmega8U2/16U2/32U2 Watchdog Early warning Typical Reset/Interrupt Typical Time-out at Time-out 5. Reserved Watchdog Early warning Typical Reset/Interrupt Typical Time-out at Time-out 5. ...

Page 62

... ATmega8U2/16U2/32U2 Watchdog Early warning Typical Reset/Interrupt Typical Time-out at Time-out 5. 176 ms 176 ms 352 ms 352 ms 704 ms 704 ms 1 ...

Page 63

... ATmega8U2/16U2/32U2 Watchdog Early warning Typical Reset/Interrupt Typical Time-out at Time-out 5. Reserved Watchdog Early warning Typical Reset/Interrupt Typical Time-out at Time-out 5. ...

Page 64

... Interrupts 11.1 Overview ATmega8U2/16U2/32U2. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 11.2 Interrupt Vectors in ATmega8U2/16U2/32U2 Table 11-1. Vector No 7799D–AVR–11/10 13. Reset and Interrupt Vectors Program (2) Address Source Interrupt Definition External Pin, Power-on Reset, Brown-out Reset, ...

Page 65

... JTD – – R ATmega8U2/16U2/32U2 Interrupt Definition Analog Comparator EEPROM Ready Store Program Memory Ready 246. (1) Interrupt Vectors Start Address 0x0002 Boot Reset Address + 0x0002 0x0002 Boot Reset Address + 0x0002 Table 23-8 on page 239. For the BOOTRST Fuse “1” ...

Page 66

... Enable change of Interrupt Vectors ldi r16, (1<<IVCE) out MCUCR, r16 ; Move interrupts to Boot Flash section ldi r16, (1<<IVSEL) out MCUCR, r16 ret /* Enable change of Interrupt Vectors */ MCUCR = (1<<IVCE); /* Move interrupts to Boot Flash section */ MCUCR = (1<<IVSEL); ATmega8U2/16U2/32U2 “Memory 66 ...

Page 67

... Ground as indicated in CC for a complete list of parameters. Pxn C pin “Register Description for I/O-Ports” on page 72. Refer to the individual module sections for a full description of the alter- ATmega8U2/16U2/32U2 Figure 12-1. Refer to “Electrical Char Logic See Figure "General Digital I/O" for Details 82 ...

Page 68

... I/O CLOCK I/O 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk SLEEP, and PUD are common to all ports. 82, the DDxn bits are accessed at the DDRx I/O address, the ATmega8U2/16U2/32U2 Figure 12-2 PUD Q D DDxn ...

Page 69

... Input 1 1 Input 0 X Output 1 X Output Figure 12-2, the PINxn Register bit and the preceding latch con- pd,max ATmega8U2/16U2/32U2 Pull-up Comment No Tri-state (Hi-Z) Yes Pxn will source current if ext. pulled low. No Tri-state (Hi-Z) No Output Low (Sink) No Output High (Source) Figure 12-3 ...

Page 70

... SYNC LATCH PINxn r17 Figure 12-4. The out instruction sets the “SYNC LATCH” signal at the positive edge of SYSTEM CLK r16 out PORTx, r16 SYNC LATCH PINxn r17 ATmega8U2/16U2/32U2 XXX in r17, PINx 0x00 t pd, max t pd, min 0xFF nop in r17, PINx ...

Page 71

... Figure 12-2, the digital input signal can be clamped to ground at the input of the “Alternate Port Functions” on page ATmega8U2/16U2/32U2 /2. CC 72. 71 ...

Page 72

... Pxn PULL-UP OVERRIDE ENABLE Pxn PULL-UP OVERRIDE VALUE Pxn DATA DIRECTION OVERRIDE ENABLE Pxn DATA DIRECTION OVERRIDE VALUE Pxn PORT VALUE OVERRIDE ENABLE Pxn PORT VALUE OVERRIDE VALUE SLEEP CONTROL Pxn, PORT TOGGLE OVERRIDE ENABLE ATmega8U2/16U2/32U2 Figure 12-2 can be overridden by PUD Q D DDxn Q ...

Page 73

... Unless the Digital Input is used as a clock source, the module with the alternate function will use its own synchronizer. This is the Analog Input/output to/from alternate functions. The Analog signal is connected directly to the pad, and can be used bi- Input/Output directionally. ATmega8U2/16U2/32U2 , I/O Fig- 73 ...

Page 74

... PDO/MISO/PCINT3 (Programming Data Output or SPI Bus Master Input/Slave Output or Pin Change Interrupt 3) PDI/MOSI/PCINT2 (Programming Data Input or SPI Bus Master Output/Slave Input or Pin Change Interrupt 2) SCLK/PCINT1 (SPI Bus Serial Clock or Pin Change Interrupt 1) SS/PCINT0 (SPI Slave Select input or Pin Change Interrupt 0) ATmega8U2/16U2/32U2 Table 12-3. 74 ...

Page 75

... PCINT0, Pin Change Interrupt source 0: The PB0 pin can serve as an external interrupt source 7799D–AVR–11/10 and Table 12-5 relate the alternate functions of Port B to the overriding signals Figure 12-5 on page 72. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the ATmega8U2/16U2/32U2 75 ...

Page 76

... SPE • MSTR SPE • MSTR SPI SLAVE OUTPUT SPI MSTR OUTPUT PCINT3 • PCIE0 PCINT2 • PCIE0 1 1 SPI MSTR INPUT SPI SLAVE INPUT PCINT3 INPUT PCINT2 INPUT – – ATmega8U2/16U2/32U2 PB5/PCINT5 PB4/T1/PCINT4 PCINT5 • PCIE0 PCINT4 • PCIE0 ...

Page 77

... PCINT11, Pin Change Interrupt source 11 : The PC2 pin can serve as an external interrupt source. • Reset/dW, Bit 1 7799D–AVR–11/10 Port C Pins Alternate Functions Port Pin Alternate Function PC7 ICP1/INT4/CLKO PC6 PCINT8/OC1A PC5 PCINT9/OC1B PC4 PCINT10 - - PC2 PCINT11 PC1 Reset, dW PC0 XTAL2 ATmega8U2/16U2/32U2 77 ...

Page 78

... OC1A INT4 ENABLE PCINT8 ENABLE 1 1 INT4 INPUT PCINT8 INPUT – – Overriding Signals for Alternate Functions in PC2..PC0 PC2/PCINT11 PCINT11 ENABLE 1 PCINT11 INPUT – ATmega8U2/16U2/32U2 PC5/PCINT9/ OC1B PC4/PCINT10 OC1B ENABLE 0 OC1B 0 PCINT9 ENABLE PCINT10 ENABLE 1 1 PCINT9 INPUT PCINT10 INPUT – ...

Page 79

... Port D Pins Alternate Functions Alternate Function HWB/TO/INT7/CTS INT6/RTS XCK1/PCINT12 (USART1 External Clock Input/Output) INT5 INT3/TXD1 (External Interrupt3 Input or USART1 Transmit Pin) INT2/AIN1/RXD1(External Interrupt2 Input or USART1 Receive Pin) INT1/AIN0 (External Interrupt1 Input) INT0/OC0B (External Interrupt0 Input) , Bit 7 ,Bit 6 , Bit 5 , Bit 3 ATmega8U2/16U2/32U2 Table 12-9. 79 ...

Page 80

... The OC0B pin is also the output pin for the PWM mode timer function. Table 12-10 shown in 7799D–AVR–11/10 , Bit 2 , Bit 1 , Bit 0 and Table 12-11 relates the alternate functions of Port D to the overriding signals Figure 12-5 on page 72. ATmega8U2/16U2/32U2 80 ...

Page 81

... INT2 INPUT/RXD1 – AIN1 INPUT 1. When enabled, the 2-wire Serial Interface enables Slew-Rate controls on the output pins PD0 and PD1. This is not shown in this table. In addition, spike filters are connected between the AIO outputs shown in the port figure. ATmega8U2/16U2/32U2 PD5/XCK/PCINT12 PD4/INT5 ...

Page 82

... PORTC4 R/W R/W R/W R DDC7 DDC6 DDC5 DDC4 R/W R/W R/W R PINC7 PINC6 PINC5 PINC4 R/W R/W R/W R/W N/A N/A N/A N/A ATmega8U2/16U2/32U2 – – IVSEL IVCE R R R/W R PORTB3 PORTB2 PORTB1 PORTB0 R/W R/W R/W R DDB3 DDB2 DDB1 DDB0 ...

Page 83

... R/W R/W R/W R DDD7 DDD6 DDD5 DDD4 R/W R/W R/W R PIND7 PIND6 PIND5 PIND4 R/W R/W R/W R/W N/A N/A N/A N/A ATmega8U2/16U2/32U2 PORTD3 PORTD2 PORTD1 PORTD0 R/W R/W R/W R DDD3 DDD2 DDD1 DDD0 R/W R/W R/W R PIND3 PIND2 PIND1 PIND0 ...

Page 84

... Low level interrupts and the edge interrupt on INT[3:0] are 26 ISC31 ISC30 ISC21 ISC20 R/W R/W R/W R Table 13-1. Edges on INT[3:0] are registered asynchro- will generate an interrupt. Shorter pulses are not guaranteed to ATmega8U2/16U2/32U2 ISC11 ISC10 ISC01 ISC00 R/W R/W R/W R “External Interrupts “System EICRA 84 ...

Page 85

... The falling edge between two samples of INTn generates an interrupt request. 1 The rising edge between two samples of INTn generates an interrupt request When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed. ATmega8U2/16U2/32U2 ISC60 ...

Page 86

... R/W R/W R/W R INTF7 INTF6 INTF5 INTF4 R/W R/W R/W R – – – – ATmega8U2/16U2/32U2 INT3 INT2 INT1 IINT0 R/W R/W R/W R INTF3 INTF2 INTF1 INTF0 R/W R/W R/W R for more information – – PCIE1 PCIE0 R R R/W R – – PCIF1 ...

Page 87

... I/O pin. If PCINT[12:8] is cleared, pin change interrupt on the corresponding I/O pin is disabled. 7799D–AVR–11/ PCINT7 PCINT6 PCINT5 PCINT4 R/W R/W R/W R PCINT12 R R R/W R ATmega8U2/16U2/32U2 PCINT3 PCINT2 PCINT1 PCINT0 R/W R/W R/W R PCINT11 PCINT10 PCINT9 PCINT8 R/W R/W R/W R PCMSK0 PCMSK1 ...

Page 88

... Alternatively, one of four taps from the prescaler can be used CLK_I/O /1024. CLK_I/O pulse for each positive (CSn2 negative (CSn2 clk I/O Synchronization ATmega8U2/16U2/32U2 /8, f CLK_I/O Figure 14-1 shows a functional ). The latch is transparent in the clk I/O Tn_sync D Q (To Clock Select Logic) Edge Detector ...

Page 89

... Timer/Counters start counting simultaneously. 7799D–AVR–11/10 < f /2) given a 50/50% duty cycle. Since the edge detector uses ExtClk clk_I/O I/O Clear Synchronization Synchronization TIMER/COUNTERn CLOCK SOURCE clk TSM – – R ATmega8U2/16U2/32U2 CSn0 CSn1 CSn2 TIMER/COUNTERn CLOCK SOURCE – – – /2.5. clk_I/O ...

Page 90

... When this bit is one, Timer/Counter0 and Timer/Counter1, Timer/Counter3, Timer/Counter4 and Timer/Counter5 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter0 and Timer/Counter1 share the same pres- caler and a reset of this prescaler will affect all timers. 7799D–AVR–11/10 ATmega8U2/16U2/32U2 90 ...

Page 91

... Mask Register (TIMSK0). TIFR0 and TIMSK0 are not shown in the figure. The Timer/Counter can be clocked internally, via the prescaler external clock source on the T0 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter 7799D–AVR–11/10 ATmega8U2/16U2/32U2 “Pinout” on page 2. CPU accessible I/O Registers, including I/O 102. ...

Page 92

... OCR0A Register. The assignment is depen- dent on the mode of operation. “Timer/Counter0 and Timer/Counter1 Prescalers” on page DATA BUS count clear TCNTn direction bottom ATmega8U2/16U2/32U2 for details. The Compare Match event will also 88. TOVn (Int.Req.) Clock Select Edge Detector clk ...

Page 93

... Signalize that TCNT0 has reached minimum value (zero). ). clk can be generated from an external or internal clock source present or not. A CPU write overrides (has priority over) all counter clear or T0 96. shows a block diagram of the Output Compare unit. ATmega8U2/16U2/32U2 in the following. T0 (“Modes of Operation” on page 96). “Modes of 93 ...

Page 94

... Unit, independently of whether the Timer/Counter is running or not. If the value written to TCNT0 equals the OCR0x value, the Compare Match will be missed, resulting in incorrect waveform 7799D–AVR–11/10 DATA BUS OCRnx = (8-bit Comparator ) top bottom Waveform Generator FOCn WGMn1:0 ATmega8U2/16U2/32U2 TCNTn OCFnx (Int.Req.) OCnx COMnX1:0 94 ...

Page 95

... The design of the Output Compare pin logic allows initialization of the OC0x state before the out- put is enabled. Note that some COM0x1:0 bit settings are reserved for certain modes of operation. 7799D–AVR–11/10 COMnx1 Waveform COMnx0 Generator FOCn clk I/O See “Register Description” on page 102. ATmega8U2/16U2/32U2 Figure 15 OCnx OCnx PORT D ...

Page 96

... The timing diagram for the CTC mode is shown in increases until a Compare Match occurs between TCNT0 and OCR0A, and then counter (TCNT0) is cleared. 7799D–AVR–11/10 ATmega8U2/16U2/32U2 Table 15-2 on page 102, and for phase correct PWM refer to (See “Compare Match Output Unit” on page “ ...

Page 97

... In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast 7799D–AVR–11/10 ATmega8U2/16U2/32U2 ...

Page 98

... A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set- ting OC0x to toggle its logical level on each Compare Match (COM0x[1:0] = 1). The waveform generated will have a maximum frequency of f 7799D–AVR–11/10 ATmega8U2/16U2/32U2 Figure 15-6. The TCNT0 value is in the timing diagram shown as a his- 1 ...

Page 99

... OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM0x[1:0] to three: Setting the COM0A0 bit to 7799D–AVR–11/10 15-7. The TCNT0 value is in the timing diagram shown as a histogram for illustrating 1 ATmega8U2/16U2/32U2 OCnx Interrupt Flag Set OCRnx Update TOVn Interrupt Flag Set (COMnx1 ...

Page 100

... Figure 15-8 contains timing data for basic Timer/Counter operation. The figure I/O Tn /1) I/O MAX - 1 shows the same timing data, but with the prescaler enabled. ATmega8U2/16U2/32U2 103). The actual OC0x value will only f clk_I/O = ----------------- - ⋅ N 510 OCnx has a transition from high to low even though Figure 15-7 ...

Page 101

... OCF0B in all modes and OCF0A in all modes except CTC I/O Tn /8) I/O OCRnx - 1 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fast caler (f /8) clk_I/O I/O Tn /8) I/O TOP - 1 ATmega8U2/16U2/32U2 /8) clk_I/O MAX BOTTOM OCRnx OCRnx + 1 OCRnx Value TOP BOTTOM TOP BOTTOM + 1 /8) clk_I/O OCRnx + 2 ...

Page 102

... Clear OC0A on Compare Match, set OC0A at TOP 1 Set OC0A on Compare Match, clear OC0A at TOP 1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Com- pare Match is ignored, but the set or clear is done at TOP. See for more details. ATmega8U2/16U2/32U2 COM0B0 – ...

Page 103

... Set OC0B on Compare Match, clear OC0B at TOP 1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Com- pare Match is ignored, but the set or clear is done at TOP. See for more details. ATmega8U2/16U2/32U2 (1) “Phase Correct PWM Mode” on (1) “ ...

Page 104

... Fast PWM Reserved PWM, Phase Correct Reserved Fast PWM 1. MAX = 0xFF 2. BOTTOM = 0x00 ATmega8U2/16U2/32U2 (1) “Phase Correct PWM Mode” on “Modes of Operation” on page 96). Update of TOP OCRx at 0xFF Immediate 0xFF TOP OCRA Immediate 0xFF TOP – – OCRA TOP – – ...

Page 105

... FOC0B – “TCCR0A – Timer/Counter Control Register A” on page Clock Select Bit Description CS01 CS00 Description clock source (Timer/Counter stopped clk /(No prescaling) I clk /8 (From prescaler) I clk /64 (From prescaler) I/O ATmega8U2/16U2/32U2 – WGM02 CS02 CS01 R R/W R/W R CS00 TCCR0B R/W 0 102. 105 ...

Page 106

... External clock source on T0 pin. Clock on falling edge External clock source on T0 pin. Clock on rising edge R/W R/W R/W R R/W R/W R/W R R/W R/W R/W R – – – – ATmega8U2/16U2/32U2 TCNT0[7:0] R/W R/W R OCR0A[7:0] R/W R/W R OCR0B[7:0] R/W R/W R – OCIE0B OCIE0A R R/W R ...

Page 107

... When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed. The setting of this flag is dependent of the WGM0[2:0] bit setting. Refer to form Generation Mode Bit Description” on page 7799D–AVR–11/10 ATmega8U2/16U2/32U2 – ...

Page 108

... Timer/Counter 1 with PWM” on page The Power Reduction Timer/Counter1 bit, PRTIM1, in page 46 7799D–AVR–11/10 “Pinout” on page must be written to zero to enable Timer/Counter1 module. ATmega8U2/16U2/32U2 Figure 16-1. For the actual 2. CPU accessible I/O Registers, including I/O bits 108. “PRR0 – Power Reduction Register 0” on ...

Page 109

... Count Clear Direction Timer/Counter TCNTn = OCRnA = OCRnB = OCRnC ICRn TCCRnA 1. Refer to Figure 1-1 on page 2, Table 12-3 on page Timer/Counter1 pin placement and description. ATmega8U2/16U2/32U2 (1) TOVn (Int.Req.) Control Logic Clock Select TCLK Edge Detector TOP BOTTOM ( From Prescaler ) = = 0 OCFnA (Int.Req.) Waveform Generation ...

Page 110

... The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be one of the fixed values: 0x00FF, 0x01FF, or 0x03FF the value stored in the OCRnA or ICRn Register. The assignment is dependent of the mode of operation. ATmega8U2/16U2/32U2 (See 110 ...

Page 111

... Reading any of the OCRnA/B/C or ICRn Registers can be done by using the same principle. 7799D–AVR–11/10 (1) ... ; Set TCNTn to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNTnH,r17 out TCNTnL,r16 ; Read TCNTn into r17:r16 in r16,TCNTnL in r17,TCNTnH ... (1) unsigned int i; ... /* Set TCNTn to 0x01FF */ TCNTn = 0x1FF; /* Read TCNTn into TCNTn; ... 1. See “Code Examples” on page 6. ATmega8U2/16U2/32U2 111 ...

Page 112

... Restore global interrupt flag out SREG,r18 ret (1) unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ __disable_interrupt(); /* Read TCNTn into TCNTn; /* Restore global interrupt flag */ SREG = sreg; return i; 1. See “Code Examples” on page 6. ATmega8U2/16U2/32U2 112 ...

Page 113

... Restore global interrupt flag out SREG,r18 ret (1) unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ __disable_interrupt(); /* Set TCNTn TCNTn = i; /* Restore global interrupt flag */ SREG = sreg; 1. See “Code Examples” on page 6. “Timer/Counter0 and Timer/Counter1 Prescalers” on page ATmega8U2/16U2/32U2 88. 113 ...

Page 114

... Signalize that TCNTn has reached minimum value (zero). ). The clk can be generated from an external or internal clock source present or not. A CPU write overrides (has priority over) all counter clear “Modes of Operation” on page ATmega8U2/16U2/32U2 TOVn (Int.Req.) Clock Select Edge Detector clk Tn Control Logic ( From Prescaler ) TOP BOTTOM 120 ...

Page 115

... ICRnL (8-bit) ICRn (16-bit Register) WRITE ACO* ACIC* Analog Comparator ICPn The Analog Comparator Output (ACO) can only trigger the Timer/Counter1 ICP – not Timer/Counter3 ATmega8U2/16U2/32U2 Figure 16-3. The elements of DATA BUS (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) ICNC ICES ...

Page 116

... Even though the Input Capture interrupt has relatively high priority, the maximum interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests. 7799D–AVR–11/10 110. ATmega8U2/16U2/32U2 “Accessing 16-bit Registers” (Figure 14-1 on page 88). The edge detector is also 116 ...

Page 117

... Output Compare unit. The small “n” in the register and DATA BUS TEMP (8-bit) OCRnxH Buf. (8-bit) OCRnxL Buf. (8-bit) OCRnx Buffer (16-bit Register) OCRnxH (8-bit) OCRnxL (8-bit) OCRnx (16-bit Register) TOP BOTTOM ATmega8U2/16U2/32U2 120.) (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) = (16-bit Comparator ) OCFnx (Int.Req.) Waveform Generator WGMn3:0 ...

Page 118

... Normal mode. The OCnx Register keeps its value even when changing between Waveform Generation modes. Be aware that the COMnx1:0 bits are not double buffered together with the compare value. Changing the COMnx1:0 bits will take effect immediately. 7799D–AVR–11/10 110. ATmega8U2/16U2/32U2 “Accessing 16-bit Registers” 118 ...

Page 119

... For all modes, setting the COMnx1 tells the Waveform Generator that no action on the OCnx Register performed on the next compare match. For compare output actions in the 7799D–AVR–11/10 Waveform Generator I/O See “16-bit Timer/Counter 1 with PWM” on page 108. ATmega8U2/16U2/32U2 Figure 16 OCnx 0 ...

Page 120

... The timing diagram for the CTC mode is shown in increases until a compare match occurs with either OCRnA or ICRn, and then counter (TCNTn) is cleared. 7799D–AVR–11/10 ATmega8U2/16U2/32U2 Table 16-1 on page 130. For fast PWM mode refer to 119.) “Timer/Counter Timing Diagrams” on page ...

Page 121

... High frequency allows physically small sized external components (coils, capaci- tors), hence reduces total system cost. 7799D–AVR–11/ when OCRnA is set to zero (0x0000). The waveform frequency clk_I -------------------------------------------------- - ⋅ OCnA 2 N ATmega8U2/16U2/32U2 OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) (COMnA1 clk_I/O ⋅ OCRnA 121 ...

Page 122

... TOP value. The counter will then have to count to the MAX value (0xFFFF) and wrap around starting at 0x0000 before the compare match can occur. The OCRnA Register however, is double buffered. This feature allows the OCRnA I/O location 7799D–AVR–11/10 ATmega8U2/16U2/32U2 ( log TOP ...

Page 123

... However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined by either ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 7799D–AVR–11/10 ATmega8U2/16U2/32U2 Table on page f clk_I/O f ...

Page 124

... Note that when using fixed TOP values, the unused bits are masked to zero when any of the OCRnx Registers are written. As the third period shown in TOP actively while the Timer/Counter is running in the phase correct mode can result in an unsymmetrical output. The reason for this can be found in the time of update of the OCRnx Reg- 7799D–AVR–11/10 ATmega8U2/16U2/32U2 ( ) log + ...

Page 125

... Figure The PWM resolution for the phase and frequency correct PWM mode can be defined by either ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and 7799D–AVR–11/10 f OCnxPCPWM 16-9). ATmega8U2/16U2/32U2 Table 16-3 on page f clk_I/O = --------------------------- - ⋅ ⋅ TOP ...

Page 126

... R = ---------------------------------- - PFCPWM Figure 16-9. The figure shows phase and frequency correct shows the output generated is, in contrast to the phase correct mode, symmetri- ATmega8U2/16U2/32U2 ( ) + 1 TOP log OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) OCRnx/TOP Updateand TOVn Interrupt Flag Set ...

Page 127

... OCnxPFCPWM Figure 16-10 clk I/O clk Tn (clk /1) I/O TCNTn OCRnx - 1 OCRnx OCFnx shows the same timing data, but with the prescaler enabled. ATmega8U2/16U2/32U2 f clk_I/O = --------------------------- - ⋅ ⋅ TOP ) is therefore shown shows a timing diagram for the setting of OCFnx. OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value ...

Page 128

... FPWM) TCNTn TOP - 1 TOVn (FPWM) and ICFn (if used as TOP) OCRnx Old OCRnx Value (Update at TOP) shows the same timing data, but with the prescaler enabled. ATmega8U2/16U2/32U2 OCRnx OCRnx + 1 OCRnx Value TOP BOTTOM TOP TOP - 1 New OCRnx Value /8) clk_I/O OCRnx + 2 ...

Page 129

... WGMn[3:0] bits are set to a normal or a CTC mode (non-PWM). 7799D–AVR–11/10 I/O Tn /8) I/O TOP - 1 TOP - 1 (FPWM) (if used Old OCRnx Value COM1A1 COM1A0 COM1B1 R/W R/W R ATmega8U2/16U2/32U2 /8) clk_I/O TOP BOTTOM BOTTOM + 1 TOP TOP - 1 TOP - 2 New OCRnx Value COM1B0 COM1C1 COM1C0 WGM11 R/W R/W R/W R/W 0 ...

Page 130

... COMnA1/COMnB1/COMnC1 is set. In this case the compare match is ignored, but the set or clear is done at TOP. See “Fast PWM Mode” on page 97. shows the COMnx[1:0] bit functionality when the WGMn[3:0] bits are set to the phase ATmega8U2/16U2/32U2 Description Normal port operation, OCnA/OCnB/OCnC disconnected. Toggle OCnA/OCnB/OCnC on compare match. ...

Page 131

... A special case occurs when OCRnA/OCRnB/OCRnC equals TOP and COMnA1/COMnB1//COMnC1 is set. details. ATmega8U2/16U2/32U2 Description Normal port operation, OCnA/OCnB/OCnC disconnected. WGM1[3: 11: Toggle OC1A on Compare Match, OC1B and OC1C disconnected (normal port operation). For all other WGM1 settings, normal port operation, OC1A/OC1B/OC1C disconnected. ...

Page 132

... PWM, Phase and Frequency 0 1 Correct 1 0 PWM, Phase Correct 1 1 PWM, Phase Correct 0 0 CTC 0 1 (Reserved Fast PWM 1 1 Fast PWM ATmega8U2/16U2/32U2 Update of x TOP OCRn at 0xFFFF Immediate 0x00FF TOP 0x01FF TOP 0x03FF TOP OCRnA Immediate 0x00FF TOP 0x01FF TOP 0x03FF TOP ...

Page 133

... I clk /64 (From prescaler) I clk /256 (From prescaler) I clk /1024 (From prescaler) I External clock source on Tn pin. Clock on falling edge 1 1 External clock source on Tn pin. Clock on rising edge ATmega8U2/16U2/32U2 WGM12 CS12 CS11 R/W R/W R/W R CS10 TCCR1B R/W 0 Figure 133 ...

Page 134

... Writing to the TCNTn Register blocks (removes) the compare match on the following timer clock for all compare units. 7799D–AVR–11/ FOC1A FOC1B FOC1C – TCNT1[15:8] TCNT1[7:0] R/W R/W R/W R ATmega8U2/16U2/32U2 – – – – R/W R/W R/W R See “Accessing 16-bit TCCR1C TCNT1H TCNT1L ...

Page 135

... R/W R/W R/W R R/W R/W R/W R See “Accessing 16-bit Registers” on page 110 R/W R/W R/W R See “Accessing 16-bit Registers” on page 110 – – ICIE1 ATmega8U2/16U2/32U2 OCR1A[15:8] OCR1A[7:0] R/W R/W R OCR1B[15:8] OCR1B[7:0] R/W R/W R OCR1C[15:8] OCR1C[7:0] R/W R/W R ...

Page 136

... TOVn Flag, located in TIFRn, is set – – ICF1 ATmega8U2/16U2/32U2 64.) is executed when the OCFnC Flag, located in 64.) is executed when the OCFnB Flag, located in 64.) is executed when the OCFnA Flag, located – OCF1C OCF1B OCF1A R R/W ...

Page 137

... TOVn Flag is set when the timer overflows. Refer to Flag behavior when using another WGMn[3:0] bit setting. TOVn is automatically cleared when the Timer/Countern Overflow Interrupt Vector is executed. Alternatively, TOVn can be cleared by writing a logic one to its bit location. 7799D–AVR–11/10 ATmega8U2/16U2/32U2 Table 16-4 on page 132 for the TOVn 137 ...

Page 138

... Overview The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega8U2/16U2/32U2 and peripheral devices or between several AVR devices. USART can also be used in Master SPI mode, see “USART in SPI Mode” on page 176. The Power Reduction SPI bit, PRSPI must be written to zero to enable SPI module ...

Page 139

... In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure correct sampling of the clock signal, the frequency of the SPI clock should never exceed f 7799D–AVR–11/10 ATmega8U2/16U2/32U2 Figure 17-2. The sys- SHIFT ENABLE /4 ...

Page 140

... SPI Pin Overrides Direction, Master SPI User Defined Input User Defined User Defined 1. See “Alternate Functions of Port B” on page 74 direction of the user defined SPI pins. ATmega8U2/16U2/32U2 “Alternate Port Direction, Slave SPI Input User Defined Input Input for a detailed description of how to define the 140 ...

Page 141

... Set MOSI and SCK output, all others input */ DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK); /* Enable SPI, Master, set clock rate fck/16 */ SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0); /* Start transmission */ SPDR = cData; /* Wait for transmission complete */ while(!(SPSR & (1<<SPIF))) ; 1. See “Code Examples” on page 6. ATmega8U2/16U2/32U2 141 ...

Page 142

... Read received data and return in r16,SPDR ret (1) /* Set MISO output, all others input */ DDR_SPI = (1<<DD_MISO); /* Enable SPI */ SPCR = (1<<SPE); /* Wait for reception complete */ while(!(SPSR & (1<<SPIF))) ; /* Return Data Register */ return SPDR; 1. See “Code Examples” on page 6. ATmega8U2/16U2/32U2 142 ...

Page 143

... This is clearly seen by summarizing Table 17-3 7799D–AVR–11/10 Figure 17-4. Data bits are shifted out and latched in on opposite edges of the SCK sig- and Table 17-4, as done below: ATmega8U2/16U2/32U2 Figure 143 ...

Page 144

... SCK (CPOL = 1) mode 3 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB Bit 6 LSB first (DORD = 1) LSB Bit 1 ATmega8U2/16U2/32U2 Trailing eDge Setup (Falling) Sample (Falling) Setup (Rising) Sample (Rising) Bit 4 Bit 3 Bit 2 Bit 1 LSB Bit 3 Bit 4 Bit 5 Bit 6 ...

Page 145

... Figure 17-3 and Figure 17-4 CPOL Functionality CPOL Leading Edge 0 Rising 1 Falling Figure 17-3 CPHA Functionality CPHA Leading Edge 0 Sample 1 Setup ATmega8U2/16U2/32U2 CPOL CPHA SPR1 SPR0 R/W R/W R/W R for an example. The CPOL functionality is sum- Trailing Edge Falling Rising and Figure 17-4 for an example ...

Page 146

... SPI Data Register. • Bit 5:1 – Res: Reserved Bits These bits are reserved bits in the ATmega8U2/16U2/32U2 and will always read as zero. • Bit 0 – SPI2X: Double SPI Speed Bit When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode (see clock periods ...

Page 147

... The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. Reading the regis- ter causes the Shift Register Receive buffer to be read. 7799D–AVR–11/ MSB – – – R ATmega8U2/16U2/32U2 – – – LSB R SPDR Undefined 147 ...

Page 148

... The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART highly flexible serial communication device. A simplified block diagram of the USART Transmitter is shown in accessible I/O Registers and I/O pins are shown in bold. 7799D–AVR–11/10 ATmega8U2/16U2/32U2 Figure 18-1 on page 149. CPU 148 ...

Page 149

... UCSRnA Register. When using synchronous mode (UMSELn = 1), the Data Direction Register 7799D–AVR–11/10 (1) UBRR[H:L] BAUD RATE GENERATOR UDR (Transmit) TRANSMIT SHIFT REGISTER RECEIVE SHIFT REGISTER UDR (Receive) UCSRA 1. See Figure 1-1 on page 2, Table 12-9 on page 79 ATmega8U2/16U2/32U2 Clock Generator OSC SYNC LOGIC PIN XCK CONTROL Transmitter TX CONTROL PARITY GENERATOR PIN TxD ...

Page 150

... DDR_XCK UCPOL Transmitter clock (Internal Signal). Receiver base clock (Internal Signal). Input from XCK pin (internal Signal). Used for synchronous slave operation. Clock output to XCK pin (Internal Signal). Used for synchronous master operation. XTAL pin frequency (System Clock). ATmega8U2/16U2/32U2 U2X / DDR_XCK ...

Page 151

... UBRRn The baud rate is defined to be the transfer rate in bit per second (bps) Baud rate (in bits per second, bps) System Oscillator clock frequency Contents of the UBRRHn and UBRRLn Registers, (0-4095) ATmega8U2/16U2/32U2 (1) Equation for Calculating UBRR Value UBRRn = ----------------------- - 1 16BAUD ) UBRRn = ...

Page 152

... Figure 18-2 for details. depends on the stability of the system clock source therefore recommended to osc UCPOL = 1 XCK RxD / TxD UCPOL = 0 XCK RxD / TxD Figure 18-3 shows, when UCPOLn is zero the data will be changed at ATmega8U2/16U2/32U2 f OSC < ---------- - f XCK 4 Sample Sample 152 ...

Page 153

... No transfers on the communication line (RxDn or TxDn). An IDLE line high. ⊕ even n 1 – ⊕ odd – Parity bit using even parity even odd Parity bit using odd parity Data bit n of the character n ATmega8U2/16U2/32U2 FRAME 4 [5] [6] [7] [8] [P] Sp1 [Sp2] … ⊕ ⊕ ⊕ ⊕ ⊕ ...

Page 154

... UCSRnC,r16 ret (1) /* Set baud rate */ UBRRHn = (unsigned char)(baud>>8); UBRRLn = (unsigned char)baud; /* Enable receiver and transmitter */ UCSRnB = (1<<RXENn)|(1<<TXENn); /* Set frame format: 8data, 2stop bit */ UCSRnC = (1<<USBSn)|(3<<UCSZn0); 1. See “Code Examples” on page 6. ATmega8U2/16U2/32U2 154 ...

Page 155

... UCSRnA,UDREn rjmp USART_Transmit ; Put data (r16) into buffer, sends the data out UDRn,r16 ret (1) /* Wait for empty transmit buffer */ while ( !( UCSRnA & (1<<UDREn Put data into buffer, sends the data */ UDRn = data; 1. See “Code Examples” on page 6. ATmega8U2/16U2/32U2 155 ...

Page 156

... Put data into buffer, sends the data */ UDRn = data; 1. These transmit functions are written to be general functions. They can be optimized if the con- tents of the UCSRnB is static. For example, only the TXB8 bit of the UCSRnB Register is used after initialization. 2. See “Code Examples” on page 6. ATmega8U2/16U2/32U2 156 ...

Page 157

... UDRn I/O location. The following code example shows a simple USART receive function based on polling of the Receive Complete (RXCn) Flag. When using frames with less than eight bits the most significant 7799D–AVR–11/10 ATmega8U2/16U2/32U2 157 ...

Page 158

... UCSRnA, RXCn rjmp USART_Receive ; Get and return received data from buffer in r16, UDRn ret (1) /* Wait for data to be received */ while ( !(UCSRnA & (1<<RXCn Get and return received data from buffer */ return UDRn; 1. See “Code Examples” on page 6. ATmega8U2/16U2/32U2 158 ...

Page 159

... UCSRnA; resh = UCSRnB; resl = UDRn error, return - status & (1<<FEn)|(1<<DORn)|(1<<UPEn) ) return -1; /* Filter the 9th bit, then return */ resh = (resh >> 1) & 0x01; return ((resh << resl); 1. See “Code Examples” on page 6. ATmega8U2/16U2/32U2 159 ...

Page 160

... The result of the check is stored in the receive buffer together with the received data and stop bits. The Parity Error (UPEn) Flag can then be read by software to check if the frame had a Parity Error. 7799D–AVR–11/10 “Parity Bit Calculation” on page 153 ATmega8U2/16U2/32U2 and “Parity Checker” on page 160. 160 ...

Page 161

... RxDn line is idle (i.e., no communication activity). 7799D–AVR–11/10 (1) sbis UCSRnA, RXCn ret in r16, UDRn rjmp USART_Flush (1) unsigned char dummy; while ( UCSRnA & (1<<RXCn) ) dummy = UDRn; 1. See “Code Examples” on page 6. ATmega8U2/16U2/32U2 Figure 18-5 161 ...

Page 162

... Figure 18-7 of the next frame. 7799D–AVR–11/10 RxD IDLE RxD Sample (U2X = Sample (U2X = shows the sampling of the stop bit and the earliest possible beginning of the start bit ATmega8U2/16U2/32U2 START Figure 18-6 shows the sampling of the data bits and BIT ...

Page 163

... R is the ratio of the fastest incoming data rate that can be fast accepted in relation to the receiver baud rate. and Table 18-3 list the maximum receiver baud rate error that can be tolerated. Note ATmega8U2/16U2/32U2 STOP 1 (A) ( ...

Page 164

... ATmega8U2/16U2/32U2 Recommended Max Receiver Error (%) +6.67/-6.8 +5.79/-5.88 +5.11/-5.19 +4.58/-4.54 +4.14/-4.19 +3.78/-3.83 Recommended Max Receiver Error (%) +5.66/-5.88 +4.92/-5.08 +4.35/-4.48 +3 ...

Page 165

... The reception flow can be controlled by hardware using the RTS pin. The aim of the flow control is to inform the external transmitter when the internal receive Fifo is full. Thus the transmitter can 7799D–AVR–11/10 ATmega8U2/16U2/32U2 HOST TXD RXD CTS RTS ATmega8U2/16U TXD RXD CTS RTS 165 ...

Page 166

... Figure 18-10. CTS behavior 7799D–AVR–11/10 FIFO Index RXD RTS RXD Start Byte0 RTS Read from CPU Write from CPU TXD Start Byte0 sample CTS ATmega8U2/16U2/32U2 CPU Read Stop Start Byte1 Stop 1 additional byte may be sent if the transmitter misses the RTS trig Stop ...

Page 167

... Data Register Empty interrupt (see description of the UDRIEn bit). UDREn is set after a reset to indicate that the Transmitter is ready. 7799D–AVR–11/ RXB[7:0] TXB[7:0] R/W R/W R/W R RXCn TXCn UDREn FEn R R ATmega8U2/16U2/32U2 R/W R/W R/W R DORn UPEn U2Xn MPCMn R R R/W R UDRn (Read) UDRn (Write) UCSRnA 167 ...

Page 168

... UDRIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the UDREn bit in UCSRnA is set. 7799D–AVR–11/10 “Multi-processor Communication Mode” on page RXCIEn TXCIEn UDRIEn RXENn R/W R/W R/W R ATmega8U2/16U2/32U2 164 TXENn UCSZn2 RXB8n TXB8n R/W R UCSRnB 168 ...

Page 169

... UMSELn1 UMSELn0 UPMn1 R/W R/W R UMSELn Bits Settings UMSELn1 UMSELn0 See “USART in SPI Mode” on page 176 operation ATmega8U2/16U2/32U2 UPMn0 USBSn UCSZn1 UCSZn0 R/W R/W R/W R Table 18-4.. Mode Asynchronous USART Synchronous USART (Reserved) (1) Master SPI (MSPIM) for full description of the Master SPI Mode (MSPIM) ...

Page 170

... UCSZn1 UCPOLn Bit Settings Transmitted Data Changed (Output of TxDn Pin) 0 Rising XCKn Edge 1 Falling XCKn Edge ATmega8U2/16U2/32U2 Parity Mode Disabled Reserved Enabled, Even Parity Enabled, Odd Parity UCSZn0 Character Size 0 5-bit 1 6-bit 0 7-bit 1 8-bit 0 Reserved 1 Reserved 0 Reserved 1 9-bit Received Data Sampled ...

Page 171

... UBRR[7: R/W R/W R/W R 163). The error values are calculated using the following equation: BaudRate ⎛ Closest Match Error[%] ------------------------------------------------------- - 1 = ⎝ BaudRate ATmega8U2/16U2/32U2 CTSEN RTSEN R/W R/W R/W R UBRR[11: R/W R/W R/W R/W R/W R/W R/W R Table 18-9 ...

Page 172

... ATmega8U2/16U2/32U2 f = 2.0000 MHz osc U2Xn = 1 U2Xn = 0 UBRR Error UBRR Error 95 0.0% 51 0.2% 47 0.0% 25 0.2% 23 0.0% 12 0.2% 15 0.0% 8 -3.5% 11 ...

Page 173

... Mbps ATmega8U2/16U2/32U2 f = 7.3728 MHz osc U2Xn = 0 U2Xn = 1 Error UBRR Error UBRR 0.2% 191 0.0% 383 0.2% 95 0.0% 191 0.2% 47 0.0% 95 -0.8% 31 0. ...

Page 174

... Mbps 691.2 kbps ATmega8U2/16U2/32U2 MHz f = 14.7456 MHz osc U2Xn = 1 U2Xn = 0 Error UBRR Error 575 0.0% 383 0.0% 287 0.0% 191 0.0% 143 0.0% 95 0. ...

Page 175

... Mbps 1.152 Mbps ATmega8U2/16U2/32U2 f = 20.0000 MHz osc U2Xn = 1 U2Xn = 0 Error UBRR Error 959 0.0% 520 0.0% 479 0.0% 259 0.2% 239 0.0% 129 0.2% 159 0. ...

Page 176

... USART in MSPIM is enabled (i.e. TXENn and RXENn bit set to one). The internal clock generation used in MSPIM mode is identical to the USART synchronous mas- ter mode. The baud rate or UBRRn setting can therefore be calculated using the same equations, see 7799D–AVR–11/10 Table 19-1: ATmega8U2/16U2/32U2 176 ...

Page 177

... Sample (Rising) 1 Setup (Rising) 2 Sample (Falling) 3 Setup (Falling) UCPOL=0 XCK Data setup (TXD) Data sample (RXD) XCK Data setup (TXD) Data sample (RXD) ATmega8U2/16U2/32U2 (1) Equation for Calculating UBRRn Value f OSC UBRRn = ------------------- - 1 2BAUD Trailing Edge Setup (Falling) Sample (Falling) Setup (Rising) Sample (Rising) ...

Page 178

... Contrary to the normal mode USART operation the UBRRn must then be written to the desired value after the transmitter is enabled, but before the first transmission is started. Setting UBRRn to zero before enabling the transmitter is not neces- sary if the initialization is done immediately after a reset since UBRRn is reset to zero. ATmega8U2/16U2/32U2 178 ...

Page 179

... Set MSPI mode of operation and SPI data mode 0. */ UCSRnC = (1<<UMSELn1)|(1<<UMSELn0)|(0<<UCPHAn)|(0<<UCPOLn); /* Enable receiver and transmitter. */ UCSRnB = (1<<RXENn)|(1<<TXENn); /* Set baud rate IMPORTANT: The Baud Rate must be set after the transmitter is enabled */ UBRRn = baud; 1. See “Code Examples” on page 6. ATmega8U2/16U2/32U2 179 ...

Page 180

... Wait for empty transmit buffer */ while ( !( UCSRnA & (1<<UDREn Put data into buffer, sends the data */ UDRn = data; /* Wait for data to be received */ while ( !(UCSRnA & (1<<RXCn Get and return received data from buffer */ return UDRn; 1. See “Code Examples” on page 6. ATmega8U2/16U2/32U2 180 ...

Page 181

... Bit 4:0 - Reserved Bits in MSPI mode When in MSPI mode, these bits are reserved for future use. For compatibility with future devices, these bits must be written to zero when UCSRnA is written. 7799D–AVR–11/ RXCn TXCn UDREn - R/W R/W R ATmega8U2/16U2/32U2 UCSRnA 181 ...

Page 182

... When disabled, the Transmitter will no longer override the TxDn port. • Bit 2:0 - Reserved Bits in MSPI mode When in MSPI mode, these bits are reserved for future use. For compatibility with future devices, these bits must be written to zero when UCSRnB is written. 7799D–AVR–11/10 ATmega8U2/16U2/32U2 ...

Page 183

... The UDORDn bit functionality is identical to the SPI DORD bit. 7799D–AVR–11/ UMSELn1 UMSELn0 – R/W R UMSELn Bits Settings UMSELn1 UMSELn0 ATmega8U2/16U2/32U2 – – UDORDn UCPHAn R R R/W R Table 19-3. See for full description of the normal USART Mode Asynchronous USART Synchronous USART (Reserved) Master SPI (MSPIM) ...

Page 184

... A comparison of the USART in MSPIM mode and the SPI pins is shown in 184. Table 19-4. USART_MSPIM 7799D–AVR–11/10 Comparison of USART in MSPIM mode and SPI pins. SPI Comment TxDn MOSI Master Out only RxDn MISO Master In only XCKn SCK (Functionally identical) (N/A) SS Not supported by USART in MSPIM ATmega8U2/16U2/32U2 Table 19-4 on page 184 ...

Page 185

... ATmega8U2/16U2/32U2 system clock and clock options. To comply to the USB specifications electrical characteristics, the USB Pads (D+ or D-) must be powered at 3.0V to 3.6V. As the ATmega8U2/16U2/32U2 can be powered up to 5.5V, an inter- nal regulator is provided to correctly power the USB pads. See on page 186 Figure 20-1. USB controller Block Diagram 7799D– ...

Page 186

... USB compliant, without internal regulator 3.0 2.7 USB not operational VCC min 0 UCAP 1µF VBUS UVCC UDM D+ UDP D- UVSS UVSS VSS XTAL1 ), the ATmega8U2/16U2/32U2 CC Figure 20-2 on page 186. Max Operating Frequency (MHz) 16 MHz 8 MHz 2 MHz VCC AVCC XTAL2 186 ...

Page 187

... VBUS UDM UDP UVSS UVCC UCAP 1µF VBUS VBUS UDP D+ Rs=22 UDM D- Rs=22 UVSS UGND UID UID XTAL1 ATmega8U2/16U2/32U2 VCC AVCC UCAP UVCC D+ D- UVSS VSS XTAL1 XTAL2 External 3.4V - 5.5V Power Supply AVCC VCC XTAL2 GND GND 187 ...

Page 188

... Rs=22 UVSS UGND UID UID XTAL1 1. The internal 3.3V regulator is bypassed. Disable the regulator to avoid additional power con- sumption. See the “REGCR – Regulator Control Register” on page 196 ATmega8U2/16U2/32U2 (1) External 3.0V - 3.6V Power Supply AVCC VCC XTAL2 GND GND for details. ...

Page 189

... Figure 20-7. USB controller states after reset 7799D–AVR–11/10 capacitor should be 1µF ( 10%) for correct operation. +/- illustrates the USB controller main states on power-on: Clock stopped FRZCLK = 1 (macro off) USBE = 1 USBE = 0 Device ATmega8U2/16U2/32U2 5%). +/- USBE = 0 Any other state Reset HW RESET (except from EOR) USBE = 0 HW RESET (from EOR) ...

Page 190

... WAKEUPI UDINT.4 WAKEUPE UDIEN.4 EORSTI UDINT.3 EORSTE UDIEN.3 SOFI UDINT.2 SOFE UDIEN.2 SUSPI UDINT.0 SUSPE UDIEN.0 ATmega8U2/16U2/32U2 USB General Interrupt Vector USB Endpoint/Pipe Interrupt Vector USB General Interrupt Vector Asynchronous Interrupt source (allows the CPU to wake up from power down mode) 190 ...

Page 191

... WAKEUPI interrupt is triggered (single asynchronous interrupt) 7799D–AVR–11/10 Endpoint 2 Endpoint 1 Endpoint 0 FLERRE UEIENX.7 NAKINE UEIENX.6 TXSTPE UEIENX.4 EPINT UEINT.X TXOUTE UEIENX.3 RXOUTE UEIENX.2 STALLEDE UEIENX.1 TXINE UEIENX.0 210. ATmega8U2/16U2/32U2 Endpoint 4 Endpoint 3 “UDINT – USB Device Interrupt USB Endpoi Interrupt Vec 191 ...

Page 192

... Endpoint memory does not slide. Allocation and reorganization USB memory flow Free memory Free memory 4 Lost memory 3 EPEN=0 (ALLOC= Free its memory Endpoint Disable (ALLOC=0) ATmega8U2/16U2/32U2 i-1 i+1 i+1 and k . The k Endpoint memory i+2 and upper Endpoint memory Free memory ...

Page 193

... The SUSPI flag indicated that a suspend state has been detected on the USB bus. This flag automatically put the USB pad in Idle. The detection of a non-idle event sets the WAKEUPI flag and wakes-up the USB pad. 7799D–AVR–11/10 ATmega8U2/16U2/32U2 USBE=1 & DETACH=0 & suspend ...

Page 194

... Disable PLL Suspending the USB interface • Clear Suspend Bit • Set USB suspend clock • Disable PLL 7799D–AVR–11/10 ATmega8U2/16U2/32U2 Suspend detected = USB pad power down Clear Suspend by software Clear Resume by software Resume = USB pad wake-up Power Down ...

Page 195

... USB buffers direct drive by soft- ware. When direct drive for USB buffers is enable, the UPDRV[1:0] values are output to the 7799D–AVR–11/ USBE - FRZLK - R UPWE1 UPWE0 UPDRV1 UPDRV0 R/W R/W R/W R ATmega8U2/16U2/32U2 DPI DMI Table 20-2. The possi- ...

Page 196

... Writing this bit to a logic one disables the internal 3.3V regulator. Writing this bit to a logic zero enables the regulstor. 7799D–AVR–11/10 UPWE[I:0] Bits Settings UPWE1 UPWE0 ATmega8U2/16U2/32U2 Mode Direct drive is disabled. Reserved Direct drive of DP/DM (UPDRV[1:0] values) Reserved REGDIS REGCR R/W ...

Page 197

... An endpoint can be reset at any time by setting in the UERST register the bit corresponding to the endpoint (EPRSTx). This resets: • the internal state machine on that endpoint, 7799D–AVR–11/10 ATmega8U2/16U2/32U2 Programmable size FIFO bytes, default control endpoint Programmable size FIFO bytes. Programmable size FIFO bytes with ping-pong mode. ...

Page 198

... CPU. The CPU can then access to the various endpoint registers and data. 21.6 Endpoint activation The endpoint is maintained under reset as long as the EPEN bit is not set. The following flow must be respected in order to activate an endpoint: 7799D–AVR–11/10 ATmega8U2/16U2/32U2 198 ...

Page 199

... USB device address by setting ADDEN. The only accepted address by the controller is the one stored in UADD. ADDEN and UADD shall not be written at the same time. 7799D–AVR–11/10 ATmega8U2/16U2/32U2 Endpoint Activation UENUM EPNUM=x ...

Page 200

... When the USB device controller is in full-speed mode, setting DETACH will disconnect the pull-up on the D+. Then, clearing DETACH will connect the pull-up on the D+. Figure 21-3. Detach a device in Full-speed: 7799D–AVR–11/10 UVREF Detach, then EN=1 ATmega8U2/16U2/32U2 UVREF Attach EN 200 ...

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