AT90USB82-16MUR Atmel, AT90USB82-16MUR Datasheet
AT90USB82-16MUR
Specifications of AT90USB82-16MUR
Related parts for AT90USB82-16MUR
AT90USB82-16MUR Summary of contents
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... On Chip Debug Interface (debugWIRE) • Special Microcontroller Features – Power-On Reset and Programmable Brown-out Detection – Internal Calibrated Oscillator – External and Internal Interrupt Sources ® 8-Bit Microcontroller 8-bit Microcontroller with 8/16K Bytes of ISP Flash and USB Controller AT90USB82 AT90USB162 7707F–AVR–11/10 ...
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... I/O and Packages – 22 Programable I/O Lines – QFN32 (5x5mm) / TQFP32 packages • Operating Voltages – 2.7 - 5.5V • Operating temperature – Industrial (-40°C to +85°C) • Maximum Frequency – 8 MHz at 2.7V - Industrial range – 16 MHz at 4.5V - Industrial range AT90USB82/162 2 7707F–AVR–11/10 ...
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... VCC 4 QFN32 (PCINT11) PC2 5 (OC.0B / INT0) PD0 6 (AIN0 / INT1) PD1 7 (RXD1 / AIN1 / INT2) PD2 Note: . 7707F–AVR–11/10 Pinout AT90USB82/162 Reset (PC1 / dW) 23 PC6 (OC.1A / PCINT8) 22 PC7 (INT4 / ICP1 / CLKO) PB7 (PCINT7 / OC.0A / OC.1C) 21 PB6 (PCINT6 PB5 (PCINT5) 18 PB4 (T1 / PCINT4) 17 PB3 (PDO / MISO / PCINT3) ...
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... Overview The AT90USB82/162 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By exe- cuting powerful instructions in a single clock cycle, the AT90USB82/162 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1 ...
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... As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the AT90USB82/162 as listed on page 74. ...
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... As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port C also serves the functions of various special features of the AT90USB82/162 as listed on page 76. ...
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... These code examples assume that the part specific header file is included before compilation. For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR". 7707F–AVR–11/10 AT90USB82/162 7 ...
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... While one instruction is being executed, the next instruc- tion is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory. AT90USB82/162 8 Block Diagram of the AVR Architecture ...
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... SPI, and other I/O functions. The I/O Memory can be accessed directly the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the AT90USB82/162 has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used. ...
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... The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. AT90USB82/162 ...
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... R27 R28 R29 R30 R31 Figure 4-2, each register is also assigned a data memory address, mapping them The X-, Y-, and Z-registers R27 (0x1B AT90USB82/162 Addr. 0x00 0x01 0x02 0x0D 0x0E 0x0F 0x10 0x11 0x1A X-register Low Byte 0x1B X-register High Byte 0x1C ...
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... No internal clock division is used. Figure 4-4 vard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. AT90USB82/162 12 7 R29 (0x1D) 15 ...
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... Instruction Fetch shows the internal timing concept for the Register File single clock cycle an ALU Single Cycle ALU Operation T1 clk CPU Total Execution Time Result Write Back for details. “Memory Programming” on page AT90USB82/162 “Memory Program- “Interrupts” on page 63. The list also “ ...
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... EECR |= (1<<EEPE); SREG = cSREG; /* restore SREG value (I-bit) */ When using the SEI instruction to enable interrupts, the instruction following SEI will be exe- cuted before any pending interrupts, as shown in this example. AT90USB82/162 14 ; store SREG value ; disable interrupts during timed sequence ; start EEPROM write ...
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... A return from an interrupt handling routine takes three clock cycles. During these three clock cycles, the Program Counter (three bytes) is popped back from the Stack, the Stack Pointer is incremented by three, and the I-bit in SREG is set. 7707F–AVR–11/10 ; set Global Interrupt Enable AT90USB82/162 15 ...
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... Boot Program section and Application Program section. The Flash memory has an endurance of at least 100,000 write/erase cycles. The AT90USB82/162 Program Counter (PC bits wide, thus addressing the 8K / 16K program memory locations. The operation of Boot Program section and associated Boot Lock bits for software protection are described in detail in Programming” ...
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... SRAM Data Memory Figure 5-2 The AT90USB82/162 is a complex microcontroller with more peripheral units than can be sup- ported within the 64 location reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from $060 - $0FF in SRAM, only the ST/STS/STD and LD/LDS/LDD instruc- tions can be used ...
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... EEPROM Data Memory The AT90USB82/162 contains 512 bytes of data EEPROM memory organized as a sepa- rate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Reg- ister, and the EEPROM Control Register ...
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... Initial Value • Bits 15..12 – Res: Reserved Bits These bits are reserved bits in the AT90USB82/162 and will always read as zero. • Bits 11..0 – EEAR8..0: EEPROM Address The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the 512 bytes EEPROM space ...
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... Initial Value • Bits 7..6 – Res: Reserved Bits These bits are reserved bits in the AT90USB82/162 and will always read as zero. • Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits The EEPROM Programming mode bit setting defines which programming action that will be trig- gered when writing EEPE ...
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... The examples also 7707F–AVR–11/10 for details about Boot programming. EEPROM Programming Time Number of Calibrated RC Oscillator Cycles 26,368 AT90USB82/162 “Memory Pro- Table 5-2 lists the typical pro- Typ Programming Time 3.3 ms ...
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... Wait for completion of previous write */ while(EECR & (1<<EEPE)) /* Set up address and Data Registers */ EEAR = uiAddress; EEDR = ucData; /* Write logical one to EEMPE */ EECR |= (1<<EEMPE); /* Start eeprom write by setting EEPE */ EECR |= (1<<EEPE); } Note: AT90USB82/162 22 (1) ( See “About Code Examples” on page 7. 7707F–AVR–11/10 ...
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... Set up address register */ EEAR = uiAddress; /* Start eeprom read by writing EERE */ EECR |= (1<<EERE); /* Return data from Data Register */ return EEDR; 1. See “About Code Examples” on page 7. the EEPROM data can be corrupted because the supply voltage is CC, AT90USB82/162 reset Protection circuit can CC 23 ...
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... I/O Memory The I/O space definition of the AT90USB82/162 is shown in All AT90USB82/162 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions ...
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... Modules clk I/O clk USB (48MHz) USB PLL X6 clk Pllin (8MHz) Prescaler clk XTAL (2-16 MHz) Crystal Oscillator AT90USB82/162 CPU Core RAM clk AVR Clock CPU Control Unit clk FLASH Reset Logic Watchdog Timer Source clock Watchdog clock System Clock Prescaler ...
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... The PLL always multiply its input frequency by 6. Thus the PLL clock register should be programmed by software to generate a 8MHz clock on the PLL input. 6.2 Clock Switch In the AT90USB82/162 product, the Clock Multiplexer and the System Clock Prescaler can be modified by software. 6.2.1 Exemple of use The modification can occur when the device enters in USB Suspend mode ...
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... Enable_external_clock(); while (!External_clock_ready()); // while (CLKSTA.EXTON != 1); Select_external_clock(); Enable_pll(); Disable_RC_clock(); while (!Pll_ready()); Usb_unfreeze_clock(); RCSUT1 RCSUT0 EXSUT1 R/W R/W R AT90USB82/162 upstream-resume 2 Upstream Resume from device (Suspend (UDINT.SUSPI == 1) // UDINT.SUSPI = 0; // USBCON.FRZCLK = 1; // PLLCSR.PLLE = 0; // CLKSEL0.RCE = 1; // while (CLKSTA.RCON != 1); // CLKSEL0.CLKS = 0; // CLKSEL0.EXTE = (UDINT.WAKEUPI == 1) // UDINT.WAKEUPI = 0; // CLKSEL0.EXTE = 1; // CLKSEL0.CLKS = 1; // PLLCSR.PLLE = 1; // CLKSEL0.RCE = 0; // while (PLLCSR.PLOCK != 1); ...
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... Clock configuration for the External Oscillator / Low Power Oscillator. After a reset, if the Exter- nal oscillator / Low Power Oscillator is selected by fuse bits, this part of the register is loaded with the fuse configuration. Firmware can modify it to change the start-up time after the clock switch. AT90USB82/162 ...
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... Device Clocking Options Select 1. For all fuses “1” means unprogrammed while “0” means programmed. to start oscillating and a minimum number of oscillating CC , the device issues an internal reset with a time-out delay (t CC Table 6-2. The frequency of the Watchdog Oscillator is voltage AT90USB82/162 RCON ...
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... Some initial guidelines for choosing capacitors for use with crystals are given in the manufacturer should be used. AT90USB82/162 30 “AT90USB82/162 Typical Characteristics – Preliminary Data” on page Number of Watchdog Oscillator Cycles = 5.0V) Typ Time-out ( ...
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... Start-up Times for the Low Power Crystal Oscillator Clock Selection Start-up Time from Power-down and Power-save 258 CK 258 AT90USB82/162 XTAL2 XTAL1 GND (3) Recommended Range for Capacitors C1 and C2 (pF) (2) – 101 ...
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... Watchdog Oscillator will still be used for the Watchdog Timer and for the Reset Time-out. For more information on the pre-programmed calibration value, see the section Table 6-6. Notes: AT90USB82/162 32 Start-up Times for the Low Power Crystal Oscillator Clock Selection (Continued) Start-up Time from Power-down and ...
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... Start-up times for the internal calibrated RC Oscillator clock selection Start-up Time from Power- down and Power-save Reserved 1. The device is shipped with this option selected CAL7 CAL6 CAL5 R/W R/W R/W Device Specific Calibration Value AT90USB82/162 Additional Delay from Reset (V = 5.0V 4 CAL4 CAL3 CAL2 CAL1 R/W R/W ...
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... Oscillator, can be selected when the clock is output on CLKO. If the System Clock Prescaler is used the divided system clock that is output. 6.8 System Clock Prescaler The AT90USB82/162 has a system clock prescaler, and the system clock can be divided by set- ting the AT90USB82/162 34 External Clock Drive Configuration ...
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... CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to 7707F–AVR–11/10 Table 6- CLKPCE – – – R AT90USB82/162 , clk , and clk are divided by a factor as I/O CPU FLASH CLKPS3 CLKPS2 CLKPS1 CLKPS0 R/W R/W R/W R/W See Bit Description ...
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... XTAL1). 6.9.1 Internal PLL for USB interface The internal PLL in AT90USB82/162 generates a clock frequency that is 6x multiplied from nom- inally 8 MHz input. The source of the 8 MHz PLL input clock is the output of the internal PLL clock prescaler that generates the 8 MHz. ...
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... Initial Value • Bit 7..5 – Res: Reserved Bits These bits are reserved bits in the AT90USB82/162 and always read as zero. • Bit 4..2 – PLLP2:0 PLL prescaler These bits allow to configure the PLL input prescaler to generate the 8MHz input clock for the PLL ...
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... Bit 0 – PLOCK: PLL Lock Detector When the PLOCK bit is set, the PLL is locked to the reference clock, and it is safe to enable PCK for Timer/Counter1. After the PLL is enabled, it takes about 1ms up to 100 ms for the PLL to lock. AT90USB82/162 38 7707F–AVR–11/10 ...
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... Power Distribution The AT90USB82/162 product includes an internal 5V to 3.3V regulator that allows to supply the USB pad (see Figure 7-1.) and, depending on the applica- tion, external components or even the microcontroller itself (see Figure 7-2.). Figure 7-1. USB or PS/2 connector VBus or PS/2 Vcc (5V) ...
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... Bit 0 – REGDIS: Regulator Disable Set this bit to disable the internal 3.3V regulator. This bit should be used only in a full 3.3V appli- cation. This bit is reset every case. The firmware has the responsability to set it after each reset if required. AT90USB82/162 40 3.3V configuration (3.3V) ...
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... The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s 7707F–AVR–11/10 Table 8-1 presents the different clock systems in the AT90USB82/162, and their – ...
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... When the SM2..0 bits are 111 and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter Extended Standby mode. This mode is identical to Power-save mode with the exception that the Oscillator is kept running. So Extended Standby AT90USB82/162 42 , while allowing the other clocks to run. ...
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... Active Clock Domains and Wake-up Sources in the Different Sleep Modes. Active Clock Domains Oscillators X (1) 1. Only recommended with external crystal or resonator selected as clock source. 1. For INT7:4, only level interrupt. 1. Asynchronous USB interrupt is WAKEUPI only PRTIM0 – R/W R/W R AT90USB82/162 Wake-up Sources ( ( ( ( PRTIM1 ...
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... When entering Idle mode, the Analog Comparator should be disabled if not used. In other sleep modes, the Analog Comparator is automatically disabled. However, if the Analog Comparator is set up to use the Internal Voltage Reference as input, the Analog Comparator should be dis- abled in all sleep modes. Otherwise, the Internal Voltage Reference will be enabled, AT90USB82/162 ...
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... This ensures that no I/O for details on which pins are enabled. If the input buffer input pin can cause significant current even in active mode. Digital CC AT90USB82/162 for details on how to “Brown-out Detection” on page 49 “Internal Voltage Reference” on “Digital Input for details ...
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... Reset Sources The AT90USB82/162 has five sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length. • ...
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... Reset signal RESET Pin Threshold Voltage Minimum pulse width on RESET Pin 1. The POR will not work unless the supply voltage has been below VPOT (falling) Table 9-1. The POR is activated whenever V AT90USB82/162 DATA BUS MCU Status Register (MCUSR) Delay Counters CK TIMEOUT ...
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... Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage – V the Time-out period – t Figure 9-4. AT90USB82/162 48 rise. The RESET signal is activated again, without any delay, CC decreases below the detection level. ...
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... Brown-out Detection AT90USB82/162 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V during operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as V ...
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... When the USB macro is enabled and configured with the USB reset MCU feature enabled, and if a valid USB Reset signalling is detected, the microcontroller is reset unless the USB macro that remains enabled. This allows the device to stay attached to the bus during and after the reset, while enhancing firmware reliability. AT90USB82/162 50 Brown-out Reset During Operation V ...
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... Reset Flags. 7707F–AVR–11/10 USB Reset During Operation CC DP USB Traffic – – USBRF – R See Bit Description AT90USB82/162 End of Reset USB Traffic WDRF BORF EXTRF PORF R/W R/W R/W R/W MCUSR 51 ...
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... Internal Voltage Reference AT90USB82/162 features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator. 9.8.1 Voltage Reference Enable Signals and Start-up Time The voltage reference has a start-up time that may influence the way it should be used. The ...
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... Watchdog set-up must follow timed sequences. The sequence for clearing WDE or changing time-out configuration is as follows: 7707F–AVR–11/10 Watchdog Timer 128kHz OSCILLATOR OSC/1 OSC/3 CLOCK OSC/5 DIVIDER OSC/7 WATCHDOG RESET WDE WDIF WDIE WDEWIE AT90USB82/162 WDP0 WDP1 WDP2 WDP3 MCU RESET INTERRUPT EARLY WARNING INTERRUPT 53 ...
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... Clear WDE, set WDIE and load the prescaler factor into WDTCSR in a same operation 6. Now the system is properly configured for Interrupt only mode. Inverting the two opera- tions would have been resulted into “Reset and Interrupt mode” and needed a third operation to clear WDE. AT90USB82/162 54 7707F–AVR–11/10 ...
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... Clear WDRF in MCUSR */ MCUSR &= ~(1<<WDRF); /* Write logical one to WDCE and WDE */ /* Keep old prescaler setting to prevent unintentional time-out */ WDTCSR |= (1<<WDCE) | (1<<WDE); /* Turn off WDT */ WDTCSR = 0x00; __enable_interrupt(); 1. The example code assumes that the part specific header file is included. AT90USB82/162 55 ...
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... Initial Value • Bit 7 - WDIF: Watchdog Interrupt Flag This bit is set when a time-out occurs twice in the Watchdog Timer and if the Watchdog Timer is configured for interrupt. WDIF is automatically cleared by hardware when executing the corre- AT90USB82/162 56 (1) r16, WDTCSR r16, (1<<WDCE) | (1<<WDE) ...
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... Interrupt Mode 1 0 System Reset Mode Interrupt and System 1 1 Reset Mode x x System Reset Mode 59 R/W R/W R/W R AT90USB82/162 Action on 2x Time-out None Interrupt Reset Interrupt, then go to System Reset Mode Reset WDE- WDEW- WCLKD WCLKD WIF R/W R/W R/W R ...
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... When this bit has been set by software, an interrupt will be generated on the watchdog interrupt vector when the Early warning flag is set to one by hardware. • Bit 1:0 - WCLKD[1:0]: Watchdog Timer Clock Divider – WCLKD = 0 : Clk – WCLKD = 1 : Clk – WCLKD = 2 : Clk – WCLKD = 3 : Clk AT90USB82/162 58 = Clk WDT 128k = Clk / 3 ...
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... AT90USB82/162 Watchdog Early warning Typical Reset/Interrupt Typical Time-out at Time-out 5. 128 ms 0.125 s 0.250 s 0.25 s 0.5 s 1.0 s 2 ...
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... AT90USB82/162 60 Watchdog Timer Prescale Select, DIV = 1 (CLKwdt = CLK128 / 3) Number of WDT Oscillator Cycles before 1st time-out (Early warning (2048) cycles 1 4K (4096) cycles 0 8K (8192) cycles 1 16K (16384) cycles 0 32K (32768) cycles 1 64K (65536) cycles 0 128K (131072) cycles 1 256K (262144) cycles 0 512K (524288) cycles ...
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... AT90USB82/162 Watchdog Early warning Typical Reset/Interrupt Typical Time-out at Time-out 5. 160 ms 160 ms 320 ms 320 ms 640 ms 0.625 s 1. ...
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... AT90USB82/162 62 Watchdog Timer Prescale Select, DIV = 3 (CLKwdt = CLK128 / 7) Number of WDT Oscillator Cycles before 1st time-out (Early warning (2048) cycles 1 4K (4096) cycles 0 8K (8192) cycles 1 16K (16384) cycles 0 32K (32768) cycles 1 64K (65536) cycles 0 128K (131072) cycles 1 256K (262144) cycles 0 512K (524288) cycles ...
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... Interrupts This section describes the specifics of the interrupt handling as performed in AT90USB82/162. For a general explanation of the AVR interrupt handling, refer to on page 10.1 Interrupt Vectors in AT90USB82/162 Table 10-1. Vector No 7707F–AVR–11/10 13. Reset and Interrupt Vectors Program (2) Address Source (1) $0000 RESET $0002 ...
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... BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa. AT90USB82/162 64 Reset and Interrupt Vectors (Continued) Program ...
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... Application section. If Interrupt Vectors are placed in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while executing from the Boot Loader section. Refer to the section 243 for details on Boot Lock bits. AT90USB82/162 (1) Interrupt Vectors Start Address 0x0002 Boot Reset Address + 0x0002 ...
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... MCUCR, r16 ; Move interrupts to Boot Flash section ldi r16, (1<<IVSEL) out MCUCR, r16 ret C Code Example void Move_interrupts(void Enable change of Interrupt Vectors */ MCUCR = (1<<IVCE); /* Move interrupts to Boot Flash section */ MCUCR = (1<<IVSEL); } AT90USB82/162 66 7707F–AVR–11/10 ...
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... Ground as indicated in CC for a complete list of parameters. Pxn C pin “Register Description for I/O-Ports” on page 72. Refer to the individual module sections for a full description of the alter- AT90USB82/162 Figure 11-1. Refer to “Electrical Char Logic See Figure "General Digital I/O" for Details 82 ...
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... If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to be configured as an output pin. The port pins are tri-stated when reset condition becomes active, even if no clocks are running. AT90USB82/162 68 (1) Pxn ...
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... Input 1 1 Input 0 X Output 1 X Output Figure 11-2, the PINxn Register bit and the preceding latch con- pd,max AT90USB82/162 Pull-up Comment No Tri-state (Hi-Z) Pxn will source current if ext. pulled Yes low. No Tri-state (Hi-Z) No Output Low (Sink) No Output High (Source) Figure 11-3 ...
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... The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from input with pull-ups assigned to port pins 6 and 7. The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. AT90USB82/162 70 SYSTEM CLK XXX ...
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... Figure 11-2, the digital input signal can be clamped to ground at the input of the “Alternate Port Functions” on page AT90USB82/162 /2. CC 72. 71 ...
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... Figure 11-5. Alternate Port Functions Pxn PUOExn: PUOVxn: DDOExn: DDOVxn: PVOExn: PVOVxn: DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE SLEEP: PTOExn: AT90USB82/162 72 or GND is not recommended, since this may cause excessive currents if the pin is CC (1) PUOExn PUOVxn 1 0 DDOExn DDOVxn 1 ...
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... This is the Analog Input/output to/from alternate functions. The Analog signal is connected directly to the pad, and can be used bi- Input/Output directionally JTD – – AT90USB82/162 PUD – – IVSEL , I/O Fig- 0 ...
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... PCINT5, Pin Change Interrupt source 5: The PB5 pin can serve as an external interrupt source. • T1/PCINT4, Bit 4 T1, Timer/Counter1 counter source. PCINT4, Pin Change Interrupt source 4: The PB4 pin can serve as an external interrupt source. • PDO/MISO/PCINT3 – Port B, Bit 3 AT90USB82/162 74 R ...
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... PDO, SPI Serial Programming Data Output. During Serial Program Downloading, this pin is used as data output line for the AT90USB82/162. MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI is enabled as a master, this pin is configured as an input regardless of the setting of DDB3. When the SPI is enabled as a slave, the data direction of this pin is controlled by DDB3 ...
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... DIEOE DIEOV DI AIO 11.3.3 Alternate Functions of Port C The Port C alternate function is as follows: AT90USB82/162 76 and Table 11-5 relate the alternate functions of Port B to the overriding signals Figure 11-5 on page 72. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the Overriding Signals for Alternate Functions in PB7..PB4 ...
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... RSTDISBL Fuse. Pullup is activated and output driver and digital input are deactivated when the pin is used as the RESET pin. 7707F–AVR–11/10 Port C Pins Alternate Functions Port Pin Alternate Function PC7 ICP1/INT4/CLKO PC6 PCINT8/OC1A PC5 PCINT9/OC1B PC4 PCINT10 - - PC2 PCINT11 PC1 Reset, dW PC0 XTAL2 AT90USB82/162 77 ...
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... DIEOE DIEOV DI AIO Table 11-8. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO AT90USB82/162 78 and Table 11-8 relate the alternate functions of Port C to the overriding signals Figure 11-5 on page 72. Overriding Signals for Alternate Functions in PC7..PC4 PC6/PCINT8/OC1 PC7/ICP1/INT4/CLK0 ...
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... Port D Pins Alternate Functions Alternate Function HWB/TO/INT7/CTS INT6/RTS XCK1/PCINT12 (USART1 External Clock Input/Output) INT5 INT3/TXD1 (External Interrupt3 Input or USART1 Transmit Pin) INT2/AIN1/RXD1(External Interrupt2 Input or USART1 Receive Pin) INT1/AIN0 (External Interrupt1 Input) INT0/OC0B (External Interrupt0 Input) , Bit 7 ,Bit 6 , Bit 5 , Bit 3 AT90USB82/162 Table 11-9. 79 ...
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... OC0B, Output Compare Match B output: The PD0 pin can serve as an external output for the Timer/Counter0 Output Compare. The pin has to be configured as an output (DDD0 set “one”) to serve this function. The OC0B pin is also the output pin for the PWM mode timer function. Table 11-10 shown in AT90USB82/162 80 , Bit 2 , Bit 1 , Bit 0 ...
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... INT2 INPUT/RXD1 – AIN1 INPUT 1. When enabled, the 2-wire Serial Interface enables Slew-Rate controls on the output pins PD0 and PD1. This is not shown in this table. In addition, spike filters are connected between the AIO outputs shown in the port figure. AT90USB82/162 PD5/XCK/PCINT12 PD4/INT5 ...
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... Port C Input Pins Address – PINC Bit Read/Write Initial Value 11.4.7 Port D Data Register – PORTD Bit Read/Write Initial Value 11.4.8 Port D Data Direction Register – DDRD Bit Read/Write Initial Value AT90USB82/162 PORTB7 PORTB6 PORTB5 PORTB4 R/W R/W R/W R/W 0 ...
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... Port D Input Pins Address – PIND Bit Read/Write Initial Value 7707F–AVR–11/ PIND7 PIND6 PIND5 PIND4 R/W R/W R/W R/W N/A N/A N/A N/A AT90USB82/162 PIND3 PIND2 PIND1 PIND0 R/W R/W R/W R/W N/A N/A N/A N/A PIND 83 ...
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... EIMSK Register. Then, the ISCn bit can be changed. Finally, the INTn interrupt flag should be cleared by writing a logical one to its Interrupt Flag bit (INTFn) in the EIFR Register before the interrupt is re-enabled. AT90USB82/162 84 25. Low level interrupts and the edge interrupt on INT3:0 are detected 25 ...
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... The falling edge between two samples of INTn generates an interrupt request. 1 The rising edge between two samples of INTn generates an interrupt request When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed. AT90USB82/162 Condition Min Typ 50 4 ...
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... PCI1/0 Interrupt Vector. PCINT12..8/7..0 pins are enabled individually by the PCMSK1/0 Register. 12.0.6 Pin Change Interrupt Flag Register – PCIFR Bit Read/Write Initial Value • Bit 1..0 – PCIF1- PCIF0: Pin Change Interrupt Flag 1-0 AT90USB82/162 INT7 INT6 ...
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... I/O pin. If PCINT12..8 is cleared, pin change interrupt on the corresponding I/O pin is disabled. 7707F–AVR–11/ PCINT7 PCINT6 PCINT5 PCINT4 R/W R/W R/W R PCINT12 R R R/W R AT90USB82/162 PCINT3 PCINT2 PCINT1 PCINT0 R/W R/W R/W R PCINT11 PCINT10 PCINT9 PCINT8 R/W R/W R/W R PCMSK0 PCMSK1 ...
Page 88
... Tn pin to the counter is updated. Enabling and disabling of the clock input must be done when Tn has been stable for at least one system clock cycle, otherwise risk that a false Timer/Counter clock pulse is generated. AT90USB82/162 88 ). Alternatively, one of four taps from the prescaler can be used as a ...
Page 89
... Since the edge detector uses ExtClk clk_I/O I/O Clear Synchronization Synchronization TIMER/COUNTERn CLOCK SOURCE clk TSM – – – R AT90USB82/162 CSn0 CSn1 CSn2 TIMER/COUNTERn CLOCK SOURCE – – - PSRSY R/W R /2.5. clk_I/O clk Tn ...
Page 90
... T0 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clk AT90USB82/162 90 “Pinout AT90USB82/162” on page “8-bit Timer/Counter Register Description” on page Count Clear Control Logic ...
Page 91
... Timer/Counter1 Prescalers” on page DATA BUS count clear TCNTn direction bottom Increment or decrement TCNT0 by 1. Select between increment and decrement. AT90USB82/162 for details. The Compare Match event will also 88. TOVn (Int.Req.) Clock Select Edge Detector clk Tn ...
Page 92
... WGM02:0 bits and Compare Output mode (COM0x1:0) bits. The max and bottom signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation Figure 14-3 AT90USB82/162 92 Clear TCNT0 (set all bits to zero). Timer/Counter clock, referred to as clk Tn Signalize that TCNT0 has reached maximum value ...
Page 93
... Unit, independently of whether the Timer/Counter is running or not. If the value written to TCNT0 equals the OCR0x value, the Compare Match will be missed, resulting in incorrect waveform 7707F–AVR–11/10 DATA BUS OCRnx = (8-bit Comparator ) top bottom Waveform Generator FOCn WGMn1:0 AT90USB82/162 TCNTn OCFnx (Int.Req.) OCnx COMnX1:0 93 ...
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... The port override function is independent of the Waveform Generation mode. The design of the Output Compare pin logic allows initialization of the OC0x state before the out- put is enabled. Note that some COM0x1:0 bit settings are reserved for certain modes of operation. AT90USB82/162 94 COMnx1 Waveform ...
Page 95
... Compare Match occurs between TCNT0 and OCR0A, and then counter (TCNT0) is cleared. 7707F–AVR–11/10 Table 14-2 on page 101, and for phase correct PWM refer to “Timer/Counter Timing Diagrams” on page AT90USB82/162 101. For fast PWM mode, refer to Table 14-4 on page 101. 94.). 99. ...
Page 96
... In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast AT90USB82/162 96 1 ...
Page 97
... The TCNT0 value is in the timing diagram shown as a his Table 14-3 on page 101). The actual OC0x value will only be visible ----------------- - OCnxPWM N 256 = f OC0 AT90USB82/162 OCRnx Interrupt Flag Set OCRnx Update and TOVn Interrupt Flag Set (COMnx1 (COMnx1 clk_I/O ⋅ /2 when OCR0A is set to zero. This clk_I/O 97 ...
Page 98
... In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM0x1:0 to three: Setting the COM0A0 bits to AT90USB82/162 98 14-7. The TCNT0 value is in the timing diagram shown as a histogram for illustrating ...
Page 99
... Figure 14-8 contains timing data for basic Timer/Counter operation. The figure I/O Tn /1) I/O MAX - 1 shows the same timing data, but with the prescaler enabled. AT90USB82/162 101). The actual OC0x value will only f clk_I/O = ----------------- - ⋅ N 510 OCnx has a transition from high to low even though Figure 14-7 ...
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... I/O TCNTn (CTC) OCRnx OCFnx 14.8 8-bit Timer/Counter Register Description 14.8.1 Timer/Counter Control Register A – TCCR0A Bit Read/Write AT90USB82/162 100 I/O Tn /8) MAX - 1 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC I/O Tn /8) OCRnx - 1 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fast ...
Page 101
... WGM02 = 0: Normal Port Operation, OC0A Disconnected. 1 WGM02 = 1: Toggle OC0A on Compare Match. Clear OC0A on Compare Match when up-counting. Set OC0A on 0 Compare Match when down-counting. Set OC0A on Compare Match when up-counting. Clear OC0A on 1 Compare Match when down-counting. AT90USB82/162 (1) “Fast PWM Mode” on page 96 (1) 0 ...
Page 102
... PWM mode. Table 14-7. COM0A1 AT90USB82/162 102 1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Com- pare Match is ignored, but the set or clear is done at TOP. See page 98 for more details. Table 14-2 shows the COM0A1:0 bit functionality when the WGM02:0 bits ...
Page 103
... Note: • Bits 3, 2 – Res: Reserved Bits These bits are reserved bits in the AT90USB82/162 and will always read as zero. • Bits 1:0 – WGM01:0: Waveform Generation Mode Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting ...
Page 104
... If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. 14.8.3 Timer/Counter Register – TCNT0 Bit Read/Write Initial Value AT90USB82/162 104 “Timer/Counter Control Register A – TCCR0A” on page Clock Select Bit Description CS01 CS00 Description 0 ...
Page 105
... Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter 0 Inter- rupt Flag Register – TIFR0. 7707F–AVR–11/ OCR0A[7:0] R/W R/W R/W R OCR0B[7:0] R/W R/W R/W R – – – – AT90USB82/162 R/W R/W R/W R R/W R/W R/W R – OCIE0B OCIE0A TOIE0 R R/W R/W R OCR0A OCR0B TIMSK0 105 ...
Page 106
... Initial Value • Bits 7..3 – Res: Reserved Bits These bits are reserved bits in the AT90USB82/162 and will always read as zero. • Bit 2 – OCF0B: Timer/Counter 0 Output Compare B Match Flag The OCF0B bit is set when a Compare Match occurs between the Timer/Counter and the data in OCR0B – ...
Page 107
... I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit loca- tions are listed in the The Power Reduction Timer/Counter1 bit, PRTIM1, in page 43 7707F–AVR–11/10 “Pinout AT90USB82/162” on page “16-bit Timer/Counter 1 with PWM” on page must be written to zero to enable Timer/Counter1 module. AT90USB82/162 Figure 15-1 ...
Page 108
... The output from the clock select logic is referred to as the timer clock (clk The double buffered Output Compare Registers (OCRnA/B/C) are compared with the Timer/Counter value at all time. The result of the compare can be used by the Waveform Gener- ator to generate a PWM or variable frequency output on the Output Compare pin (OCnA/B/C). AT90USB82/162 108 Count Clear ...
Page 109
... The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be one of the fixed values: 0x00FF, 0x01FF, or 0x03FF the value stored in the OCRnA or ICRn Register. The assignment is dependent of the mode of operation. AT90USB82/162 (See 109 ...
Page 110
... The following code examples show how atomic read of the TCNTn Register contents. Reading any of the OCRnA/B/C or ICRn Registers can be done by using the same principle. AT90USB82/162 110 (1) (1) 1. See “ ...
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... Restore global interrupt flag out SREG,r18 ret (1) unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ __disable_interrupt(); /* Read TCNTn into TCNTn; /* Restore global interrupt flag */ SREG = sreg; return i; 1. See “About Code Examples” on page 7. AT90USB82/162 111 ...
Page 112
... The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the Clock Select logic which is controlled by the Clock Select (CSn2:0) bits located in the Timer/Counter control Register B (TCCRnB). For details on clock sources and prescaler, see AT90USB82/162 112 (1) (1) 1. See “ ...
Page 113
... Signalize that TCNTn has reached minimum value (zero). ). The clk can be generated from an external or internal clock source present or not. A CPU write overrides (has priority over) all counter clear “Modes of Operation” on page AT90USB82/162 TOVn (Int.Req.) Clock Select Edge Detector clk Tn Control Logic ( From Prescaler ) TOP BOTTOM 119 ...
Page 114
... TCNTn value is copied into ICRn Register. If enabled (TICIEn = 1), the input capture flag generates an input capture interrupt. The ICFn flag is automatically cleared when the interrupt is executed. Alternatively the ICFn flag can be cleared by software by writing a logical one to its I/O bit location. AT90USB82/162 114 TEMP (8-bit) ICRnH (8-bit) ...
Page 115
... Even though the Input Capture interrupt has relatively high priority, the maximum interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests. 7707F–AVR–11/10 109. AT90USB82/162 “Accessing 16-bit Registers” (Figure 13-1 on page 88). The edge detector is also 115 ...
Page 116
... Compare unit (A/B/C). The elements of the block diagram that are not directly a part of the Out- put Compare unit are gray shaded. Figure 15-4. Output Compare Unit, Block Diagram AT90USB82/162 116 (See “Modes of Operation” on page shows a block diagram of the Output Compare unit. The small “n” in the register and ...
Page 117
... Normal mode. The OCnx Register keeps its value even when changing between Waveform Generation modes. Be aware that the COMnx1:0 bits are not double buffered together with the compare value. Changing the COMnx1:0 bits will take effect immediately. 7707F–AVR–11/10 109. AT90USB82/162 “Accessing 16-bit Registers” 117 ...
Page 118
... The Waveform Generator uses the COMnx1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COMnx1 tells the Waveform Generator that no action on the OCnx Register performed on the next compare match. For compare output actions in the AT90USB82/162 118 Waveform ...
Page 119
... OCRnA or ICRn, and then counter (TCNTn) is cleared. 7707F–AVR–11/10 Table 15-1 on page 129. For fast PWM mode refer to 118.) “Timer/Counter Timing Diagrams” on page Figure AT90USB82/162 Table 15-2 on Table 15-3 on 126. 15-6. The counter value (TCNTn) 119 ...
Page 120
... PWM modes that use dual-slope operation. This high fre- quency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capaci- tors), hence reduces total system cost. AT90USB82/162 120 1 2 ...
Page 121
... The OCRnA Register however, is double buffered. This feature allows the OCRnA I/O location 7707F–AVR–11/10 ( log TOP R = ---------------------------------- - FPWM log AT90USB82/162 ) Figure 15-7. The figure OCRnx / TOP Update and TOVn Interrupt Flag Set and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) (COMnx1 (COMnx1 ...
Page 122
... However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined by either ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to AT90USB82/162 122 Table on page f ...
Page 123
... The reason for this can be found in the time of update of the OCRnx Reg- 7707F–AVR–11/ log + 1 TOP R = ---------------------------------- - PCPWM log Figure 15-8 AT90USB82/162 Figure 15-8. The figure OCRnx/TOP Update and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TOVn Interrupt Flag Set (Interrupt on Bottom) (COMnx1 (COMnx1 illustrates, changing the 123 ...
Page 124
... OCRnx Register is updated by the OCRnx Buffer Register, (see 8 and Figure The PWM resolution for the phase and frequency correct PWM mode can be defined by either ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and AT90USB82/162 124 f OCnxPCPWM 15-9). Table 15-3 on page ...
Page 125
... R = ---------------------------------- - PFCPWM Figure 15-9. The figure shows phase and frequency correct shows the output generated is, in contrast to the phase correct mode, symmetri- AT90USB82/162 ( ) + 1 TOP log OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) OCRnx/TOP Updateand TOVn Interrupt Flag Set ...
Page 126
... Flags are set, and when the OCRnx Register is updated with the OCRnx buffer value (only for modes utilizing double buffering). Figure 15-10. Timer/Counter Timing Diagram, Setting of OCFnx, no Prescaling (clk TCNTn OCRnx OCFnx Figure 15-11 AT90USB82/162 126 f OCnxPFCPWM Figure 15-10 clk I/O clk ...
Page 127
... FPWM) TCNTn TOP - 1 TOVn (FPWM) and ICFn (if used as TOP) OCRnx Old OCRnx Value (Update at TOP) shows the same timing data, but with the prescaler enabled. AT90USB82/162 OCRnx OCRnx + 1 OCRnx Value TOP BOTTOM TOP TOP - 1 New OCRnx Value /8) clk_I/O OCRnx + 2 ...
Page 128
... OCnC pin must be set in order to enable the output driver. When the OCnA, OCnB or OCnC is connected to the pin, the function of the COMnx1:0 bits is dependent of the WGMn3:0 bits setting. the WGMn3:0 bits are set to a normal or a CTC mode (non-PWM). AT90USB82/162 128 I/O Tn ...
Page 129
... COMnA1/COMnB1/COMnC1 is set. In this case the compare match is ignored, but the set or clear is done at TOP. See “Fast PWM Mode” on page 96. shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the phase AT90USB82/162 Description Normal port operation, OCnA/OCnB/OCnC disconnected. Toggle OCnA/OCnB/OCnC on compare match. ...
Page 130
... Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. AT90USB82/162 130 Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM COMnA0/COMnB0/ ...
Page 131
... AT90USB82/162 (1) Update of Timer/Counter Mode OCRn of Operation TOP at 0xFFF Immedi Normal F ate PWM, Phase Correct, 0x00F TOP 8-bit F PWM, Phase Correct, 0x01F TOP 9-bit F PWM, Phase Correct, 0x03F TOP 10-bit F OCRn Immedi CTC A ate 0x00F Fast PWM, 8-bit TOP F 0x01F Fast PWM, 9-bit ...
Page 132
... Bit 4:3 – WGMn3:2: Waveform Generation Mode See TCCRnA Register description. • Bit 2:0 – CSn2:0: Clock Select The three clock select bits select the clock source to be used by the Timer/Counter, see 14-1 and Table 15-5. CSn2 AT90USB82/162 132 ICNC1 ICES1 – WGM13 R/W R ...
Page 133
... Writing to the TCNTn Register blocks (removes) the compare match on the following timer clock for all compare units. 7707F–AVR–11/ FOC1A FOC1B FOC1C – TCNT1[15:8] TCNT1[7:0] R/W R/W R/W R AT90USB82/162 – – – – R/W R/W R/W R See “Accessing 16-bit TCCR1C TCNT1H TCNT1L ...
Page 134
... CPU accesses these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. 15.10.9 Timer/Counter1 Interrupt Mask Register – TIMSK1 Bit Read/Write Initial Value • Bit 5 – ICIEn: Timer/Countern, Input Capture Interrupt Enable AT90USB82/162 134 OCR1A[15:8] OCR1A[7:0] R/W ...
Page 135
... TOVn Flag, located in TIFRn, is set – – ICF1 AT90USB82/162 63.) is executed when the OCFnC Flag, located in 63.) is executed when the OCFnB Flag, located in 63.) is executed when the OCFnA Flag, located – OCF1C OCF1B OCF1A R R/W ...
Page 136
... TOVn Flag is set when the timer overflows. Refer to Flag behavior when using another WGMn3:0 bit setting. TOVn is automatically cleared when the Timer/Countern Overflow Interrupt Vector is executed. Alternatively, TOVn can be cleared by writing a logic one to its bit location. AT90USB82/162 136 Table 15-4 on page 131 for the TOVn ...
Page 137
... Serial Peripheral Interface – SPI The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the AT90USB82/162 SPI includes the following features: • Full-duplex, Three-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • ...
Page 138
... SPI Data Register before the next character has been completely shifted in. Oth- erwise, the first byte is lost. In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure correct sampling of the clock signal, the frequency of the SPI clock should never exceed f AT90USB82/162 138 SHIFT ENABLE /4 ...
Page 139
... SPI Pin Overrides Direction, Master SPI User Defined Input User Defined User Defined 1. See “Alternate Functions of Port B” on page 74 direction of the user defined SPI pins. AT90USB82/162 “Alternate Port Direction, Slave SPI Input User Defined Input Input for a detailed description of how to define the 139 ...
Page 140
... SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0); } void SPI_MasterTransmit(char cData Start transmission */ SPDR = cData; /* Wait for transmission complete */ while(!(SPSR & (1<<SPIF))) } Note: AT90USB82/162 140 (1) r17,(1<<DD_MOSI)|(1<<DD_SCK) DDR_SPI,r17 r17,(1<<SPE)|(1<<MSTR)|(1<<SPR0) SPCR,r17 SPDR,r16 (1) ; ...
Page 141
... Read received data and return in r16,SPDR ret (1) /* Set MISO output, all others input */ DDR_SPI = (1<<DD_MISO); /* Enable SPI */ SPCR = (1<<SPE); /* Wait for reception complete */ while(!(SPSR & (1<<SPIF))) ; /* Return Data Register */ return SPDR; 1. See “About Code Examples” on page 7. AT90USB82/162 141 ...
Page 142
... When the DORD bit is written to zero, the MSB of the data word is transmitted first. • Bit 4 – MSTR: Master/Slave Select This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic zero configured as an input and is driven low while MSTR is set, MSTR will be cleared, AT90USB82/162 142 7 6 ...
Page 143
... Relationship Between SCK and the Oscillator Frequency SPR1 SPIF WCOL – – AT90USB82/162 for an example. The CPOL functionality is sum- Trailing Edge Rising Falling Falling Rising and Figure 16-4 for an example. The CPOL Trailing Edge Sample Setup Setup Sample SPR0 SCK Frequency osc osc osc f / ...
Page 144
... SPI Data Register. • Bit 5..1 – Res: Reserved Bits These bits are reserved bits in the AT90USB82/162 and will always read as zero. • Bit 0 – SPI2X: Double SPI Speed Bit When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode (see clock periods ...
Page 145
... SCK (CPOL = 1) mode 3 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB Bit 6 LSB first (DORD = 1) LSB Bit 1 AT90USB82/162 Trailing eDge Setup (Falling) Sample (Falling) Setup (Rising) Sample (Rising) Bit 4 Bit 3 Bit 2 Bit 1 LSB Bit 3 Bit 4 Bit 5 Bit 6 ...
Page 146
... Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete • Multi-processor Communication Mode • Double Speed Asynchronous Communication Mode 17.1 Overview A simplified block diagram of the USART Transmitter is shown in accessible I/O Registers and I/O pins are shown in bold. AT90USB82/162 146 Figure 17-1 on page 147. CPU 7707F–AVR–11/10 ...
Page 147
... UCSRnA Register. When using synchronous mode (UMSELn = 1), the Data Direction Register 7707F–AVR–11/10 (1) UBRR[H:L] BAUD RATE GENERATOR UDR (Transmit) TRANSMIT SHIFT REGISTER RECEIVE SHIFT REGISTER UDR (Receive) UCSRA 1. See Figure 1-1 on page 3, Table 11-9 on page 79 AT90USB82/162 Clock Generator OSC SYNC LOGIC PIN XCK CONTROL Transmitter TX CONTROL PARITY GENERATOR PIN TxD ...
Page 148
... Receiver’s clock and data recovery units. However, the recovery units use a state machine that uses states depending on mode set by the state of the UMSELn, U2Xn and DDR_XCKn bits. AT90USB82/162 148 shows a block diagram of the clock generation logic. ...
Page 149
... UBRRn The baud rate is defined to be the transfer rate in bit per second (bps) Baud rate (in bits per second, bps) System Oscillator clock frequency Contents of the UBRRHn and UBRRLn Registers, (0-4095) AT90USB82/162 (1) Equation for Calculating UBRR Value f OSC UBRRn = ----------------------- - 1 – 16BAUD ...
Page 150
... The USART accepts all 30 combinations of the following as valid frame formats: • 1 start bit • data bits • no, even or odd parity bit • stop bits AT90USB82/162 150 Figure 17-2 for details. depends on the stability of the system clock source therefore recommended to osc ...
Page 151
... No transfers on the communication line (RxDn or TxDn). An IDLE line high. ⊕ even n 1 – ⊕ odd – Parity bit using even parity even odd Parity bit using odd parity Data bit n of the character n AT90USB82/162 FRAME 4 [5] [6] [7] [8] [P] Sp1 [Sp2] … ⊕ ⊕ ⊕ ⊕ ⊕ ...
Page 152
... However, many applications use a fixed setting of the baud and control registers, and for these types of applications the initialization code can be placed directly in the main routine combined with initialization code for other I/O modules. AT90USB82/162 152 (1) UBRRHn, r17 UBRRLn, r16 r16, (1< ...
Page 153
... UCSRnA,UDREn rjmp USART_Transmit ; Put data (r16) into buffer, sends the data out UDRn,r16 ret (1) /* Wait for empty transmit buffer */ while ( !( UCSRnA & (1<<UDREn Put data into buffer, sends the data */ UDRn = data; 1. See “About Code Examples” on page 7. AT90USB82/162 153 ...
Page 154
... When the Data Register Empty Interrupt Enable (UDRIEn) bit in UCSRnB is written to one, the USART Data Register Empty Interrupt will be executed as long as UDREn is set (provided that global interrupts are enabled). UDREn is cleared by writing UDRn. When interrupt-driven data transmission is used, the Data Register Empty interrupt routine must either write new data to AT90USB82/162 154 (1)(2) UCSRnB,TXB8 ...
Page 155
... UDRn I/O location. The following code example shows a simple USART receive function based on polling of the Receive Complete (RXCn) Flag. When using frames with less than eight bits the most significant 7707F–AVR–11/10 AT90USB82/162 155 ...
Page 156
... UDRn I/O location will change the state of the receive buffer FIFO and consequently the TXB8n, FEn, DORn and UPEn bits, which all are stored in the FIFO, will change. The following code example shows a simple USART receive function that handles both nine bit characters and the status bits. AT90USB82/162 156 (1) r16, UDRn (1) ...
Page 157
... UCSRnA; resh = UCSRnB; resl = UDRn error, return - status & (1<<FEn)|(1<<DORn)|(1<<UPEn) ) return -1; /* Filter the 9th bit, then return */ resh = (resh >> 1) & 0x01; return ((resh << resl); 1. See “About Code Examples” on page 7. AT90USB82/162 157 ...
Page 158
... The result of the check is stored in the receive buffer together with the received data and stop bits. The Parity Error (UPEn) Flag can then be read by software to check if the frame had a Parity Error. AT90USB82/162 158 “Parity Bit Calculation” on page 151 and “ ...
Page 159
... RxDn line is idle (i.e., no communication activity). 7707F–AVR–11/10 (1) sbis UCSRnA, RXCn ret in r16, UDRn rjmp USART_Flush (1) unsigned char dummy; while ( UCSRnA & (1<<RXCn) ) dummy = UDRn; 1. See “About Code Examples” on page 7. AT90USB82/162 Figure 17-5 159 ...
Page 160
... RxDn pin. The recovery process is then repeated until a complete frame is received. Including the first stop bit. Note that the Receiver only uses the first stop bit of a frame. Figure 17-7 of the next frame. AT90USB82/162 160 RxD IDLE 0 ...
Page 161
... R is the ratio of the fastest incoming data rate that can be fast accepted in relation to the receiver baud rate. and Table 17-3 list the maximum receiver baud rate error that can be tolerated. Note AT90USB82/162 STOP 1 (A) ( ...
Page 162
... When the frame type bit (the first stop or the ninth bit) is one, the frame contains an address. When the frame type bit is zero the frame is a data frame. AT90USB82/162 162 (%) ...
Page 163
... The reception flow can be controlled by hardware using the RTS pin. The aim of the flow control is to inform the external transmitter when the internal receive Fifo is full. Thus the transmitter can 7707F–AVR–11/10 HOST TXD RXD CTS RTS AT90USB82/162 AT90USB82/162 TXD RXD CTS RTS 163 ...
Page 164
... The aim of the flow control is to stop transmission when the receiver is full of data (CTS = 1). CTS usage and so associated flow control is enabled using CTSEN bit in UCSRnD. The CTS pin is sampled at each CPU write and at the middle of the last stop bit that is curently being sent. Figure 17-10. CTS behavior AT90USB82/162 164 FIFO Index RXD ...
Page 165
... Data Register Empty interrupt (see description of the UDRIEn bit). UDREn is set after a reset to indicate that the Transmitter is ready. 7707F–AVR–11/ RXB[7:0] TXB[7:0] R/W R/W R/W R RXCn TXCn UDREn FEn R R AT90USB82/162 R/W R/W R/W R DORn UPEn U2Xn MPCMn R R R/W R UDRn (Read) UDRn (Write) UCSRnA 165 ...
Page 166
... Writing this bit to one enables interrupt on the UDREn Flag. A Data Register Empty interrupt will be generated only if the UDRIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the UDREn bit in UCSRnA is set. AT90USB82/162 166 “Multi-processor Communication Mode” on page ...
Page 167
... UMSELn1 UMSELn0 UPMn1 R/W R/W R UMSELn0 Mode 0 Asynchronous USART 1 Synchronous USART 0 (Reserved) 1 Master SPI (MSPIM) 1. See “USART in SPI Mode” on page 173 operation AT90USB82/162 UPMn0 USBSn UCSZn1 UCSZn0 R/W R/W R/W R Table 17-4.. (1) for full description of the Master SPI Mode (MSPIM) 0 ...
Page 168
... The UCPOLn bit sets the relationship between data output change and data input sample, and the synchronous clock (XCKn). Table 17-8. UCPOLn Bit Settings UCPOLn Transmitted Data Changed (Output of TxDn Pin) 0 Rising XCKn Edge 1 Falling XCKn Edge AT90USB82/162 168 UPMn0 Parity Mode 0 Disabled 1 Reserved 0 Enabled, Even Parity ...
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... R/W R/W R – – – – UBRR[7: R/W R/W R/W R 161). The error values are calculated using the following equation: BaudRate ⎛ Error[%] = ------------------------------------------------------- - 1 ⎝ BaudRate AT90USB82/162 CTSEN RTSEN R/W R/W R/W R UBRR[11: R/W R/W R/W R/W R/W R/W R/W R Table 17-9 to “ ...
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... Max. 62.5 kbps 125 kbps 1. UBRR = 0, Error = 0.0% AT90USB82/162 170 f = 1.8432 MHz osc U2Xn = 0 U2Xn = 1 Error UBRR Error UBRR 0.2% 47 0.0% 95 0.2% 23 0.0% 47 0.2% 11 0.0% 23 -3. ...
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... Mbps AT90USB82/162 f = 7.3728 MHz osc U2Xn = 0 U2Xn = 1 Error UBRR Error UBRR 0.2% 191 0.0% 383 0.2% 95 0.0% 191 0.2% 47 0.0% 95 -0.8% 31 0. ...
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... Max. 0.5 Mbps 1. UBRR = 0, Error = 0.0% AT90USB82/162 172 11.0592 f = osc U2Xn = 0 Error UBRR Error UBRR -0.1% 287 0.0% 0.2% 143 0.0% 0.2% 71 0.0% 0.6% 47 0.0% 0.2% 35 0.0% -0.8% 23 0.0% ...
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... Mbps 1.152 Mbps AT90USB82/162 f = 20.0000 MHz osc U2Xn = 1 U2Xn = 0 Error UBRR Error 959 0.0% 520 0.0% 479 0.0% 259 0.2% 239 0.0% 129 0.2% 159 0. ...
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... The baud rate or UBRRn setting can therefore be calculated using the same equations, see Table 18-1. Equations for Calculating Baud Rate Register Setting Operating Mode Synchronous Master mode Note: BAUD f OSC UBRRn AT90USB82/162 174 Table 18-1: Equation for Calculating Baud Rate f OSC BAUD = -------------------------------------- - ( ...
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... Sample (Falling) 3 Setup (Falling) UCPOL=0 XCK Data setup (TXD) Data sample (RXD) XCK Data setup (TXD) Data sample (RXD) AT90USB82/162 Trailing Edge Setup (Falling) Sample (Falling) Setup (Rising) Sample (Rising) UCPOL=1 XCK Data setup (TXD) Data sample (RXD) XCK Data setup (TXD) ...
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... The examples assume polling (no interrupts enabled). The baud rate is given as a function parameter. For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 registers. AT90USB82/162 176 To ensure immediate initialization of the XCKn output the baud-rate register (UBRRn) must be zero at the time the transmitter is enabled ...
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... UCSRnC = (1<<UMSELn1)|(1<<UMSELn0)|(0<<UCPHAn)|(0<<UCPOLn); /* Enable receiver and transmitter. */ UCSRnB = (1<<RXENn)|(1<<TXENn); /* Set baud rate IMPORTANT: The Baud Rate must be set after the transmitter is enabled */ UBRRn = baud; 1. See “About Code Examples” on page 7. AT90USB82/162 177 ...
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... Get and return received data from buffer */ return UDRn; } Note: AT90USB82/162 178 To keep the input buffer in sync with the number of data bytes transmitted, the UDRn register must be read once for each byte transmitted. The input buffer operation is identical to normal USART mode, i. overflow occurs the character last received will be lost, not the first data in the buf- fer ...
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... Bit 4:0 - Reserved Bits in MSPI mode When in MSPI mode, these bits are reserved for future use. For compatibility with future devices, these bits must be written to zero when UCSRnA is written. 7707F–AVR–11/ RXCn TXCn UDREn - R/W R/W R AT90USB82/162 UCSRnA 179 ...
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... When disabled, the Transmitter will no longer override the TxDn port. • Bit 2:0 - Reserved Bits in MSPI mode When in MSPI mode, these bits are reserved for future use. For compatibility with future devices, these bits must be written to zero when UCSRnB is written. AT90USB82/162 180 7 6 ...
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... The UCPOLn bit functionality is identical to the SPI CPOL bit. 7707F–AVR–11/ UMSELn1 UMSELn0 - - R/W R Mode Asynchronous USART Synchronous USART (Reserved) Master SPI (MSPIM) AT90USB82/162 UDORDn UCPHAn UCPOLn R R/W R/W R Table 18-3. See for full description of the normal UCSRnC “USART 181 ...
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... Pin control differs due to the master only operation of the USART in MSPIM mode. A comparison of the USART in MSPIM mode and the SPI pins is shown in 182. Table 18-4. Comparison of USART in MSPIM mode and SPI pins. USART_MSPIM TxDn RxDn XCKn (N/A) AT90USB82/162 182 SPI Comment MOSI Master Out only MISO Master In only SCK (Functionally identical) ...
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... Digital Phase Locked Loop (DPLL) block, which is compliant with the jitter specifica- tion of the USB bus. To comply the USB Electrical characteristics, USB Pads (D+ or D-) should be powered within the 3.0 to 3.6V range. As AT90USB82/162 can be powered up to 5.5V, the internal regulator provides the USB pads power supply. 7707F–AVR–11/10 ...
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... Figure 19-1. USB controller Block Diagram overview 19.3 Typical Application Implementation Depending on the target application power supply, the AT90USB82/162 requires different hard- ware typical implementations. Figure 19-2. Operating modes versus frequency and power-supply AT90USB82/162 184 UVCC Regulator UCAP clk 48MHz D- DPLL ...
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... Figure 19-3. Typical Bus powered application with 5V I/O VBUS UDP UDM UVSS Figure 19-4. Typical Bus powered application with 3V I/O VBUS UDM UDP UVSS 7707F–AVR–11/10 VCC UCAP 1µF UVCC D+ D- UVSS VSS XTAL1 XTAL2 VCC UCAP 1µF UVCC D+ D- UVSS VSS XTAL1 XTAL2 AT90USB82/162 185 ...
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... Self Powered device Figure 19-5. Typical Self powered application with 3.4V to 5.5V I/O UDP UDM UVSS Figure 19-6. Typical Self powered application with 3.0V to 3.6 I/O UDP UDM UVSS AT90USB82/162 186 UVCC AVCC UCAP 1µF D+ Rs=22 D- Rs=22 UGND XTAL1 XTAL2 ...
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... When the USB controller is in reset state: • USBE is not set 7707F–AVR–11/10 capacitor should be 1µF ( 10%) for correct operation. +/- Clock stopped FRZCLK=1 Macro off USBE=1 USBE=0 Dev ice HW RESET from EOR AT90USB82/162 5%). +/- <any other USBE=0 state> Reset HW RESET (excepted from EOR) USBE=0 187 ...
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... The macro distinguishes between USB General events in opposition with USB Endpoints events that are relevant with data transfers relatives to each endpoint. Figure 19-9. USB General interrupt vector sources UPRSMI UDINT.6 EORSMI UDINT.5 WAKEUPI UDINT.4 EORSTI UDINT.3 UDINT.2 UDINT.0 AT90USB82/162 188 USB Device Interrupt Endpoint Interrupt UPRSME UDIEN.6 EORSME UDIEN.5 WAKEUPE UDIEN.4 EORSTE UDIEN ...
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... USB Endpoint Interrupt vector. The user may determine the source (endpoint) of the interrupt by reading the UEINT register, and then handle the event detected by polling the different flags. 7707F–AVR–11/10 Endpoint 4 Endpoint 3 Endpoint 2 Endpoint 1 Endpoint 0 EPINT UEINT.X AT90USB82/162 USB Endpoint Interrupt Vector 189 ...
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... Endpoint memory automatically “slides” down. Note that the “k memory does not slide. The following figure illustrates the allocation and reorganization of the USB memory in a typical example: AT90USB82/162 190 i ” is done when its ALLOC bit is set. Then, the hardware allo- i-1 ” ...
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... In the “idle” mode, the pad is put in low power consumption mode. • In the “active” mode, the pad is working. 7707F–AVR–11/10 Allocation and reorganization USB memory flow Free memory Free memory 4 Lost memory 3 EPEN=0 (ALLOC= Free its memory Endpoint Disable (ALLOC=0) AT90USB82/162 Free memory (bigger size Endpoint Activatation Conflict 191 ...
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... D+/D- Read/write The level of D+ and D- can be read and written using the UPOE register. The USB controller has to be enabled to write a value. For read operation, the USB controller can be enabled or disabled. AT90USB82/162 192 USBE=1 & DETACH=0 & suspend Idle mode ...
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... Clear this bit for normal operation and access the DPR through the endpoint FIFO. • 6-0 – Reserved The value read from these bits is always 0. Do not set these bits. Bit Read/Writ e Initial Val- ue 7707F–AVR–11/ USBE - FRZLK - R DPACC - - - R DPADD7:0 R/W R/W R/W R AT90USB82/162 R/W R/W R/W R USBCON UDPADDH UDPADDL 193 ...
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... This bit is set to zero by hardware if a ‘0’ is read on D- (USB pad). 19.10 USB Software Operating modes Depending on the USB operating mode, the software should perform some the following operations: Power On the USB interface • Configure PLL interface • Enable PLL • Check PLL lock AT90USB82/162 194 UPWE1 UPWE0 ...
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... Disable PLL • Be sure to have interrupts enabled (WAKEUPE) to exit sleep mode • Put the MCU in sleep mode Resuming the USB interface • Enable PLL • Wait PLL lock • Clear USB suspend clock • Clear Resume information 7707F–AVR–11/10 AT90USB82/162 195 ...
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... An endpoint can be reset at any time by setting in the UERST register the bit corresponding to the endpoint (EPRSTx). This resets: • the internal state machine on that endpoint, • the Rx and Tx banks are cleared and their internal pointers are restored, AT90USB82/162 196 <any other state> ...
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... CPU. The CPU can then access to the various endpoint registers and data. 20.6 Endpoint activation The endpoint is maintained under reset as long as the EPEN bit is not set. The following flow must be respected in order to activate an endpoint: 7707F–AVR–11/10 AT90USB82/162 197 ...
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... USB device address by setting ADDEN. The only accepted address by the controller is the one stored in UADD. ADDEN and UADD shall not be written at the same time. UADD contains the default address 00h after a power- USB reset. AT90USB82/162 198 Endpoint Activation ...
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... When the USB device controller is in full-speed mode, setting DETACH will disconnect the pull-up on the D+ . Then, clearing DETACH will connect the pull-up on the D+. Figure 20-3. Detach a device in Full-speed: 7707F–AVR–11/10 UVREF Detach, then EN=1 AT90USB82/162 UVREF Attach EN 199 ...
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... STALL request flag and can return to the main task, waiting for the next SETUP request GET_DESCRIPTOR. The firmware sets the STALL request just after receiving the status. All extra status will be automatically STALL’ed until the next SETUP request. AT90USB82/162 200 7707F–AVR–11/10 ...