AT90USB162-16AUR Atmel, AT90USB162-16AUR Datasheet
AT90USB162-16AUR
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AT90USB162-16AURTR
AT90USB162-16AUTR
AT90USB162-16AUTR
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AT90USB162-16AUR Summary of contents
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... On Chip Debug Interface (debugWIRE) • Special Microcontroller Features – Power-On Reset and Programmable Brown-out Detection – Internal Calibrated Oscillator – External and Internal Interrupt Sources ® 8-Bit Microcontroller 8-bit Microcontroller with 8/16K Bytes of ISP Flash and USB Controller AT90USB82 AT90USB162 7707F–AVR–11/10 ...
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Five Sleep Modes: Idle, Power-save, Power-down, Standby, and Extended Standby • I/O and Packages – 22 Programable I/O Lines – QFN32 (5x5mm) / TQFP32 packages • Operating Voltages – 2.7 - 5.5V • Operating temperature – Industrial (-40°C to ...
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Pin Configurations Figure 1- XTAL1 2 (PC0) XTAL2 GND 3 VCC 4 QFN32 (PCINT11) PC2 5 (OC.0B / INT0) PD0 6 (AIN0 / INT1) PD1 7 (RXD1 / AIN1 / INT2) PD2 8 9 ...
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Overview The AT90USB82/162 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By exe- cuting powerful instructions in a single clock cycle, the AT90USB82/162 achieves throughputs approaching 1 MIPS per MHz allowing the system designer ...
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... Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel AT90USB82/162 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The AT90USB82/162 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emula- tors, and evaluation kits ...
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Port C (PC7..PC0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C ...
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About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in ...
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AVR CPU Core 4.1 Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control ...
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The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation typ- ical ALU operation, two operands are output from the Register ...
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Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact ...
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General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: • One 8-bit output ...
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Y-register Z-register In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 4.6 Stack Pointer The Stack is mainly used for storing temporary data, for ...
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Figure 4-4. 1st Instruction Execute 2nd Instruction Execute 3rd Instruction Execute Figure 4-5 operation using two register operands is executed, and the result is stored back to the destina- tion register. Figure 4-5. Register Operands Fetch ALU Operation Execute 4.8 ...
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There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vec- tor in order to execute the interrupt ...
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Assembly Code Example sei sleep; enter sleep, waiting for interrupt ; note: will enter sleep before any pending ; interrupt(s) C Code Example __enable_interrupt(); /* set Global Interrupt Enable */ __sleep(); /* enter sleep, waiting for interrupt */ /* note: ...
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AVR AT90USB82/162 Memories This section describes the different memories in the AT90USB82/162. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the AT90USB82/162 features an EEPROM Memory for data storage. ...
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Figure 5-1. 5.2 SRAM Data Memory Figure 5-2 The AT90USB82/162 is a complex microcontroller with more peripheral units than can be sup- ported within the 64 location reserved in the Opcode for the IN and OUT instructions. For the Extended ...
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The 32 general purpose working registers, 64 I/O registers, and the 512 bytes of internal data SRAM in the AT90USB82/162 are all accessible through all these addressing modes. The Reg- ister File is described in Figure 5-2. 5.2.1 Data Memory ...
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For a detailed description of SPI, debugWIRE and Parallel data downloading to the EEPROM, see page 5.3.1 EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space. The write access time for the EEPROM is given in ...
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The EEPROM Control Register – EECR Bit Read/Write Initial Value • Bits 7..6 – Res: Reserved Bits These bits are reserved bits in the AT90USB82/162 and will always read as zero. • Bits 5, 4 – EEPM1 and EEPM0: ...
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Write new EEPROM data to EEDR (optional). 5. Write a logical one to the EEMPE bit while writing a zero to EEPE in EECR. 6. Within four clock cycles after setting EEMPE, write a logical one to EEPE. The ...
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Flash Boot Loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish. Assembly Code Example EEPROM_write: ; Wait for completion of previous ...
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The next code examples show assembly and C functions for reading the EEPROM. The exam- ples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. Assembly Code Example EEPROM_read: C Code Example unsigned ...
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If a reset occurs while a write operation is in progress, the write operation will be com- pleted provided that the power supply voltage is sufficient. 5.4 I/O Memory The I/O space definition of the AT90USB82/162 is shown ...
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System Clock and Clock Options 6.1 Clock Systems and their Distribution Figure 6-1 need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using ...
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USB Clock – clk USB The USB is provided with a dedicated clock domain. This clock is generated with an on-chip PLL running at 48MHz. The PLL always multiply its input frequency by 6. Thus the PLL clock register ...
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Figure 6-3. USB non-Idle CPU Clock External Oscillator RC oscillator 6.2.2 Clock switch Algorythm 6.2.2.1 Swith from external clock to RC clock if (Usb_suspend_detected()) { } 6.2.2.2 Switch from RC clock to external clock if (Usb_wake_up_detected()) { } 6.2.3 Clock ...
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Bit 7-6 – RCSUT[1:0]: SUT for RC oscillator These 2 bits are the SUT value for the RC Oscillator. If the RC oscillator is selected by fuse bits, the SUT fuse are copied into these bits. A firmware change ...
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Clock Status Register – CLKSTA Bit Read/Write Initial Value • Bit 7-2 - Reserved bits These bits are reserved and will always read as zero. • Bit 1 – RCON: RC Oscillator On This bit is set by hardware ...
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Table 6-2. Typ Time-out (V Main purpose of the delay is to keep the AVR in reset until it is supplied with minimum Vcc. The delay will not monitor the actual voltage and it will ...
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Figure 6-4. The Low Power Oscillator can operate in three different modes, each optimized for a specific fre- quency range. The operating mode is selected by the fuses CKSEL3..1 as shown in Table 6-3. Frequency Range Notes: The CLKSEL0 Fuse ...
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Table 6-4. Oscillator Source / Power Conditions Crystal Oscillator, BOD enabled Crystal Oscillator, fast rising power Crystal Oscillator, slowly rising power Notes: Table 6-5. Power Conditions BOD enabled Fast rising power Slowly rising power Note: 6.5 Calibrated Internal RC Oscillator ...
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When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in Table 6-5 on page Table 6-7. Power Conditions BOD enabled Fast rising power Slowly rising power Note: 6.5.1 Oscillator Calibration Register – OSCCAL Bit ...
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External Clock The device can utilize a external clock source as shown in external clock, the CKSEL Fuses must be programmed as shown in Figure 6-5. When this clock source is selected, start-up times are determined by the SUT ...
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This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals. clk ...
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This feature should be used if the selected clock source has a higher frequency than the maximum frequency of the device at the present operat- ing conditions. Note that any ...
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Figure 6-6. 6.9.2 PLL Control and Status Register – PLLCSR Bit $29 ($29) Read/Write Initial Value • Bit 7..5 – Res: Reserved Bits These bits are reserved bits in the AT90USB82/162 and always read as zero. • Bit 4..2 – ...
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Bit 0 – PLOCK: PLL Lock Detector When the PLOCK bit is set, the PLL is locked to the reference clock, and it is safe to enable PCK for Timer/Counter1. After the PLL is enabled, it takes about 1ms ...
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Power Distribution The AT90USB82/162 product includes an internal 5V to 3.3V regulator that allows to supply the USB pad (see Figure 7-1.) and, depending on the applica- tion, external components or even the microcontroller itself (see Figure 7-2.). Figure ...
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Figure 7-3. UVCC UCAP PS/2 Pad 3.3V Reg USB Pad UVSS Important note: In the 3.3V configuration, the internal regulator is bypassed. The regulator has to be disabled to avoid extra power consumption. 7.0.1 Regulator Control Register – REGCR Bit ...
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Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consump- tion to the application’s ...
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Sleep Enable (SE) bit to one just before the execution of the SLEEP instruction and to clear it immediately after waking up. 8.1 Idle Mode When the SM2..0 bits are written to 000, ...
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Mode is equivalent to Standy Mode, but is also conserved for compatibility purpose. From Extended Standby mode, the device wakes up in six clock cycle. Table 8-2. Sleep Mode Idle Power-down Power-save Standby Extended Standby Notes: Notes: Notes: 8.6 Power ...
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Bit 4 - Res: Reserved bit This bit is reserved and will always read as zero. • Bit 3 - PRTIM1: Power Reduction Timer/Counter1 Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1 ...
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Refer to configure the Analog Comparator. 8.7.2 Brown-out Detector If the Brown-out Detector is not needed by the application, this module should be turned off. If the Brown-out Detector is enabled by the BODLEVEL Fuses, it ...
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System Control and Reset 9.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP ...
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Figure 9-1. BODLEVEL [2..0] Table 9-1. Symbol V POT V POR V CCRR V RST t RST Notes: 9.3 Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in POR ...
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RESET after V when V CC Figure 9-2. TIME-OUT INTERNAL Figure 9-3. TIME-OUT INTERNAL 9.4 External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum ...
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Brown-out Detection AT90USB82/162 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V during operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger ...
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Figure 9-5. 9.6 Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period t page 52 ...
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Figure 9-7. 9.7.1 MCU Status Register –MCUSR The MCU Status Register provides information on which reset source caused an MCU reset. Bit Read/Write Initial Value • Bit 7-6 – Res: Reserved Bit These bits are reserved and will always read ...
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Internal Voltage Reference AT90USB82/162 features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator. 9.8.1 Voltage Reference Enable Signals and Start-up Time The voltage reference ...
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Selectable Time-out period from 16ms to 8s • Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode • Early warning after one Time-Out period reached, programmable Reset (see operating modes) after 2 Time-Out periods reached. Figure 9-8. The ...
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In the same operation, write a logic one to the Watchdog change enable bits WDCE and WDE. A logic one must be written to WDE regardless of the previous value of the WDE bit and even if it will ...
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The following code example shows one assembly and one C function for turning off the Watch- dog Timer. The example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during the execution of ...
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The following code example shows one assembly and one C function for changing the time-out value of the Watchdog Timer. Assembly Code Example WDT_Prescaler_Change: ; Turn off global interrupt cli ; Reset Watchdog Timer wdr ; Start timed sequence in ...
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Alternatively, WDIF is cleared by writing a logic one to the flag. When the I-bit in SREG and WDIE are set, the Watchdog Time-out Interrupt is executed. • Bit 6 - WDIE: Watchdog Interrupt Enable When ...
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Bit 7-4 - Reserved bits These bits are reserved and will always read as zero. • Bit 3 - WDEWIF: Watchdog Early Warning Interrupt Flag This bit is set when a first time-out occurs in the Watchdog Timer and ...
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Table 9-6. WDP3 WDP2 WDP1 WDP0 ...
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Table 9-7. WDP3 WDP2 WDP1 WDP0 ...
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Table 9-8. WDP3 WDP2 WDP1 WDP0 ...
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Table 9-9. WDP3 WDP2 WDP1 WDP0 ...
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Interrupts This section describes the specifics of the interrupt handling as performed in AT90USB82/162. For a general explanation of the AVR interrupt handling, refer to on page 10.1 Interrupt Vectors in AT90USB82/162 Table 10-1. Vector No ...
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Table 10-1. Vector No Notes: Table 10-2 BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is ...
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Table 10-2. BOOTRST Note: 10.1.1 Moving Interrupts Between Application and Boot Space The General Interrupt Control Register controls the placement of the Interrupt Vector table. 10.1.2 MCU Control Register – MCUCR Bit Read/Write Initial Value • Bit 1 – IVSEL: ...
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The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as ...
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I/O-Ports 11.1 Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with ...
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Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. 11.2 Ports as General Digital I/O The ports are bi-directional I/O ports ...
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If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin ...
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Figure 11-3. Synchronization when Reading an Externally Applied Pin value INSTRUCTIONS Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the ...
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Assembly Code Example C Code Example unsigned char i; Note: 11.2.5 Digital Input Enable and Sleep Modes As shown in schmitt-trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-down mode, Power-save mode, ...
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Unconnected Pins If some pins are unused recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, float- ing inputs ...
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Note: Table 11-2 ure 11-5 in the modules having the alternate function. Table 11-2. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO The following subsections shortly describe the alternate functions for each port, and relate ...
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Read/Write Initial Value • Bit 4 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} ...
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PDO, SPI Serial Programming Data Output. During Serial Program Downloading, this pin is used as data output line for the AT90USB82/162. MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI is enabled as a master, ...
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MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT.. Table 11-4. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Table 11-5. Signal Name PUOE PUOV DDOE DDOV ...
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Table 11-6. The alternate pin configuration is as follows: • ICP1/INT4/CLK0, Bit 7 ICP1, Input Capture pin 1 :The PC7 pin can act as an input capture for Timer/Counter1. INT4, External Interrupt source 4 : The PC7 pin can serve ...
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When the debugWIRE Enable (DWEN) Fuse is programmed and Lock bits are unprogrammed, the debugWIRE system within the target device is activated. The RESET port pin is configured as a wired -AND (open-drain) bi-directional I/O pin with ...
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Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 11-9. Port Pin PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 The alternate pin configuration is as follows: • HWB/TO/INT7/CTS HWB, Hardware Boot ...
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TXD1, USART1 Transmit Data : When the USART1 Transmitter is enabled, this pin is config- ured as an ouput regardless of DDRD3. • INT2/AIN1/RXD1 INT2, External Interrupt source 2: The PD2 pin can serve as an external interrupt source to ...
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Table 11-10. Overriding Signals for Alternate Functions PD7..PD4 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Table 11-11. Overriding Signals for Alternate Functions in PD3..PD0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI ...
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Register Description for I/O-Ports 11.4.1 Port B Data Register – PORTB Bit Read/Write Initial Value 11.4.2 Port B Data Direction Register – DDRB Bit Read/Write Initial Value 11.4.3 Port B Input Pins Address – PINB Bit Read/Write Initial Value ...
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Port D Input Pins Address – PIND Bit Read/Write Initial Value 7707F–AVR–11/ PIND7 PIND6 PIND5 PIND4 R/W R/W R/W R/W N/A N/A N/A N/A AT90USB82/162 PIND3 PIND2 PIND1 PIND0 R/W R/W ...
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External Interrupts The External Interrupts are triggered by the INT7:0 pin or any of the PCINT12..0 pins. Observe that, if enabled, the interrupts will trigger even if the INT7:0 or PCINT12..0 pins are configured as outputs. This feature provides ...
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Table 12-1. ISCn1 Note: Table 12-2. Symbol t INT 12.0.2 External Interrupt Control Register B – EICRB Bit Read/Write Initial Value • Bits 7..0 – ISC71, ISC70 - ISC41, ISC40: External Interrupt Sense ...
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External Interrupt Mask Register – EIMSK Bit Read/Write Initial Value • Bits 7..0 – INT7 – INT0: External Interrupt Request Enable When an INT7 – INT0 bit is written to one and the I-bit in the ...
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When a logic change on any PCINT12..8/7..0 pin triggers an interrupt request, PCIF1/0 becomes set (one). If the I-bit in SREG and the PCIE1/0 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The ...
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Timer/Counter0 and Timer/Counter1 Prescalers Timer/Counter0 and 1 share the same prescaler module, but the Timer/Counters can have dif- ferent prescaler settings. The description below applies to all Timer/Counters used as a general name ...
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Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the sys- tem clock frequency (f sampling, the maximum ...
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Timer/Counter0 with PWM Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output Compare Units, and with PWM support. It allows accurate program execution timing (event man- agement) and wave generation. The main features are: • ...
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The double buffered Output Compare Registers (OCR0A and OCR0B) are compared with the Timer/Counter value at all times. The result of the compare can be used by the Waveform Gen- erator to generate a PWM or variable frequency output on ...
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Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02 the ...
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Figure 14-3. Output Compare Unit, Block Diagram The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the dou- ble buffering is ...
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Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is down-counting. The setup of the OC0x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of ...
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Compare Output Mode and Waveform Generation The Waveform Generator uses the COM0x1:0 bits differently in Normal, CTC, and PWM modes. For all modes, setting the COM0x1 tells the Waveform Generator that no action on the OC0x Register ...
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Figure 14-5. CTC Mode, Timing Diagram TCNTn OCn (Toggle) Period An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be ...
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PWM mode is shown in togram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent Com- pare Matches between OCR0x and TCNT0. Figure 14-6. Fast PWM ...
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OC0A toggle in CTC mode, except the double buffer feature of the Out- put Compare unit is enabled in the fast PWM mode. 14.6.4 Phase Correct PWM Mode The phase correct PWM mode (WGM02:0 = ...
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OC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is not available for the OC0B pin (See be visible on the port pin if the data direction for the port pin ...
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Figure 14-9. Timer/Counter Timing Diagram, with Prescaler (f clk clk (clk I/O TCNTn TOVn Figure 14-10 mode and PWM mode, where OCR0A is TOP. Figure 14-10. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (f clk clk (clk I/O TCNTn ...
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Initial Value • Bits 7:6 – COM01A:0: Compare Match Output A Mode These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0 bits are set, the OC0A output overrides the normal port functionality of ...
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Note: • Bits 5:4 – COM0B1:0: Compare Match Output B Mode These bits control the Output Compare pin (OC0B) behavior. If one or both of the COM0B1:0 bits are set, the OC0B output overrides the normal port functionality of the ...
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Note: • Bits 3, 2 – Res: Reserved Bits These bits are reserved bits in the AT90USB82/162 and will always read as zero. • Bits 1:0 – WGM01:0: Waveform Generation Mode Combined with the WGM02 bit found in the TCCR0B ...
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A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0A as TOP. The FOC0A bit is always read as zero. • Bit 6 – FOC0B: Force Output Compare B The FOC0B ...
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The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes) the Compare Match on the following timer clock. Modifying the counter (TCNT0) while the counter ...
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Timer/Counter 0 Interrupt Flag Register – TIFR0 Bit Read/Write Initial Value • Bits 7..3 – Res: Reserved Bits These bits are reserved bits in the AT90USB82/162 and will always read as zero. • Bit 2 – OCF0B: Timer/Counter 0 ...
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Timer/Counter 1 with PWM The 16-bit Timer/Counter 1 unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. The main features are: • True 16-bit Design (i.e., Allows 16-bit PWM) • Three independent Output ...
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Figure 15-1. 16-bit Timer/Counter Block Diagram Note: 15.1.1 Registers The Timer/Counter (TCNTn), Output Compare Registers (OCRnA/B/C), and Input Capture Reg- ister (ICRn) are all 16-bit registers. Special procedures must be followed when accessing the 16- bit registers. These procedures are ...
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See “Output Compare Units” on page Match Flag (OCFnA/B/C) which can be used to generate an Output Compare interrupt request. The Input Capture Register can capture the Timer/Counter value at a given external (edge trig- gered) event on either the ...
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Assembly Code Examples ... ; Set TCNTn to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNTnH,r17 out TCNTnL,r16 ; Read TCNTn into r17:r16 in r16,TCNTnL in r17,TCNTnH ... C Code Examples unsigned int i; ... /* Set TCNTn to 0x01FF */ ...
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Assembly Code Example TIM16_ReadTCNTn: C Code Example unsigned int TIM16_ReadTCNTn( void ) { } Note: The assembly code example returns the TCNTn value in the r17:r16 register pair. 7707F–AVR–11/10 (1) ; Save global interrupt flag in r18,SREG ; Disable interrupts ...
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The following code examples show how atomic write of the TCNTn Register contents. Writing any of the OCRnA/B/C or ICRn Registers can be done by using the same principle. Assembly Code Example TIM16_WriteTCNTn: ; Save global interrupt ...
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Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 15-2 Figure 15-2. Counter Unit Block Diagram Signal description (internal signals): Count Direction Clear clk TOP BOTTOM The 16-bit counter is mapped ...
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The Timer/Counter Overflow Flag (TOVn) is set according to the mode of operation selected by the WGMn3:0 bits. TOVn can be used for generating a CPU interrupt. 15.5 Input Capture Unit The Timer/Counter incorporates an input capture unit that can ...
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Reading the 16-bit value in the Input Capture Register (ICRn) is done by first reading the low byte (ICRnL) and then the high byte (ICRnH). When the low byte is read the high byte is copied into the high byte ...
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Using the Input Capture unit in any mode of operation when the TOP value (resolution) is actively changed during operation, is not recommended. Measurement of an external signal’s duty cycle requires that the trigger edge is changed after each capture. ...
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The OCRnx Register is double buffered when using any of the twelve Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update ...
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Compare Match Output Unit The Compare Output mode (COMnx1:0) bits have two functions. The Waveform Generator uses the COMnx1:0 bits for defining the Output Compare (OCnx) state at the next compare match. Secondly the COMnx1:0 bits control the OCnx ...
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PWM refer to page 130. A change of the COMnx1:0 bits state will have effect at the first compare match after the bits are written. ...
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Figure 15-6. CTC Mode, Timing Diagram TCNTn OCnA (Toggle) Period An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCFnA or ICFn Flag according to the register used to define ...
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The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and the max- imum resolution is 16-bit ...
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When the OCRnA I/O location is written the value written will be put into the OCRnA Buffer Register. The OCRnA Compare Register will then be updated with the value in the Buffer Register at the next ...
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OCRnA set to MAX). The PWM resolu- tion in bits can be calculated by using the following equation: In phase correct PWM mode the counter is incremented until the counter value ...
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Since the OCRnx update occurs at TOP, the PWM period starts and ends at TOP. This implies that the length of the falling slope is determined by the previous TOP value, while the length of the rising slope is ...
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OCRnA set to MAX). The PWM resolution in bits can be calculated using the following equation: In phase and frequency correct PWM mode the counter is incremented until the counter value matches either ...
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Using the ICRn Register for defining TOP works well when using fixed TOP values. By using ICRn, the OCRnA Register is free to be used for generating a PWM output on OCnA. However, if the base PWM frequency is actively ...
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Figure 15-11. Timer/Counter Timing Diagram, Setting of OCFnx, with Prescaler (f Figure 15-12 frequency correct PWM mode the OCRnx Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by ...
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Figure 15-13. Timer/Counter Timing Diagram, with Prescaler (f clk clk (clk TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOVn and ICF n as TOP) OCRnx (Update at TOP) 15.10 16-bit Timer/Counter Register Description 15.10.1 Timer/Counter1 Control Register A ...
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Table 15-1. COMnA1/COMnB1/ Table 15-2 PWM mode. Table 15-2. COMnA1/COMnB1/ Note: Table 15-3 correct and frequency correct PWM mode. 7707F–AVR–11/10 Compare Output Mode, non-PWM COMnA0/COMnB0/ COMnC1 COMnC0 shows the COMnx1:0 bit ...
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Table 15-3. COMnA1/COMnB/ Note: • Bit 1:0 – WGMn1:0: Waveform Generation Mode Combined with the WGMn3:2 bits found in the TCCRnB Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what ...
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Table 15- Note: 1. The CTCn and PWMn1:0 bit definition names are obsolete. Use the location of these bits are compatible with ...
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Timer/Counter1 Control Register B – TCCR1B Bit Read/Write Initial Value • Bit 7 – ICNCn: Input Capture Noise Canceler Setting this bit (to one) activates the Input Capture Noise Canceler. When the Noise Canceler is activated, the input from ...
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If external pin modes are used for the Timer/Countern, transitions on the Tn pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. 15.10.3 Timer/Counter1 Control Register C ...
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Output Compare Register 1 A – OCR1AH and OCR1AL Bit Read/Write Initial Value 15.10.6 Output Compare Register 1 B – OCR1BH and OCR1BL Bit Read/Write Initial Value 15.10.7 Output Compare Register 1 C – OCR1CH and OCR1CL Bit Read/Write ...
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When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Countern Input Capture interrupt is enabled. The corresponding Interrupt Vector Bit 3 – OCIEnC: Timer/Countern, Output Compare C Match Interrupt ...
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This flag is set in the timer clock cycle after the counter (TCNTn) value matches the Output Compare Register B (OCRnB). Note that a Forced Output Compare (FOCnB) strobe will not set the OCFnB Flag. OCFnB is automatically cleared when ...
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Serial Peripheral Interface – SPI The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ...
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Slave prepare the data to be sent in their respective shift Registers, and the Master generates the required clock pulses on the SCK line to interchange data. Data is always shifted from Mas- ter to Slave on the Master Out ...
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When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Functions” on page Table 16-1. Pin MOSI MISO SCK SS Note: The following code examples show how to initialize the ...
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Assembly Code Example SPI_MasterInit: ; Set MOSI and SCK output, all others input ldi out ; Enable SPI, Master, set clock rate fck/16 ldi out ret SPI_MasterTransmit: ; Start transmission of data (r16) out Wait_Transmit: ; Wait for transmission complete ...
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The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception. Assembly Code Example SPI_SlaveInit: SPI_SlaveReceive: C Code Example void SPI_SlaveInit(void char SPI_SlaveReceive(void Note: 16.1 SS Pin ...
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Note that the SPI logic will be reset once the SS pin is driven high. The SS pin is useful for packet/byte synchronization to keep the slave bit counter synchronous with the ...
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SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Mas- ter mode. • Bit 3 – CPOL: Clock Polarity When this bit is written to one, SCK is high when idle. ...
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When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if SPIE in SPCR is set and global interrupts are enabled input and is driven low when the SPI is in ...
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Table 16-5. CPOL=0, CPHA=0 CPOL=0, CPHA=1 CPOL=1, CPHA=0 CPOL=1, CPHA=1 Figure 16-3. SPI Transfer Format with CPHA = 0 Figure 16-4. SPI Transfer Format with CPHA = 1 7707F–AVR–11/10 CPOL Functionality Leading Edge Sample (Rising) Setup (Rising) Sample (Falling) Setup ...
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USART The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART highly flexible serial communication device. The main features are: • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Flow ...
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Figure 17-1. USART Block Diagram Note: The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): Clock Generator, Transmitter and Receiver. Control Registers are shared by all units. The Clock Generation ...
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XCKn pin (DDR_XCKn) controls whether the clock source is internal (Master mode) or external (Slave mode). The XCKn pin is only active when using synchronous mode. Figure 17-2 Figure 17-2. Clock Generation Logic, Block Diagram DDR_XCK Signal description: ...
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Table 17-1 ing the UBRRn value for each mode of operation using an internally generated clock source. Table 17-1. Equations for Calculating Baud Rate Register Setting Operating Mode Asynchronous Normal mode (U2Xn = 0) Asynchronous Double Speed mode (U2Xn = ...
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External Clock External clocking is used by the synchronous slave modes of operation. The description in this section refers to External clock input from the XCKn pin is sampled by a synchronization register to minimize the chance of meta-stability. ...
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A frame starts with the start bit followed by the least significant data bit. Then the next data bits total of nine, are succeeding, ending with the most significant bit. If enabled, the parity bit is inserted ...
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USART Initialization The USART has to be initialized before any communication can take place. The initialization pro- cess normally consists of setting the baud rate, setting frame format and enabling the Transmitter or the Receiver depending on the usage. ...
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Data Transmission – The USART Transmitter The USART Transmitter is enabled by setting the Transmit Enable (TXEN) bit in the UCSRnB Register. When the Transmitter is enabled, the normal port operation of the TxDn pin is overrid- den by ...
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For the assembly code, the data to be sent is assumed to be stored in registers R17:R16. Assembly Code Example USART_Transmit: ; Wait for empty transmit buffer sbis UCSRnA,UDREn rjmp USART_Transmit ; ...
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UDRn in order to clear UDREn or disable the Data Register Empty interrupt, otherwise a new interrupt will occur once the interrupt routine terminates. The Transmit Complete (TXCn) Flag bit is set one when the entire frame in the Transmit ...
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UDRn will be masked to zero. The USART has to be initialized before the function can be used. Assembly Code Example USART_Receive: ; Wait for data to be received sbis UCSRnA, RXCn rjmp ...
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Assembly Code Example USART_Receive: USART_ReceiveNoError: C Code Example unsigned int USART_Receive( void ) { } Note: The receive function example reads all the I/O Registers into the Register File before any com- putation is done. This gives an optimal receive ...
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Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXCn) Flag indicates if there are unread data present in the receive buf- fer. This flag is one when unread ...
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The UPEn bit is set if the next character that can be read from the receive buffer had a Parity Error when received and the Parity Checking was enabled at that point (UPMn1 = 1). This bit is valid until ...
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Figure 17-5. Start Bit Sampling Sample (U2X = 0) Sample (U2X = 1) When the clock recovery logic detects a high (idle) to low (start) transition on the RxDn line, the start bit detection sequence is initiated. Let sample 1 ...
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Figure 17-7. Stop Bit Sampling and Next Start Bit Sampling The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop bit is registered to have a logic 0 ...
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Table 17-2. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2Xn = (Data+Parity Bit) R slow 5 93.20 6 94.12 7 94.81 8 95.36 9 95.81 10 96.17 Table 17-3. Recommended Maximum Receiver Baud Rate ...
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The Multi-processor Communication mode enables several slave MCUs to receive data from a master MCU. This is done by first decoding an address frame to find out which MCU has been addressed particular slave MCU has been addressed, ...
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RTS usage and so associated flow control is enabled using RTSEN bit in UCSRnD. Figure 17-8. shows a reception example. Figure 17-8. Reception Flow Control Waveform Example Figure 17-9. RTS behavior RTS will rise at 2/3 of ...
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USART Register Description 17.10.1 USART I/O Data Register n– UDRn Bit Read/Write Initial Value The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address referred to as USART Data Register or UDRn. ...
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Bit 4 – FEn: Frame Error This bit is set if the next character in the receive buffer had a Frame Error when received. I.e., when the first stop bit of the next character in the receive buffer is ...
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Bit 4 – RXENn: Receiver Enable n Writing this bit to one enables the USART Receiver. The Receiver will override normal port oper- ation for the RxDn pin when enabled. Disabling the Receiver will flush the receive buffer invalidating ...
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Receiver will generate a parity value for the incoming data and compare it to the UPMn setting mismatch is detected, the UPEn Flag in UCSRnA will be set. Table 17-5. UPMn Bits Settings UPMn1 ...
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USART Control and Status Register n D – UCSRnD Bit Read/Write Initial Value • Bits 1 – CTSEN : USART CTS Enable Set this bit to one by firmware to enable the transmission flow control (CTS). Transmission is allowed ...
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Table 17-9. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies f = 1.0000 MHz osc Baud U2Xn = 0 U2Xn = 1 Rate (bps) UBRR Error UBRR 2400 25 0.2% 51 4800 12 0.2% 25 9600 6 -7.0% 12 ...
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Table 17-10. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued 3.6864 MHz osc Baud U2Xn = 0 U2Xn = 1 Rate (bps) UBRR Error UBRR 2400 95 0.0% 191 4800 47 0.0% 95 9600 23 0.0% ...
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Table 17-11. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued 8.0000 MHz osc Baud U2Xn = 0 U2Xn = 1 Rate (bps) UBRR Error UBRR 2400 207 0.2% 416 4800 103 0.2% 207 9600 51 0.2% ...
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Table 17-12. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued 16.0000 MHz osc Baud U2Xn = 0 U2Xn = 1 Rate (bps) UBRR Error UBRR 2400 416 -0.1% 832 4800 207 0.2% 416 9600 103 0.2% ...
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The USART RX and TX control logic is replaced by a common SPI transfer control logic. However, the pin control logic and interrupt generation logic is identical in both modes of operation. The I/O register locations ...
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SPI Data Modes and Timing There are four combinations of XCKn (SCK) phase and polarity with respect to serial data, which are determined by control bits UCPHAn and UCPOLn. The data transfer timing diagrams are shown in signal, ensuring ...
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USART MSPIM Initialization The USART in MSPIM mode has to be initialized before any communication can take place. The initialization process normally consists of setting the baud rate, setting master mode of operation (by setting DDR_XCKn to one), setting ...
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Assembly Code Example USART_Init: C Code Example void USART_Init( unsigned int baud ) { } Note: 18.5 Data Transfer Using the USART in MSPI mode requires the Transmitter to be enabled, i.e. the TXENn bit in the UCSRnB register is ...
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The data written to UDRn is moved from the transmit buf- fer to the shift register when the shift register is ready to send a new frame. Note: The following code examples show a simple ...
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Transmitter and Receiver Flags and Interrupts The RXCn, TXCn, and UDREn flags and corresponding interrupts in USART in MSPIM mode are identical in function to the normal USART operation. However, the receiver error status flags (FE, DOR, and PE) ...
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USART MSPIM Control and Status Register UCSRnB Bit Read/Write Initial Value • Bit 7 - RXCIEn: RX Complete Interrupt Enable Writing this bit to one enables interrupt on the RXCn Flag. A USART Receive Complete interrupt ...
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USART MSPIM Control and Status Register UCSRnC Bit Read/Write Initial Value • Bit 7:6 - UMSELn1:0: USART Mode Select These bits select the mode of operation of the USART as shown in Control and Status Register ...
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The UCPHAn bit functionality is identical to the SPI CPHA bit. • The UDORDn bit functionality is identical to the SPI DORD bit. However, since the USART in MSPIM mode reuses the USART resources, the use of the USART ...
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USB controller 19.1 Features • Support full-speed • Support ping-pong mode (dual bank), with transparent switch • 176 bytes of DPRAM – 1 endpoint of 64 bytes max, (default control endpoint) – 2 endpoints of 64 bytes max, (one ...
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Figure 19-1. USB controller Block Diagram overview 19.3 Typical Application Implementation Depending on the target application power supply, the AT90USB82/162 requires different hard- ware typical implementations. Figure 19-2. Operating modes versus frequency and power-supply AT90USB82/162 184 UVCC Regulator UCAP clk ...
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Bus Powered device Figure 19-3. Typical Bus powered application with 5V I/O VBUS UDP UDM UVSS Figure 19-4. Typical Bus powered application with 3V I/O VBUS UDM UDP UVSS 7707F–AVR–11/10 VCC UCAP 1µF UVCC D+ D- UVSS VSS XTAL1 ...
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Self Powered device Figure 19-5. Typical Self powered application with 3.4V to 5.5V I/O UDP UDM UVSS Figure 19-6. Typical Self powered application with 3.0V to 3.6 I/O UDP UDM UVSS AT90USB82/162 186 UVCC AVCC UCAP 1µF D+ Rs=22 ...
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Design guidelines • Serial resistors on USB Data lines must have 22 Ohms value ( • Traces from the input USB receptable (or from the cable connection in the case of a tethered device) to the USB microcontroller pads ...
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USB controller clock is stopped in order to minimize the power consumption (FRZCLK=1), • the USB controller is disabled, • USB is in the suspend mode, • the Device USB controllers internal state is reset. • The DPACC ...
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Each of these interupts are time-relative events that will be detected only if the USB clock is enabled (FRZCLK bit cleared), except for the WAKEUP interrupt that will trigger each time a state change is detected on the data lines. ...
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Power modes 19.5.1 Idle mode In this mode, the CPU core is halted (CPU clock stopped). The Idle mode is taken wether the USB controller is running or not. The CPU can wake up on any USB interrupts. 19.5.2 ...
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Table 19-1. Free memory EPEN=1 ALLOC=1 Endpoints activation • First, Endpoint 0 to Endpoint 4 are configured, in the growing order. The memory of each is reserved in the DPRAM. • Then, the Endpoint 2is ...
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Figure 19-11. Pad behaviour The SUSPI flag indicated that a suspend state has been detected on the USB bus. This flag automatically put the USB pad in Idle. The detection of a non-idle event sets the WAKEUPI flag and wakes-up ...
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Registers description 19.9.1 USB general registers Bit Read/Writ e Initial Val- ue • 7 – USBE: USB macro Enable Bit Set to enable the USB controller. Clear to disable and reset the USB controller, to disable the USB transceiver ...
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DPADD7:0: DPRAM Address Low Bit DAPDD7:0 is the least significant part of DPADD. 19.9.2 USB/PS2 Software Output Enable register – UPOE Bit Read/Write Initial Value • Bit 7:6 – UPOE[1:0]: USB/PS2 Output enable Set these bits with ...
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Enable USB interface • Configure USB interface (USB Endpoint 0 configuration) • Attach USB device Power Off the USB interface • Detach USB device • Disable USB interface • Disable PLL Suspending the USB interface • Clear Suspend Bit ...
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USB Device Operating modes 20.1 Introduction The USB device controller supports full speed data transfers. In addition to the default control endpoint, it provides four other endpoints, which can be configured in control, bulk, interrupt or isochronous modes: • ...
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UEINTX, UESTA0X and UESTA1X are restored to their reset value. The data toggle field remains unchanged. The other registers remain unchanged. The endpoint configuration remains active and the endpoint is still enabled. The endpoint reset may be associated ...
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Figure 20-2. Endpoint activation flow: As long as the endpoint is not correctly configured (CFGOK cleared), the hardware does not acknowledge the packets sent by the host. CFGOK will not be set if the Endpoint size parameter is bigger than ...
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ADDEN is cleared by hardware: • after a power-up reset, • when an USB reset is received, • or when the macro is disabled (USBE cleared) When this bit is cleared, the default device address 00h is used. 20.8 Suspend, ...
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Remote Wake-up The “Remote Wake-up” (or “upstream resume”) request is the only operation allowed to be sent by the device on its own initiative. Anyway that, the device should first have received a DEVICE_REMOTE_WAKEUP request from the ...