ATMEGA88-20AUR Atmel, ATMEGA88-20AUR Datasheet - Page 244

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ATMEGA88-20AUR

Manufacturer Part Number
ATMEGA88-20AUR
Description
MCU AVR 8K FLASH 20MHZ 32TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet

Specifications of ATMEGA88-20AUR

Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

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Part Number:
ATMEGA88-20AUR
Manufacturer:
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10 000
244
ATmega48/88/168
Figure 23-1. Analog to Digital Converter Block Schematic Operation
The analog input channel is selected by writing to the MUX bits in ADMUX. Any of the ADC input
pins, as well as GND and a fixed bandgap voltage reference, can be selected as single ended
inputs to the ADC. The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Volt-
age reference and input channel selections will not go into effect until ADEN is set. The ADC
does not consume power when ADEN is cleared, so it is recommended to switch off the ADC
before entering power saving sleep modes.
The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and
ADCL. By default, the result is presented right adjusted, but can optionally be presented left
adjusted by setting the ADLAR bit in ADMUX.
If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read
ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the Data
Registers belongs to the same conversion. Once ADCL is read, ADC access to Data Registers
is blocked. This means that if ADCL has been read, and a conversion completes before ADCH is
AREF
ADC7
ADC6
ADC5
ADC4
ADC3
ADC2
ADC1
ADC0
AVCC
GND
INTERNAL 1.1V
REFERENCE
REFERENCE
BANDGAP
8-BIT DATA BUS
INPUT
MUX
ADC MULTIPLEXER
SELECT (ADMUX)
MUX DECODER
10-BIT DAC
ADC CTRL. & STATUS
REGISTER (ADCSRA)
ADC CONVERSION
COMPLETE IRQ
CONVERSION LOGIC
PRESCALER
SAMPLE & HOLD
COMPARATOR
15
+
-
ADC DATA REGISTER
(ADCH/ADCL)
ADC MULTIPLEXER
OUTPUT
2545S–AVR–07/10
0

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