ATMEGA88P-20MUR Atmel, ATMEGA88P-20MUR Datasheet - Page 41

• Manufacturer Part Number: ATMEGA88P-20MUR
• Description: MCU AVR 8KB FLASH 20MHZ 32QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA88P-20MUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.2
9.3
9.4
8025L–AVR–7/10
BOD Disable
Idle Mode
ADC Noise Reduction Mode
When the Brown-out Detector (BOD) is enabled by BODLEVEL fuses,
the BOD is actively monitoring the power supply voltage during a sleep period. To save power, it
is possible to disable the BOD by software for some of the sleep modes, see
40. The sleep mode power consumption will then be at the same level as when BOD is globally
disabled by fuses. If BOD is disabled in software, the BOD function is turned off immediately
after entering the sleep mode. Upon wake-up from sleep, BOD is automatically enabled again.
This ensures safe operation in case the V
When the BOD has been disabled, the wake-up time from sleep mode will be approximately 60
µs to ensure that the BOD is working correctly before the MCU continues executing code.
BOD disable is controlled by bit 6, BODS (BOD Sleep) in the control register MCUCR, see
”MCUCR – MCU Control Register” on page
vant sleep modes, while a zero in this bit keeps BOD active. Default setting keeps BOD active,
i.e. BODS set to zero.
Writing to the BODS bit is controlled by a timed sequence and an enable bit, see
MCU Control Register” on page
When the SM[2:0] bits are written to 000, the SLEEP instruction makes the MCU enter Idle
mode, stopping the CPU but allowing the SPI, USART, Analog Comparator, ADC, 2-wire Serial
Interface, Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep
mode basically halts clk
Idle mode enables the MCU to wake up from external triggered interrupts as well as internal
ones like the Timer Overflow and USART Transmit Complete interrupts. If wake-up from the
Analog Comparator interrupt is not required, the Analog Comparator can be powered down by
setting the ACD bit in the Analog Comparator Control and Status Register – ACSR. This will
reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automati-
cally when this mode is entered.
When the SM[2:0] bits are written to 001, the SLEEP instruction makes the MCU enter ADC
Noise Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, the 2-
wire Serial Interface address watch, Timer/Counter2
(if enabled). This sleep mode basically halts clk
clocks to run.
This improves the noise environment for the ADC, enabling higher resolution measurements. If
the ADC is enabled, a conversion starts automatically when this mode is entered. Apart from the
ADC Conversion Complete interrupt, only an External Reset, a Watchdog System Reset, a
Watchdog Interrupt, a Brown-out Reset, a 2-wire Serial Interface address match, a
Timer/Counter2 interrupt, an SPM/EEPROM ready interrupt, an external level interrupt on INT0
or INT1 or a pin change interrupt can wake up the MCU from ADC Noise Reduction mode.
Note:
1. Timer/Counter2 will only keep running in asynchronous mode, see
PWM and Asynchronous Operation” on page 142
CPU
and clk
45.
FLASH
, while allowing the other clocks to run.
CC
45. Writing this bit to one turns off the BOD in rele-
level has dropped during the sleep period.
I/O
, clk
(1)
ATmega48P/88P/168P
CPU
, and the Watchdog to continue operating
for details.
, and clk
FLASH
, while allowing the other
Table 27-6 on page
”8-bit Timer/Counter2 with
Table 9-1 on page
”MCUCR –
293,
41