ATMEGA8535-16MUR Atmel, ATMEGA8535-16MUR Datasheet
ATMEGA8535-16MUR
Specifications of ATMEGA8535-16MUR
Related parts for ATMEGA8535-16MUR
ATMEGA8535-16MUR Summary of contents
Page 1
... PDIP, 44-lead TQFP, 44-lead PLCC, and 44-pad QFN/MLF • Operating Voltages – 2.7 - 5.5V for ATmega8535L – 4.5 - 5.5V for ATmega8535 • Speed Grades – MHz for ATmega8535L – MHz for ATmega8535 ® 8-bit Microcontroller 8-bit Microcontroller with 8K Bytes In-System Programmable ...
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... Pin Configurations Disclaimer ATmega8535(L) 2 Figure 1. Pinout ATmega8535 (XCK/T0) PB0 (T1) PB1 (INT2/AIN0) PB2 (OC0/AIN1) PB3 (SS) PB4 (MOSI) PB5 (MISO) PB6 (SCK) PB7 (RXD) PD0 (TXD) PD1 (INT0) PD2 (INT1) PD3 (OC1B) PD4 (OC1A) PD5 (ICP1) PD6 (MOSI) PB5 1 33 PA4 (ADC4) (MISO) PB6 ...
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... Overview Block Diagram 2502K–AVR–10/06 The ATmega8535 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing instructions in a single clock cycle, the ATmega8535 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. ...
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... In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega8535 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega8535 AVR is supported with a full suite of program and system develop- ment tools including: C compilers, macro assemblers, program debugger/simulators, In- Circuit Emulators, and evaluation kits. ...
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... The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATmega8535 as listed on page 60. Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit) ...
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... Resources ATmega8535( comprehensive set of development tools, application notes and datasheets are avail- able for download on http://www.atmel.com/avr. 2502K–AVR–10/06 ...
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... These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit defini- tions in the header files and interrupt handling compiler dependent. Please confirm with the C Compiler documentation for more details. ATmega8535(L) 7 ...
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... AVR CPU Core Introduction Architectural Overview ATmega8535(L) 8 This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Figure 3. Block Diagram of the AVR MCU Architecture ...
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... The ALU operations are divided into three main categories – arithmetic, logical, and bit-func- tions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the “Instruc- tion Set” section for a detailed description. ATmega8535(L) 9 ...
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... Status Register ATmega8535(L) 10 The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will, in many cases, remove the need for using the dedicated compare instructions, resulting in faster and more compact code ...
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... Data Space. Although not being phys- ically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y-, and Z-pointer Registers can be set to index any register in the file. ATmega8535(L) 0 Addr. R0 ...
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... The X-register, Y-register, and Z-register Stack Pointer ATmega8535(L) 12 The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the Data Space. The three indirect address registers X, Y, and Z are defined as described in Figure 5. ...
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... INT0 – the External Interrupt Request 0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL bit in the General Interrupt Control Regis- ter (GICR). Refer to “Interrupts” on page 46 for more information. The Reset Vector can ATmega8535(L) , directly generated from the selected clock CPU ...
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... ATmega8535(L) 14 also be moved to the start of the Boot Flash section by programming the BOOTRST Fuse, see “Boot Loader Support – Read-While-Write Self-Programming” on page 224. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested inter- rupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – ...
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... This increase comes in addition to the start-up time from the selected sleep mode. A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. ATmega8535(L) 15 ...
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... Boot Program section and Application Program section. The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega8535 Program Counter (PC bits wide, thus addressing the 4K program memory locations. The operation of Boot Program section and associated Boot Lock bits for software protection are described in detail in “ ...
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... X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, and the 512 bytes of inter- nal data SRAM in the ATmega8535 are all accessible through all these addressing modes. The Register File is described in “General Purpose Register File” on page 11. ...
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... Data RD Memory Access Instruction The ATmega8535 contains 512 bytes of data EEPROM memory organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register. “ ...
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... X X • Bits 15..9 – Res: Reserved Bits These bits are reserved bits in the ATmega8535 and will always read as zero. • Bits 8..0 – EEAR8..0: EEPROM Address The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the 512 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 511 ...
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... ATmega8535(L) 20 value into the EEPROM. The EEMWE bit must be written to one before a logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential): 1. Wait until EEWE becomes zero. ...
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... EEPROM_write(unsigned int uiAddress, unsigned char ucData Wait for completion of previous write */ while(EECR & (1<<EEWE Set up Address and Data Registers */ EEAR = uiAddress; EEDR = ucData; /* Write logical one to EEMWE */ EECR |= (1<<EEMWE); /* Start eeprom write by setting EEWE */ EECR |= (1<<EEWE); } ATmega8535(L) 21 ...
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... EEPROM Write During Power- down Sleep Mode Preventing EEPROM Corruption ATmega8535(L) 22 The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. Assembly Code Example EEPROM_read: ...
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... The I/O space definition of the ATmega8535 is shown in page 299. All ATmega8535 I/Os and peripherals are placed in the I/O space. The I/O locations are accessed by the IN and OUT instructions, transferring data between the 32 general pur- pose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions ...
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... I/O Clock – clk I/O Flash Clock – clk FLASH ATmega8535(L) 24 Figure 11 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in “ ...
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... The Watchdog Oscillator is used for timing this real-time part of the start-up time. The number of WDT Oscillator cycles used for each time-out is shown in Table 3. The frequency of the Watchdog Oscil- lator is voltage dependent as shown in “ATmega8535 Typical Characteristics” on page 266. Table 3. Number of Watchdog Oscillator Cycles Typ Time-out ( ...
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... ATmega8535(L) 26 This mode has a limited frequency range and it can not be used to drive other clock buffers. For resonators, the maximum frequency is 8 MHz with CKOPT unprogrammed and 16 MHz with CKOPT programmed. C1 and C2 should always be equal for both crystals and resonators. The optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environ- ment ...
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... These options are intended for use with ceramic resonators and will ensure fre- quency stability at start-up. They can also be used with crystals when not operating close to the maximum frequency of the device, and if frequency stability at start-up is not important for the application. ATmega8535(L) Additional Delay from Reset ( ...
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... Low-frequency Crystal Oscillator External RC Oscillator ATmega8535( use a 32.768 kHz watch crystal as the clock source for the device, the Low-fre- quency Crystal Oscillator must be selected by setting the CKSEL Fuses to “1001”. The crystal should be connected as shown in Figure 12. By programming the CKOPT Fuse, the user can enable internal capacitors on XTAL1 and XTAL2, thereby removing the need for external capacitors ...
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... Note: 1. The device is shipped with this option selected. When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in Table 10. XTAL1 and XTAL2 should be left unconnected (NC). ATmega8535(L) Frequency Range (MHz) 0.1 - 0.9 0.9 - 3.0 3.0 - 8.0 8.0 - 12.0 ...
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... Oscillator Calibration Register – OSCCAL ATmega8535(L) 30 Table 10. Start-up Times for the Internal Calibrated RC Oscillator Clock Selection Start-up Time from Power- SUT1..0 down and Power-save ( Note: 1. The device is shipped with this option selected. Bit CAL7 CAL6 CAL5 Read/Write R/W R/W R/W Initial Value Device Specific Calibration Value • ...
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... For AVR microcontrollers with Timer/Counter Oscillator pins (TOSC1 and TOSC2), the crystal is connected directly between the pins. No external capacitors are needed. The Oscillator is optimized for use with a 32.768 kHz watch crystal. Applying an external clock source to TOSC1 is not recommended. ATmega8535(L) Additional Delay from Reset (V = 5.0V) ...
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... If a Reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector. Figure 11 on page 24 presents the different clock systems in the ATmega8535, and their distribution. The figure is helpful in selecting an appropriate sleep mode. The MCU Control Register contains control bits for power management. ...
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... Timer/Counter2 interrupt enable bits are set in TIMSK, and the Global Interrupt Enable bit in SREG is set. If the asynchronous timer is NOT clocked asynchronously, Power-down mode is recom- mended instead of Power-save mode because the contents of the registers in the ATmega8535(L) and clk , while allowing the other CPU ...
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... External Crystal or resonator selected as clock source bit in ASSR is set 3. Only INT2 or level interrupt INT1 and INT0 ATmega8535(L) 34 asynchronous timer should be considered undefined after wake-up in Power-save mode if AS2 is 0. This sleep mode basically halts all clocks except clk chronous modules, including Timer/Counter2 if clocked asynchronously. ...
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... Enable and Sleep Modes” on page 55 for details on which pins are enabled. If the input buffer is enabled and the input signal is left floating or have an analog signal level close to V /2, the input buffer will use excessive power. CC ATmega8535(L) ) and the ADC clock (clk ) are stopped, the I/O ADC ...
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... The time-out period of the delay counter is defined by the user through the CKSEL Fuses. The different selections for the delay period are presented in “Clock Sources” on page 25. The ATmega8535 has four sources of Reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V ) ...
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... Brown-out Detection BOD Brown-out Detector V HYST hysteresis Notes: 1. Values are guidelines only. 2. The Power-on Reset will not work unless the supply voltage has been below V (falling). ATmega8535(L) DATA BUS MCU Control and Status Register (MCUCSR) Timer Delay Counters Clock CK (1) Condition ...
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... This guarantees that a Brown-out Reset will occur before voltage where correct operation of the microcontroller is no longer guaranteed. The test is performed using BODLEVEL = 1 for ATmega8535L and BODLEVEL = 0 for ATmega8535. BODLEVEL = 1 is not applicable for ATmega8535. A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detec- tion level is defined in Table 15 ...
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... MCU after the Time-out period t Figure 18. External Reset During Operation CC ATmega8535 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V level during operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the fuse BODLEVEL to be 2.7V (BODLEVEL unprogrammed ...
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... Watchdog Reset MCU Control and Status Register – MCUCSR ATmega8535(L) 40 When the Watchdog times out, it will generate a short reset pulse of one CK cycle dura- tion. On the falling edge of this pulse, the delay timer starts counting the Time-out period t . Refer to page 41 for details on operation of the Watchdog Timer. ...
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... Chip Reset occurs. Eight different clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog Reset, the ATmega8535 resets and executes from the Reset Vector. For tim- ing details on the Watchdog Reset, refer to page 40. ...
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... Bits 7..5 – Res: Reserved Bits These bits are reserved bits in the ATmega8535 and will always read as zero. • Bit 4 – WDCE: Watchdog Change Enable This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not be disabled ...
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... Note: 1. Values are guidelines only. ATmega8535(L) (1) Typical Time-out Typical Time-out 3. 17.1 ms 16.3 ms 34.3 ms 32 0.14 s 0.13 s 0.27 s 0.26 s 0.55 s 0.52 s 1.1 s 1.0 s 2 5.0V 43 ...
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... ATmega8535(L) 44 The following code example shows one assembly and one C function for turning off the WDT. The example assumes that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions. Assembly Code Example WDT_off: ; Reset WDT wdr ...
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... In the same operation, write a logical one to WDCE and WDE. Even though the WDE always is set, the WDE must be written to one to start the timed sequence. 2. Within the next four clock cycles, in the same operation, write the WDP bits as desired, but with the WDCE bit cleared. The value written to the WDE bit is irrelevant. ATmega8535(L) 45 ...
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... Interrupts Interrupt Vectors in ATmega8535 ATmega8535(L) 46 This section describes the specifics of the interrupt handling as performed in ATmega8535. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 13. Table 19. Reset and Interrupt Vectors Vector Program (2) No. Address Source (1) 1 0x000 ...
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... Note: 1. The Boot Reset Address is shown in Table 93 on page 235. For the BOOTRST Fuse “1” means unprogrammed while “0” means programmed. The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega8535 is: AddressLabels Code 0x000 ...
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... ATmega8535(L) 48 AddressLabels Code 0x000 RESET: ldi r16,high(RAMEND) ; Main program start 0x001 out SPH,r16 0x002 ldi r16,low(RAMEND) 0x003 out SPL,r16 0x004 sei 0x005 <instr> xxx ; .org 0xC01 0xC01 rjmp EXT_INT0 0xC02 rjmp EXT_INT1 ... .... .. 0xC14 rjmp SPM_RDY When the BOOTRST Fuse is programmed and the Boot section size set to 2K bytes, the ...
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... Bit 0 – IVCE: Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the IVSEL description above. See Code Example below. ATmega8535( – ...
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... ATmega8535(L) 50 Assembly Code Example Move_interrupts: ; Enable change of interrupt vectors ldi r16, (1<<IVCE) out GICR, r16 ; Move interrupts to boot Flash section ldi r16, (1<<IVSEL) out GICR, r16 ret C Code Example void Move_interrupts(void Enable change of interrupt vectors */ GICR = (1<<IVCE); /* Move interrupts to boot Flash section */ GICR = (1< ...
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... Port Functions” on page 57. Refer to the individual module sections for a full description of the alternate functions. Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. ATmega8535( Logic See Figure " ...
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... Ports as General Digital I/O Configuring the Pin ATmega8535(L) 52 The ports are bi-directional I/O ports with optional internal pull-ups. Figure 23 shows a functional description of one I/O-port pin, here generically called Pxn. (1) Figure 23. General Digital I/O Pxn PUD: PULLUP DISABLE SLEEP: SLEEP CONTROL clk ...
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... The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low clocked into the PINxn Register at the suc- ATmega8535(L) I/O Pull-up ...
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... ATmega8535(L) 54 ceeding positive clock edge. As indicated by the two arrows t signal transition on the pin will be delayed between ½ and 1½ system clock period depending upon the time of assertion. When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure 25. The out instruction sets the “SYNC LATCH” signal at the positive edge of the clock ...
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... Port Func- tions” on page 57 logic high level (“one”) is present on an Asynchronous External Interrupt pin config- ured as “Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt is not enabled, the corresponding External Interrupt Flag will be set ATmega8535(L) / ...
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... Unconnected pins ATmega8535(L) 56 when resuming from the above mentioned sleep modes, as the clamping in these sleep modes produces the requested logic change. If some pins are unused recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode) ...
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... DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE SLEEP: SLEEP CONTROL Note: 1. WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk SLEEP, and PUD are common to all ports. All other signals are unique for each pin. ATmega8535(L) (1) PUOExn PUOVxn DDOExn DDOVxn ...
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... ATmega8535(L) 58 Table 22 summarizes the function of the overriding signals. The pin and port indexes from Figure 26 are not shown in the succeeding tables. The overriding signals are gen- erated internally in the modules having the alternate function. Table 22. Generic Description of Overriding Signals for Alternate Functions ...
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... Table 24 and Table 25 relate the alternate functions of Port A to the overriding signals shown in Figure 26 on page 57. Table 24. Overriding Signals for Alternate Functions in PA7..PA4 Signal Name PA7/ADC7 PUOE 0 PUOV 0 DDOE 0 DDOV 0 PVOE 0 PVOV 0 DIEOE 0 DIEOV 0 DI – AIO ADC7 INPUT ATmega8535( – ACME PUD PSR2 R R/W R/W R PA6/ADC6 PA5/ADC5 ...
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... Alternate Functions Of Port B ATmega8535(L) 60 Table 25. Overriding Signals for Alternate Functions in PA3..PA0 Signal Name PA3/ADC3 PUOE 0 PUOV 0 DDOE 0 DDOV 0 PVOE 0 PVOV 0 DIEOE 0 DIEOV 0 DI – AIO ADC3 INPUT The Port B pins with alternate functions are shown in Table 26. Table 26. Port B Pins Alternate Functions ...
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... USART operates in synchronous mode. Table 27 and Table 28 relate the alternate functions of Port B to the overriding signals shown in Figure 26 on page 57. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT. ATmega8535(L) 61 ...
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... Alternate Functions of Port C ATmega8535(L) 62 Table 27. Overriding Signals for Alternate Functions in PB7..PB4 Signal Name PB7/SCK PB6/MISO PUOE SPE • MSTR SPE • MSTR PUOV PORTB7 • PUD PORTB6 • PUD DDOE SPE • MSTR SPE • MSTR DDOV 0 0 PVOE SPE • MSTR SPE • ...
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... Figure 26 on page 57. Table 30. Overriding Signals for Alternate Functions in PC7..PC6 Signal Name PC7/TOSC2 PUOE AS2 PUOV 0 DDOE AS2 DDOV 0 PVOE 0 PVOV 0 DIEOE AS2 DIEOV 0 DI – AIO T/C2 OSC OUTPUT ATmega8535(L) PC6/TOSC1 AS2 0 AS2 AS2 0 – T/C2 OSC INPUT 63 ...
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... Alternate Functions of Port D ATmega8535(L) 64 Table 31. Overriding Signals for Alternate Functions in PC1..PC0 Signal Name PC1/SDA PUOE TWEN PUOV PORTC1 • PUD DDOE TWEN DDOV SDA_OUT PVOE TWEN PVOV 0 DIEOE 0 DIEOV 0 DI – AIO SDA INPUT Note: 1. When enabled, the Two-wire Serial Interface enables slew-rate controls on the output pins PC0 and PC1 ...
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... Figure 26 on page 57. Table 33. Overriding Signals for Alternate Functions PD7..PD4 Signal Name PD7/OC2 PUOE 0 PUOV 0 DDOE 0 DDOV 0 PVOE OC2 ENABLE PVOV OC2 DIEOE 0 DIEOV 0 DI – AIO – ATmega8535(L) PD6/ICP1 PD5/OC1A OC1A ENABLE 0 OC1A ICP1 INPUT – – – PD4/OC1B ...
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... Port A Data Register – PORTA Port A Data Direction Register – DDRA Port A Input Pins Address – PINA Port B Data Register – PORTB Port B Data Direction Register – DDRB ATmega8535(L) 66 Table 34. Overriding Signals for Alternate Functions in PD3..PD0 Signal Name PD3/INT1 PUOE 0 PUOV ...
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... R/W R/W R/W Initial Value Bit DDD7 DDD6 DDD5 Read/Write R/W R/W R/W Initial Value Bit PIND7 PIND6 PIND5 Read/Write Initial Value N/A N/A N/A ATmega8535( PINB4 PINB3 PINB2 PINB1 N/A N/A N/A N PORTC4 PORTC3 PORTC2 PORTC1 R/W R/W R/W R DDC4 ...
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... External Interrupts MCU Control Register – MCUCR ATmega8535(L) 68 The External Interrupts are triggered by the INT0, INT1, and INT2 pins. Observe that, if enabled, the interrupts will trigger even if the INT0..2 pins are configured as outputs. This feature provides a way of generating a software interrupt. The External Interrupts can be triggered by a falling or rising edge or a low level (INT2 is only an edge triggered interrupt). This is set up as indicated in the specification for the MCU Control Register – ...
Page 69
... The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10) in the MCU General Control Register (MCUCR) define whether the external interrupt is activated on the rising and/or falling edge of the INT1 pin or level sensed. Activity on the pin will cause an interrupt request even if INT1 is configured as an output. ATmega8535( – ...
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... General Interrupt Flag Register – GIFR ATmega8535(L) 70 The corresponding interrupt of External Interrupt Request 1 is executed from the INT1 Interrupt Vector. • Bit 6 – INT0: External Interrupt Request 0 Enable When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled ...
Page 71
... Overflow and Compare Match Interrupt Sources (TOV0 and OCF0) A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 27. For the actual placement of I/O pins, refer to “Pinout ATmega8535” on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the “ ...
Page 72
... Definitions Timer/Counter Clock Sources Counter Unit ATmega8535(L) 72 The double buffered Output Compare Register (OCR0) is compared with the Timer/Counter value at all times. The result of the compare can be used by the Wave- form Generator to generate a PWM or variable frequency output on the Output Compare pin (OC0). See “Output Compare Unit” on page 73. for details. The Compare Match event will also set the Compare Flag (OCF0) which can be used to generate an output compare interrupt request ...
Page 73
... Operation” on page 76.). Figure 29 shows a block diagram of the output compare unit. Figure 29. Output Compare Unit, Block Diagram OCRn top bottom FOCn ATmega8535(L) ). clk can be generated from an external or internal T0 is present or not. A CPU write overrides (has T0 DATA BUS TCNTn ...
Page 74
... Compare Match Blocking by TCNT0 Write Using the Output Compare Unit ATmega8535(L) 74 The OCR0 Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR0 Compare Register to either top or bottom of the counting sequence ...
Page 75
... Table 41 on page 84, and for phase correct PWM refer to Table 42 on page 84. A change of the COM01:0 bits state will have effect at the first Compare Match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC0 strobe bits. ATmega8535( OCn ...
Page 76
... Modes of Operation Normal Mode Clear Timer on Compare Match (CTC) Mode ATmega8535(L) 76 The mode of operation, i.e., the behavior of the Timer/Counter and the output compare pins, is defined by the combination of the Waveform Generation mode (WGM01:0) and Compare Output mode (COM01:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do ...
Page 77
... PWM mode is shown in Figure 32. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent compare matches between OCR0 and TCNT0. ATmega8535(L) f clk_I/O = ---------------------------------------------- - ⋅ ...
Page 78
... ATmega8535(L) 78 Figure 32. Fast PWM Mode, Timing Diagram TCNTn OCn OCn Period The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches MAX. If the interrupt is enabled, the interrupt handler routine can be used for updating the com- pare value. In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0 pin ...
Page 79
... The PWM waveform is generated by clearing (or setting) the OC0 Register at the Compare Match between OCR0 and TCNT0 when the counter increments, and setting (or clearing) the OC0 Register at Compare Match between ATmega8535(L) OCn Interrupt Flag Set OCRn Update ...
Page 80
... Timer/Counter Timing Diagrams ATmega8535(L) 80 OCR0 and TCNT0 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: f OCnPCPWM The “N” variable represents the prescale factor (1, 8, 64, 256, or 1024). The extreme values for the OCR0 Register represent special cases when generating a PWM waveform output in the phase correct PWM mode ...
Page 81
... Figure 36. Timer/Counter Timing Diagram, Setting of OCF0, with Prescaler (f clk I/O clk Tn (clk /8) I/O TCNTn OCRn - 1 OCRn OCFn Figure 37 shows the setting of OCF0 and the clearing of TCNT0 in CTC mode. ATmega8535(L) /8) clk_I/O MAX BOTTOM OCRn OCRn + 1 OCRn Value BOTTOM + 1 /8) clk_I/O OCRn + 2 81 ...
Page 82
... ATmega8535(L) 82 Figure 37. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with Prescaler (f /8) clk_I/O clk I/O clk Tn (clk /8) I/O TCNTn TOP - 1 (CTC) OCRn OCFn TOP BOTTOM TOP 2502K–AVR–10/06 BOTTOM + 1 ...
Page 83
... These bits control the Output Compare pin (OC0) behavior. If one or both of the COM01:0 bits are set, the OC0 output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corre- sponding to the OC0 pin must be set in order to enable the output driver. ATmega8535( ...
Page 84
... ATmega8535(L) 84 When OC0 is connected to the pin, the function of the COM01:0 bits depends on the WGM01:0 bit setting. Table 40 shows the COM01:0 bit functionality when the WGM01:0 bits are set to a normal or CTC mode (non-PWM). Table 40. Compare Output Mode, non-PWM Mode COM01 COM00 ...
Page 85
... When the OCIE0 bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter0 Compare Match interrupt is enabled. The corresponding interrupt is executed if a Compare Match in Timer/Counter0 occurs (i.e., when the OCF0 bit is set in the Timer/Counter Interrupt Flag Register – TIFR). ATmega8535(L) /(No prescaling) /8 (From prescaler) /64 (From prescaler) ...
Page 86
... Timer/Counter Interrupt Flag Register – TIFR ATmega8535(L) 86 • Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable When the TOIE0 bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs (i.e., when the TOV0 bit is set in the Timer/Counter Interrupt Flag Register – ...
Page 87
... T1/T0 pin to the counter is updated. Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least one system clock cycle, otherwise risk that a false Timer/Counter clock pulse is generated. ATmega8535(L) ). Alternatively, one of four taps from CLK_I/O /256 /1024 ...
Page 88
... Special Function IO Register – SFIOR ATmega8535(L) 88 Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the system clock frequency (f the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem) ...
Page 89
... A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 40. For the actual placement of I/O pins, refer to “Pinout ATmega8535” on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the “16-bit Timer/Counter Register Description” ...
Page 90
... Registers ATmega8535(L) 90 Figure 40. 16-bit Timer/Counter Block Diagram Count Clear Control Logic Direction Timer/Counter TCNTn = OCRnA = OCRnB ICRn TCCRnA Note: 1. Refer to Figure 1 on page 2, Table 26 on page 60, and Table 32 on page 64 for Timer/Counter1 pin placement and description. The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture Register (ICR1) are all 16-bit registers. Special procedures must be followed when accessing the 16-bit registers. These procedures are described in the section “ ...
Page 91
... PWM11 is changed to WGM11. • CTC1 is changed to WGM12. The following bits are added to the 16-bit Timer/Counter Control Registers: • FOC1A and FOC1B are added to TCCR1A. • WGM13 is added to TCCR1B. The 16-bit Timer/Counter has improvements that will affect the compatibility in some special cases. ATmega8535(L) 91 ...
Page 92
... Accessing 16-bit Registers ATmega8535(L) 92 The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations. Each 16-bit timer has a single 8-bit register for temporary storing of the high byte of the 16-bit access ...
Page 93
... Save Global Interrupt Flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Read TCNT1 into TCNT1; /* Restore Global Interrupt Flag */ SREG = sreg; return i; } Note: 1. See “About Code Examples” on page 7. The assembly code example returns the TCNT1 value in the r17:r16 register pair. ATmega8535(L) 93 ...
Page 94
... Re-using the Temporary High Byte Register ATmega8535(L) 94 The following code examples show how atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle. (1) Assembly Code Example TIM16_WriteTCNT1: ; Save Global Interrupt Flag in r18,SREG ; Disable interrupts cli ...
Page 95
... CPU, independent of whether clk rides (has priority over) all counter clear or count operations. The counting sequence is determined by the setting of the Waveform Generation mode bits (WGM13:0) located in the Timer/Counter Control Registers A and B (TCCR1A and ATmega8535(L) TOVn (Int.Req.) Clock Select Count ...
Page 96
... Input Capture Unit ATmega8535(L) 96 TCCR1B). There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare outputs OC1x. For more details about advanced counting sequences and waveform generation, see “Modes of Opera- tion” on page 101. ...
Page 97
... Measurement of an external signal’s duty cycle requires that the trigger edge is changed after each capture. Changing the edge sensing must be done as early as possible after the ICR1 Register has been read. After a change of the edge, the Input Capture Flag (ICF1) must be cleared by software (writing a logical one to the I/O bit location). For ATmega8535(L) 97 ...
Page 98
... Output Compare Units ATmega8535(L) 98 measuring frequency only, the clearing of the ICF1 Flag is not required (if an interrupt handler is used). The 16-bit comparator continuously compares TCNT1 with the Output Compare Regis- ter (OCR1x). If TCNT equals OCR1x the comparator signals a match. A match will set the Output Compare Flag (OCF1x) at the next timer clock cycle ...
Page 99
... Output Compare (FOC1x) strobe bits in Normal mode. The OC1x Register keeps its value even when changing between Waveform Generation modes. Be aware that the COM1x1:0 bits are not double buffered together with the compare value. Changing the COM1x1:0 bits will take effect immediately. ATmega8535(L) 99 ...
Page 100
... Compare Match Output Unit Compare Output Mode and Waveform Generation ATmega8535(L) 100 The Compare Output Mode (COM1x1:0) bits have two functions. The waveform genera- tor uses the COM1x1:0 bits for defining the Output Compare (OC1x) state at the next Compare Match. Secondly the COM1x1:0 bits control the OC1x pin output source. Fig- ure 44 shows a simplified schematic of the logic affected by the COM1x1:0 bit setting ...
Page 101
... This mode allows greater control of the Compare Match output frequency. It also simplifies the operation of counting external events. The timing diagram for the CTC mode is shown in Figure 45. The counter value (TCNT1) increases until a Compare Match occurs with either OCR1A or ICR1, and then counter (TCNT1) is cleared. ATmega8535(L) 101 ...
Page 102
... Fast PWM Mode ATmega8535(L) 102 Figure 45. CTC Mode, Timing Diagram TCNTn OCnA (Toggle) Period interrupt can be generated each time the counter value reaches the TOP value by either using the OCF1A or ICF1 Flag according to the register used to define the TOP value. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value ...
Page 103
... ICR1 value written is lower than the current value of TCNT1. The result will then be that the counter will miss the Compare Match at the TOP value. ATmega8535( ...
Page 104
... Phase Correct PWM Mode ATmega8535(L) 104 The counter will then have to count to the MAX value (0xFFFF) and wrap around start- ing at 0x0000 before the Compare Match can occur. The OCR1A Register however, is double buffered. This feature allows the OCR1A I/O location to be written anytime. ...
Page 105
... The reason for this can be found in the time of update of the OCR1x Register. Since the OCR1x update occurs at TOP, the PWM period starts and ends at TOP. This implies that the length of the fall- ATmega8535( ...
Page 106
... Phase and Frequency Correct PWM Mode ATmega8535(L) 106 ing slope is determined by the previous TOP value, while the length of the rising slope is determined by the new TOP value. When these two values differ the two slopes of the period will differ in length. The difference in length gives the unsymmetrical result on the output ...
Page 107
... ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. However, if the base PWM frequency is actively changed by changing the TOP value, using the OCR1A as TOP is clearly a better choice due to its double buffer feature. ATmega8535(L) OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) ...
Page 108
... Timer/Counter Timing Diagrams ATmega8535(L) 108 In phase and frequency correct PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins. Setting the COM1x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM1x1:0 to three (see Table 47 on page 111). The actual OC1x value will only be vis- ible on the port pin if the data direction for the port pin is set as output (DDR_OC1x) ...
Page 109
... TOP - 1 (PC and PFC PWM) TOVn (FPWM) and ICFn (if used as TOP) OCRnx Old OCRnx Value (Update at TOP) Figure 52 shows the same timing data, but with the prescaler enabled. ATmega8535(L) OCRnx OCRnx + 1 OCRnx Value TOP BOTTOM TOP TOP - 1 New OCRnx Value /8) clk_I/O ...
Page 110
... Timer/Counter Register Description Timer/Counter1 Control Register A – TCCR1A ATmega8535(L) 110 Figure 52. Timer/Counter Timing Diagram, with Prescaler (f clk I/O clk Tn (clk /8) I/O TCNTn TOP - 1 (CTC and FPWM) TCNTn TOP - 1 (PC and PFC PWM) TOVn (FPWM) and ICFn (if used as TOP) OCRnx Old OCRnx Value ...
Page 111
... COM1x1:0 bits that determine the effect of the forced compare. A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare Match (CTC) mode using OCR1A as TOP. The FOC1A/FOC1B bits are always read as zero. • Bit 1:0 – WGM11:0: Waveform Generation Mode ATmega8535(L) (1) 111 ...
Page 112
... The CTC1 and PWM11:0 bit definition names are obsolete. Use the WGM12:0 definitions. However, the functionality and location of these bits are compatible with previous versions of the timer. ATmega8535(L) 112 Combined with the WGM13:2 bits found in the TCCR1B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 48 ...
Page 113
... External clock source on T1 pin. Clock on falling edge External clock source on T1 pin. Clock on rising edge. If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. ATmega8535( WGM13 WGM12 CS12 ...
Page 114
... Timer/Counter1 – TCNT1H and TCNT1L Output Compare Register 1 A – OCR1AH and OCR1AL Output Compare Register 1 B – OCR1BH and OCR1BL Input Capture Register 1 – ICR1H and ICR1L ATmega8535(L) 114 Bit Read/Write R/W R/W R/W Initial Value The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct access, both for read and for write operations, to the Timer/Counter unit 16-bit counter ...
Page 115
... Bit 2 – TOIE1: Timer/Counter1, Overflow Interrupt Enable When this bit is written to one and the I-flag in the Status Register is set (interrupts glo- bally enabled), the Timer/Counter1 overflow interrupt is enabled. The corresponding Interrupt Vector (see “Interrupts” on page 46) is executed when the TOV1 Flag, located in TIFR, is set. ATmega8535( ...
Page 116
... Timer/Counter Interrupt Flag (1) Register – TIFR ATmega8535(L) 116 Bit OCF2 TOV2 ICF1 Read/Write R/W R/W R/W Initial Value Note: 1. This register contains flag bits for several Timer/Counters, but only Timer1 bits are described in this section. The remaining bits are described in their respective timer sections. • ...
Page 117
... Allows Clocking from External 32 kHz Watch Crystal Independent of the I/O Clock A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 53. For the actual placement of I/O pins, refer to “Pinout ATmega8535” on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the “ ...
Page 118
... Registers Definitions Timer/Counter Clock Sources ATmega8535(L) 118 The Timer/Counter (TCNT2) and Output Compare Register (OCR2) are 8-bit registers. Interrupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK) ...
Page 119
... WGM21:0 bits and Compare Output mode (COM21:0) bits. The max and bottom sig- nals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation (see “Modes of Operation” on page 122). Figure 55 shows a block diagram of the output compare unit. ATmega8535(L) TOVn (Int.Req.) clk ...
Page 120
... Force Output Compare Compare Match Blocking by TCNT2 Write Using the Output Compare Unit ATmega8535(L) 120 Figure 55. Output Compare Unit, Block Diagram OCRn top bottom FOCn The OCR2 Register is double buffered when using any of the pulse width modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled ...
Page 121
... OC2 Register performed on the next Compare Match. For com- pare output actions in the non-PWM modes refer to Table 52 on page 129. For fast PWM mode, refer to Table 53 on page 129, and for phase correct PWM refer to Table 54 on page 130. ATmega8535( ...
Page 122
... Modes of Operation Normal Mode Clear Timer on Compare Match (CTC) Mode ATmega8535(L) 122 A change of the COM21:0 bits state will take effect at the first Compare Match after the bits are written. For non-PWM modes, the action can be forced to have an immediate effect by using the FOC2 strobe bits. ...
Page 123
... PWM mode is shown in Figure 58. The TCNT2 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2 and TCNT2. ATmega8535(L) f clk_I/O = ---------------------------------------------- - ⋅ ...
Page 124
... ATmega8535(L) 124 Figure 58. Fast PWM Mode, Timing Diagram TCNTn OCn OCn Period The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches MAX. If the interrupt is enabled, the interrupt handler routine can be used for updating the com- pare value. In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2 pin ...
Page 125
... The PWM waveform is generated by clearing (or setting) the OC2 Register at the Compare Match between OCR2 and TCNT2 when the counter increments, and setting (or clearing) the OC2 Register at Compare Match ATmega8535(L) OCn Interrupt Flag Set OCRn Update ...
Page 126
... Timer/Counter Timing Diagrams ATmega8535(L) 126 between OCR2 and TCNT2 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: f OCnPCPWM The “N” variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). ...
Page 127
... Figure 62. Timer/Counter Timing Diagram, Setting of OCF2, with Prescaler (f clk I/O clk Tn (clk /8) I/O TCNTn OCRn - 1 OCRn OCFn Figure 63 shows the setting of OCF2 and the clearing of TCNT2 in CTC mode. ATmega8535(L) /8) clk_I/O MAX BOTTOM OCRn OCRn + 1 OCRn Value BOTTOM + 1 /8) clk_I/O OCRn + 2 127 ...
Page 128
... Timer/Counter Register Description Timer/Counter Control Register – TCCR2 ATmega8535(L) 128 Figure 63. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with Prescaler (f /8) clk_I/O clk I/O clk Tn (clk /8) I/O TCNTn TOP - 1 (CTC) OCRn OCFn Bit FOC2 WGM20 COM21 Read/Write W R/W R/W ...
Page 129
... Set OC2 on Compare Match, clear OC2 at TOP (Inverting). Note special case occurs when OCR2 equals TOP and COM21 is set. In this case, the Compare Match is ignored, but the set or clear is done at TOP. See “Fast PWM Mode” on page 123 for more details. ATmega8535(L) (1) Update of TOV2 Flag TOP ...
Page 130
... Timer/Counter Register – TCNT2 ATmega8535(L) 130 Table 54 shows the COM21:0 bit functionality when the WGM21:0 bits are set to phase correct PWM mode. Table 54. Compare Output Mode, Phase Correct PWM Mode COM21 COM20 Description 0 0 Normal port operation, OC2 disconnected Reserved 1 0 Clear OC2 on Compare Match when up-counting. Set OC2 on Compare Match when down-counting ...
Page 131
... The mechanisms for reading TCNT2, OCR2, and TCCR2 are different. When reading TCNT2, the actual timer value is read. When reading OCR2 or TCCR2, the value in the temporary storage register is read. ATmega8535( ...
Page 132
... Asynchronous Operation of Timer/Counter2 ATmega8535(L) 132 When Timer/Counter2 operates asynchronously, some considerations must be taken. • Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the timer registers TCNT2, OCR2, and TCCR2 might be corrupted. A safe procedure for switching clock source is: 1. Disable the Timer/Counter2 interrupts by clearing OCIE2 and TOIE2. ...
Page 133
... When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter2 occurs (i.e., when the TOV2 bit is set in the Timer/Counter Interrupt Flag Register – TIFR). ATmega8535(L) ) again becomes active, TCNT2 will I/O 4 ...
Page 134
... Timer/Counter Interrupt Flag Register – TIFR Timer/Counter Prescaler ATmega8535(L) 134 Bit OCF2 TOV2 ICF1 Read/Write R/W R/W R/W Initial Value • Bit 7 – OCF2: Output Compare Flag 2 The OCF2 bit is set (one) when a Compare Match occurs between the Timer/Counter2 and the data in OCR2 – Output Compare Register 2. OCF2 is cleared by hardware when executing the corresponding interrupt handling vector ...
Page 135
... Writing a zero to this bit will have no effect. This bit will always be read as zero if Timer/Counter2 is clocked by the internal CPU clock. If this bit is written when Timer/Counter2 is operating in asynchronous mode, the bit will remain one until the prescaler has been reset. ATmega8535( ...
Page 136
... Serial Peripheral Interface – SPI ATmega8535(L) 136 The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega8535 and peripheral devices or between several AVR devices. The ATmega8535 SPI includes the following features: • Full Duplex, Three-wire Synchronous Data Transfer • ...
Page 137
... High periods: Longer than 2 CPU clock cycles. When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Table 56 on page 138. For more details on automatic port over- rides, refer to “Alternate Port Functions” on page 57. ATmega8535(L) MSB SLAVE MISO ...
Page 138
... ATmega8535(L) 138 (1) Table 56. SPI Pin Overrides Pin Direction, Master SPI MOSI User Defined MISO Input SCK User Defined SS User Defined Note: 1. See “Alternate Functions Of Port B” on page 60 for a detailed description of how to define the direction of the user defined SPI pins. The following code examples show how to initialize the SPI as a Master and how to per- form a simple transmission ...
Page 139
... DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK); /* Enable SPI, Master, set clock rate fck/16 */ SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0); } void SPI_MasterTransmit(char cData Start transmission */ SPDR = cData; /* Wait for transmission complete */ while(!(SPSR & (1<<SPIF))) ; } Note: 1. See “About Code Examples” on page 7. ATmega8535(L) 139 ...
Page 140
... ATmega8535(L) 140 The following code examples show how to initialize the SPI as a Slave and how to per- form a simple reception. (1) Assembly Code Example SPI_SlaveInit: ; Set MISO output, all others input ldi r17,(1<<DD_MISO) out DDR_SPI,r17 ; Enable SPI ldi r17,(1<<SPE) ...
Page 141
... When the DORD bit is written to zero, the MSB of the data word is transmitted first. • Bit 4 – MSTR: Master/Slave Select This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic zero configured as an input and is driven low while MSTR is set, MSTR will ATmega8535( ...
Page 142
... ATmega8535(L) 142 be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Master mode. • Bit 3 – CPOL: Clock Polarity When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low when idle. Refer to Figure 67 and Figure 68 for an example. The CPOL func- tionality is summarized below: Table 57 ...
Page 143
... WCOL set, and then accessing the SPI Data Register. • Bit 5..1 – Res: Reserved Bits These bits are reserved bits in the ATmega8535 and will always read as zero. • Bit 0 – SPI2X: Double SPI Speed Bit When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode (see Table 59) ...
Page 144
... Data Modes ATmega8535(L) 144 There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure 67 and Figure 68. Data bits are shifted out and latched in on oppo- site edges of the SCK signal, ensuring sufficient time for data signals to stabilize ...
Page 145
... UBRR[H:L] BAUD RATE GENERATOR UDR (Transmit) TRANSMIT SHIFT REGISTER RECEIVE SHIFT REGISTER UDR (Receive) UCSRA Note: 1. Refer to Figure 1 on page 2, Table 34 on page 66, and Table 28 on page 62 for USART pin placement. ATmega8535(L) (1) Clock Generator OSC SYNC LOGIC PIN CONTROL Transmitter TX CONTROL ...
Page 146
... AVR USART vs. AVR UART – Compatibility Clock Generation ATmega8535(L) 146 The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): Clock Generator, Transmitter and Receiver. Control registers are shared by all units. The clock generation logic consists of synchronization logic for exter- nal clock input used by synchronous slave operation, and the baud rate generator ...
Page 147
... UMSEL, U2X and DDR_XCK bits. Table 61 contains equations for calculating the baud rate (in bits per second) and for calculating the UBRR value for each mode of operation using an internally generated clock source. ATmega8535(L) fosc UBRR ...
Page 148
... Double Speed Operation (U2X) External Clock ATmega8535(L) 148 Table 61. Equations for Calculating Baud Rate Register Setting Equation for Calculating Operating Mode Asynchronous Normal Mode (U2X = 0) BAUD Asynchronous Double Speed Mode (U2X = 1) BAUD Synchronous Master Mode BAUD Note: 1. The baud rate is defined to be the transfer rate in bit per second (bps). ...
Page 149
... Figure 72 illustrates the possible combinations of the frame formats. Bits inside brackets are optional. Figure 72. Frame Formats (IDLE Start bit, always low. (n) Data bits (0 to 8). P Parity bit. Can be odd or even. ATmega8535(L) Sample Sample FRAME 3 4 [5] [6] [7] [8] [P] Sp1 [Sp2] (St / IDLE) 149 ...
Page 150
... Parity Bit Calculation USART Initialization ATmega8535(L) 150 Sp Stop bit, always high. IDLE No transfers on the communication line (RxD or TxD). An IDLE line must be high. The frame format used by the USART is set by the UCSZ2:0, UPM1:0 and USBS bits in UCSRB and UCSRC. The Receiver and Transmitter use the same setting. Note that changing the setting of any of these bits will corrupt all ongoing communication for both the Receiver and Transmitter ...
Page 151
... However, many applications use a fixed setting of the baud and control registers, and for these types of applications the initialization code can be placed directly in the main routine or be combined with initialization code for other I/O modules. ATmega8535(L) 151 ...
Page 152
... Data Transmission – The USART Transmitter Sending Frames with Data Bits ATmega8535(L) 152 The USART Transmitter is enabled by setting the Transmit Enable (TXEN) bit in the UCSRB Register. When the Transmitter is enabled, the normal port operation of the TxD pin is overridden by the USART and given the function as the Transmitter’s serial output ...
Page 153
... Register. For compatibility with future devices, always write this bit to zero when writing the UCSRA Register. When the Data Register Empty Interrupt Enable (UDRIE) bit in UCSRB is written to one, the USART Data Register Empty interrupt will be executed as long as UDRE is set (pro- vided that global interrupts are enabled). UDRE is cleared by writing UDR. When ATmega8535(L) 153 ...
Page 154
... Parity Generator Disabling the Transmitter ATmega8535(L) 154 interrupt-driven data transmission is used, the Data Register Empty interrupt routine must either write new data to UDR in order to clear UDRE or disable the Data Register Empty interrupt, otherwise a new interrupt will occur once the interrupt routine terminates ...
Page 155
... Get and return received data from buffer */ return UDR; } Note: 1. See “About Code Examples” on page 7. The function simply waits for data to be present in the receive buffer by checking the RXC Flag, before reading the buffer and returning the value. ATmega8535(L) 155 ...
Page 156
... Receiving Frames with 9 Data Bits ATmega8535(L) 156 If 9-bit characters are used (UCSZ=7) the ninth bit must be read from the RXB8 bit in UCSRB before reading the low bits from the UDR. This rule applies to the FE, DOR, and PE Status Flags as well. Read status from UCSRA, then data from UDR. Reading the UDR I/O location will change the state of the receive buffer FIFO and consequently the TXB8, FE, DOR, and PE bits, which all are stored in the FIFO, will change ...
Page 157
... Parity Check to be performed (odd or even) is selected by the UPM0 bit. When enabled, the Parity Checker calculates the parity of the data bits in incoming frames and compares the result with the parity bit from the serial frame. The result of the check is ATmega8535(L) 157 ...
Page 158
... Asynchronous Data Reception Asynchronous Clock Recovery ATmega8535(L) 158 stored in the receive buffer together with the received data and stop bits. The Parity Error (PE) Flag can then be read by software to check if the frame had a Parity Error. The PE bit is set if the next character that can be read from the receive buffer had a par- ity error when received and the parity checking was enabled at that point (UPM1 = 1) ...
Page 159
... RxD pin. The recovery process is then repeated until a complete frame is received. Including the first stop bit. Note that the Receiver only uses the first stop bit of a frame. Figure 75 shows the sampling of the stop bit and the earliest possible beginning of the start bit of the next frame. ATmega8535(L) START ...
Page 160
... Asynchronous Operational Range ATmega8535(L) 160 Figure 75. Stop Bit Sampling and Next Start Bit Sampling RxD Sample (U2X = Sample (U2X = The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop bit is registered to have a logic 0 value, the Frame Error (FE) Flag will be set. ...
Page 161
... The second source for the error is more controllable. The baud rate generator can not always do an exact division of the system frequency to get the baud rate wanted. In this case an UBRR value that gives an acceptable low error can be used if possible. ATmega8535(L) Max Total Recommended Max (%) ...
Page 162
... Multi-processor Communication Mode Using MPCM ATmega8535(L) 162 Setting the Multi-processor Communication Mode (MPCM) bit in UCSRA enables a fil- tering function of incoming frames received by the USART Receiver. Frames that do not contain address information will be ignored and not put into the receive buffer. This effectively reduces the number of incoming frames that has to be handled by the CPU system with multiple MCUs that communicate via the same serial bus ...
Page 163
... Set the USBS and the UCSZ1 bit to one, and */ /* the remaining bits to zero. */ UCSRC = (1<<URSEL)|(1<<USBS)|(1<<UCSZ1); ... Note: 1. See “About Code Examples” on page 7. As the code examples illustrate, write accesses of the two registers are relatively unaf- fected of the sharing of I/O location. ATmega8535(L) 163 ...
Page 164
... USART Register Description USART I/O Data Register – UDR ATmega8535(L) 164 Doing a read access to the UBRRH or the UCSRC Register is a more complex opera- tion. However, in most applications rarely necessary to read any of these registers. The read access is controlled by a timed sequence. Reading the I/O location once returns the UBRRH Register contents ...
Page 165
... This bit is set if the next character in the receive buffer had a Parity Error when received and the parity checking was enabled at that point (UPM1 = 1). This bit is valid until the receive buffer (UDR) is read. Always set this bit to zero when writing to UCSRA. ATmega8535( ...
Page 166
... USART Control and Status Register B – UCSRB ATmega8535(L) 166 • Bit 1 – U2X: Double the USART Transmission Speed This bit only has effect for the asynchronous operation. Write this bit to zero when using synchronous operation. Writing this bit to one will reduce the divisor of the baud rate divider from effec- tively doubling the transfer rate for asynchronous communication. • ...
Page 167
... UCSRC. The URSEL must be one when writing the UCSRC. • Bit 6 – UMSEL: USART Mode Select This bit selects between asynchronous and synchronous mode of operation. Table 64. UMSEL Bit Settings UMSEL Mode 0 Asynchronous Operation 1 Synchronous Operation ATmega8535( UPM0 USBS UCSZ1 UCSZ0 UCPOL ...
Page 168
... ATmega8535(L) 168 • Bit 5:4 – UPM1:0: Parity Mode These bits enable and set type of parity generation and check. If enabled, the Transmit- ter will automatically generate and send the parity of the transmitted data bits within each frame. The Receiver will generate a parity value for the incoming data and com- pare it to the UPM0 setting ...
Page 169
... UBRRL contains the eight least significant bits of the USART baud rate. Ongoing transmissions by the Transmitter and Receiver will be cor- rupted if the baud rate is changed. Writing UBRRL will trigger an immediate update of the baud rate prescaler. ATmega8535(L) Received Data Sampled (Input on RxD Pin) Falling XCK Edge ...
Page 170
... UBRR = 0, Error = 0.0% ATmega8535(L) 170 For standard crystal and resonator frequencies, the most commonly used baud rates for asynchronous operation can be generated by using the UBRR settings in Table 69. UBRR values which yield an actual baud rate differing less than 0.5% from the target baud rate, are bold in the table ...
Page 171
... ATmega8535( 7.3728 MHz osc U2X = 1 U2X = 0 Error UBRR Error 207 0.2% 191 0.0% 103 0.2% 95 0.0% 51 0.2% 47 0.0% 34 -0.8% 31 0.0% 25 ...
Page 172
... Max 0.5 Mbps 1 Mbps 1. UBRR = 0, Error = 0.0% ATmega8535(L) 172 11.0592 f = MHz osc U2X = 0 U2X = 1 Error UBRR Error UBRR -0.1% 287 0.0% 575 0.2% 143 0.0% 287 0.2% 71 0.0% 143 0. ...
Page 173
... Mbps 1.152 Mbps ATmega8535( 20.0000 MHz osc U2X = 1 U2X = 0 Error UBRR Error 959 0.0% 520 0.0% 479 0.0% 259 0.2% 239 0.0% 129 0.2% 159 0. ...
Page 174
... Two-wire Serial Interface Features Two-wire Serial Interface Bus Definition TWI Terminology ATmega8535(L) 174 • Simple yet Powerful and Flexible Communication Interface, only Two Bus Lines Needed • Both Master and Slave Operation Supported • Device can Operate as Transmitter or Receiver • 7-bit Address Space Allows up to 128 Different Slave Addresses • ...
Page 175
... START behavior, and therefore START is used to describe both START and REPEATED START for the remainder of this datasheet, unless otherwise noted. As depicted below, START and STOP conditions are signalled by changing the level of the SDA line when the SCL line is high. ATmega8535(L) Data Stable Data Change 175 ...
Page 176
... Address Packet Format Data Packet Format ATmega8535(L) 176 Figure 78. START, REPEATED START, and STOP Conditions SDA SCL START All address packets transmitted on the TWI bus are nine bits long, consisting of seven address bits, one READ/WRITE control bit and an acknowledge bit. If the READ/WRITE bit is set, a read operation performed, otherwise a write operation should be per- formed ...
Page 177
... Masters, in order to let the transmission proceed in a lockstep fashion. This will facilitate the arbitration process. The wired-ANDing of the bus lines is used to solve both these problems. The serial clocks from all Masters will be wired-ANDed, yielding a combined clock with a high ATmega8535(L) Data LSB ACK 7 ...
Page 178
... ATmega8535(L) 178 period equal to the one from the Master with the shortest high period. The low period of the combined clock is equal to the low period of the Master with the longest low period. Note that all masters listen to the SCL line, effectively starting to count their SCL high and low time-out periods when the combined SCL line goes high or low, respectively ...
Page 179
... Note that the inter- nal pull-ups in the AVR pads can be enabled by setting the PORT bits corresponding to the SCL and SDA pins, as explained in the I/O Port section. The internal pull-ups can in some systems eliminate the need for external ones. ATmega8535(L) SDA Spike Slew-rate ...
Page 180
... Bit Rate Generator Unit Bus Interface Unit Address Match Unit Control Unit ATmega8535(L) 180 This unit controls the period of SCL when operating in a Master mode. The SCL period is controlled by settings in the TWI Bit Rate Register (TWBR) and the Prescaler bits in the TWI Status Register (TWSR). Slave operation does not depend on Bit Rate or Pres- caler settings, but the CPU clock frequency in the Slave must be at least 16 times higher than the SCL frequency ...
Page 181
... ACK pulse is generated on the TWI bus if the following conditions are met: 1. The device’s own slave address has been received general call has been received, while the TWGCE bit in the TWAR is set data byte has been received in Master Receiver or Slave Receiver mode. ATmega8535( ...
Page 182
... ATmega8535(L) 182 By writing the TWEA bit to zero, the device can be virtually disconnected from the Two- wire Serial Bus temporarily. Address recognition can then be resumed by writing the TWEA bit to one again. • Bit 5 – TWSTA: TWI START Condition Bit The application writes the TWSTA bit to one when it desires to become a Master on the Two-wire Serial Bus ...
Page 183
... TWI logic, the CPU cannot access the ACK bit directly. • Bits 7..0 – TWD: TWI Data Register These eight bits constitute the next data byte to be transmitted, or the latest data byte received on the Two-wire Serial Bus. Bit TWA6 TWA5 TWA4 ATmega8535( TWS4 TWS3 – TWPS1 TWPS0 R ...
Page 184
... ATmega8535(L) 184 Read/Write R/W R/W R/W Initial Value The TWAR should be loaded with the 7-bit slave address (in the seven most significant bits of TWAR) to which the TWI will respond when programmed as a Slave Transmitter or Receiver, and not needed in the Master modes. In multimaster systems, TWAR must be set in masters which can be addressed as slaves by other masters ...
Page 185
... START condition was successfully transmitted. If TWSR indicates other- wise, the application software might take some special action, like calling an error routine. Assuming that the status code is as expected, the application must ATmega8535(L) 7. Check TWSR to see if data was sent and ACK received. Application loads ...
Page 186
... ATmega8535(L) 186 load SLA+W into TWDR. Remember that TWDR is used both for address and data. After TWDR has been loaded with the desired SLA+W, a specific value must be written to TWCR, instructing the TWI hardware to transmit the SLA+W present in TWDR. Which value to write is described later on. However important that the TWINT bit is set in the value written ...
Page 187
... TWCR = (1<<TWINT) | (1<<TWEN); while (!(TWCR & (1<<TWINT))) ; if ((TWSR & 0xF8) != MT_DATA_ACK) ERROR(); TWCR = (1<<TWINT)|(1<<TWEN)| (1<<TWSTO); ATmega8535(L) Comments Send START condition. Wait for TWINT Flag set. This indicates that the START condition has been transmitted. Check value of TWI Status Register ...
Page 188
... Transmission Modes ATmega8535(L) 188 The TWI can operate in one of four major modes. These are named Master Transmitter (MT), Master Receiver (MR), Slave Transmitter (ST), and Slave Receiver (SR). Several of these modes can be used in the same application example, the TWI can use MT mode to write data into a TWI EEPROM, MR mode to read the data back from the EEPROM ...
Page 189
... TWINT is high. If not, the access will be discarded, and the Write Collision bit (TWWC) will be set in the TWCR Register. After updating TWDR, the TWINT bit should be cleared (by writing it to one) to continue the transfer. This is accomplished by writing the following value to TWCR: TWCR TWINT TWEA TWSTA Value 1 X ATmega8535( Device 3 Device n ........ R1 TWSTO TWWC TWEN 1 ...
Page 190
... NOT ACK has been received 0x38 Arbitration lost in SLA+W or data bytes ATmega8535(L) 190 This scheme is repeated until the last byte has been sent and the transfer is ended by generating a STOP condition or a repeated START condition. A STOP condition is gen- erated by writing the following value to TWCR: ...
Page 191
... Next transfer started with a repeated start condition Not acknowledge received after the slave address Not acknowledge received after a data byte Arbitration lost in slave address or data byte Arbitration lost and addressed as slave From master to slave From slave to master ATmega8535(L) A DATA A P $ $30 ...
Page 192
... Master Receiver Mode ATmega8535(L) 192 In the Master Receiver mode, a number of data bytes are received from a Slave Trans- mitter (see Figure 88). In order to enter a Master mode, a START condition must be transmitted. The format of the following address packet determines whether Master Transmitter or Master Receiver mode entered. If SLA+W is transmitted, MT mode is entered, if SLA+R is transmitted, MR mode is entered ...
Page 193
... Read data byte Read data byte 0 0 Read data byte Read data byte Read data byte 1 1 ATmega8535(L) TWSTO TWWC TWEN TWINT TWEA Next Action Taken by TWI Hardware 1 X SLA+R will be transmitted ACK or NOT ACK will be received 1 X SLA+R will be transmitted ...
Page 194
... Slave Receiver Mode ATmega8535(L) 194 Figure 89. Formats and States in the Master Receiver Mode MR Successfull S SLA R A reception from a slave receiver $08 $40 Next transfer started with a repeated start condition Not acknowledge A received after the slave address $48 Arbitration lost in slave address or data byte ...
Page 195
... SCL line may be held low for a long time, blocking other data transmissions. Note that the Two-wire Serial Interface Data Register – TWDR – does not reflect the last byte present on the bus when waking up from these sleep modes. ATmega8535(L) TWA4 TWA3 TWA2 TWA1 Device’ ...
Page 196
... Previously addressed with general call; data has been received; NOT ACK has been returned 0xA0 A STOP condition or repeated START condition has been received while still addressed as Slave ATmega8535(L) 196 Application Software Response To TWCR To/from TWDR STA STO TWINT No TWDR action or X ...
Page 197
... Reception of the general call General Call address and one or more data bytes Last data byte received is not acknowledged Arbitration lost as master and addressed as slave by general call From master to slave From slave to master ATmega8535( DATA A $60 $80 A $68 A DATA ...
Page 198
... Slave Transmitter Mode ATmega8535(L) 198 In the Slave Transmitter mode, a number of data bytes are transmitted to a Master Receiver (see Figure 92). All the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. Figure 92. Data Transfer in Slave Transmitter Mode ...
Page 199
... No TWDR action TWDR action TWDR action TWDR action 1 0 ATmega8535(L) TWINT TWEA Next Action Taken by TWI Hardware 1 0 Last data byte will be transmitted and NOT ACK should be received 1 1 Data byte will be transmitted and ACK should be re- ceived 1 0 Last data byte will be transmitted and NOT ACK should ...
Page 200
... Hardware 0xF8 No relevant state information available; TWINT = “0” 0x00 Bus error due to an illegal START or STOP condition ATmega8535(L) 200 Figure 93. Formats and States in the Slave Transmitter Mode Reception of the own S SLA R slave address and one or more data bytes ...