ATMEGA8535L-8AUR Atmel, ATMEGA8535L-8AUR Datasheet

Page 1

... PDIP, 44-lead TQFP, 44-lead PLCC, and 44-pad QFN/MLF • Operating Voltages – 2.7 - 5.5V for ATmega8535L – 4.5 - 5.5V for ATmega8535 • Speed Grades – MHz for ATmega8535L – MHz for ATmega8535 ® 8-bit Microcontroller 8-bit Microcontroller with 8K Bytes ...

Page 2

Pin Configurations Disclaimer ATmega8535(L) 2 Figure 1. Pinout ATmega8535 (XCK/T0) PB0 (T1) PB1 (INT2/AIN0) PB2 (OC0/AIN1) PB3 (SS) PB4 (MOSI) PB5 (MISO) PB6 (SCK) PB7 (RXD) PD0 (TXD) PD1 (INT0) PD2 (INT1) PD3 (OC1B) PD4 (OC1A) PD5 (ICP1) PD6 (MOSI) ...

Page 3

Overview Block Diagram 2502K–AVR–10/06 The ATmega8535 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing instructions in a single clock cycle, the ATmega8535 achieves throughputs approaching 1 MIPS per MHz allowing the system designer ...

Page 4

... Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega8535 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications ...

Page 5

Pin Descriptions V CC GND Port A (PA7..PA0) Port B (PB7..PB0) Port C (PC7..PC0) Port D (PD7..PD0) RESET XTAL1 XTAL2 AVCC AREF 2502K–AVR–10/06 Digital supply voltage. Ground. Port A serves as the analog inputs to the A/D Converter. Port A ...

Page 6

... Resources ATmega8535( comprehensive set of development tools, application notes and datasheets are avail- able for download on http://www.atmel.com/avr. 2502K–AVR–10/06 ...

Page 7

About Code Examples 2502K–AVR–10/06 This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all ...

Page 8

AVR CPU Core Introduction Architectural Overview ATmega8535(L) 8 This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform ...

Page 9

ALU – Arithmetic Logic Unit 2502K–AVR–10/06 Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used ...

Page 10

Status Register ATmega8535(L) 10 The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is ...

Page 11

General Purpose Register File 2502K–AVR–10/06 The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: • One 8-bit output ...

Page 12

The X-register, Y-register, and Z-register Stack Pointer ATmega8535(L) 12 The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the Data Space. The three indirect address registers X, ...

Page 13

Instruction Execution Timing Reset and Interrupt Handling 2502K–AVR–10/06 This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clk source for the chip. No internal clock division is used. Figure ...

Page 14

ATmega8535(L) 14 also be moved to the start of the Boot Flash section by programming the BOOTRST Fuse, see “Boot Loader Support – Read-While-Write Self-Programming” on page 224. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and ...

Page 15

Interrupt Response Time 2502K–AVR–10/06 When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example. Assembly Code Example sei ; set global interrupt enable sleep ; enter ...

Page 16

AVR ATmega8535 Memories In-System Reprogrammable Flash Program Memory ATmega8535(L) 16 This section describes the different memories in the ATmega8535. The AVR architec- ture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega8535 ...

Page 17

SRAM Data Memory 2502K–AVR–10/06 Figure 9 shows how the ATmega8535 SRAM Memory is organized. The 608 Data Memory locations address the Register File, the I/O Memory, and the internal data SRAM. The first 96 locations address the Register File and ...

Page 18

Data Memory Access Times EEPROM Data Memory EEPROM Read/Write Access ATmega8535(L) 18 This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk 10. Figure 10. On-chip Data SRAM ...

Page 19

The EEPROM Address Register – EEARH and EEARL The EEPROM Data Register – EEDR The EEPROM Control Register – EECR 2502K–AVR–10/06 Bit – – – EEAR7 EEAR6 EEAR5 Read/Write R/W R/W ...

Page 20

ATmega8535(L) 20 value into the EEPROM. The EEMWE bit must be written to one before a logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order ...

Page 21

The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (e.g., by disabling inter- rupts globally) so that no interrupts will occur during execution of these ...

Page 22

EEPROM Write During Power- down Sleep Mode Preventing EEPROM Corruption ATmega8535(L) 22 The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution ...

Page 23

I/O Memory 2502K–AVR–10/ ...

Page 24

System Clock and Clock Options Clock Systems and their Distribution CPU Clock – clk CPU I/O Clock – clk I/O Flash Clock – clk FLASH ATmega8535(L) 24 Figure 11 presents the principal clock systems in the AVR and their distribution. ...

Page 25

Asynchronous Timer Clock – clk ASY ADC Clock – clk ADC Clock Sources Default Clock Source Crystal Oscillator 2502K–AVR–10/06 The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly from an external 32 kHz clock crystal. The dedicated ...

Page 26

ATmega8535(L) 26 This mode has a limited frequency range and it can not be used to drive other clock buffers. For resonators, the maximum frequency is 8 MHz with CKOPT unprogrammed and 16 MHz with CKOPT programmed. C1 and C2 ...

Page 27

The CKSEL0 fuse together with the SUT1..0 Fuses select the start-up times as shown in Table 5. Table 5. Start-up Times for the Crystal Oscillator Clock Selection Start-up Time from Power-down and CKSEL0 SUT1..0 Power-save 0 00 258 CK ...

Page 28

Low-frequency Crystal Oscillator External RC Oscillator ATmega8535( use a 32.768 kHz watch crystal as the clock source for the device, the Low-fre- quency Crystal Oscillator must be selected by setting the CKSEL Fuses to “1001”. The crystal should ...

Page 29

... At 5V, 25°C and 1.0 MHz Oscillator frequency selected, this calibration gives a fre- quency within ± the nominal frequency. Using run-time calibration methods as described in application notes available at www.atmel.com/avr it is possible to achieve ±1% accuracy at any given V and Temperature. When this Oscillator is used as the ...

Page 30

Oscillator Calibration Register – OSCCAL ATmega8535(L) 30 Table 10. Start-up Times for the Internal Calibrated RC Oscillator Clock Selection Start-up Time from Power- SUT1..0 down and Power-save ( Note: 1. ...

Page 31

External Clock Timer/Counter Oscillator 2502K–AVR–10/06 To drive the device from an external clock source, XTAL1 should be driven as shown in Figure 14. To run the device on an external clock, the CKSEL Fuses must be pro- grammed to “0000”. ...

Page 32

Power Management and Sleep Modes MCU Control Register – MCUCR ATmega8535(L) 32 Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the ...

Page 33

Idle Mode ADC Noise Reduction Mode Power-down Mode Power-save Mode 2502K–AVR–10/06 When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing SPI, USART, Analog Comparator, ADC, Two- wire ...

Page 34

Standby Mode Extended Standby Mode Table 14. Active Clock Domains and Wake-up Sources in the Different Sleep Modes. Active Clock domains Sleep Mode clk clk clk CPU FLASH IO Idle X ADC Noise Reduction Power- down Power- save (1) Standby ...

Page 35

Minimizing Power Consumption Analog-to-Digital Converter Analog Comparator Brown-out Detector Internal Voltage Reference Watchdog Timer Port Pins 2502K–AVR–10/06 There are several issues to consider when trying to minimize the power consumption in an AVR controlled system. In general, sleep modes should ...

Page 36

System Control and Reset Resetting the AVR Reset Sources ATmega8535(L) 36 During Reset, all I/O Registers are set to their initial values, and the program starts exe- cution from the Reset Vector. The instruction placed at the Reset Vector must ...

Page 37

Figure 15. Reset Logic Power-on Reset Circuit Brown-out BODEN Reset Circuit BODLEVEL Pull-up Resistor Spike Reset Circuit Filter Watchdog Watchdog Oscillator Generator CKSEL[3:0] SUT[1:0] Table 15. Reset Characteristics Symbol Parameter Power-on Reset Threshold Voltage (rising) V POT Power-on Reset ...

Page 38

... This guarantees that a Brown-out Reset will occur before voltage where correct operation of the microcontroller is no longer guaranteed. The test is performed using BODLEVEL = 1 for ATmega8535L and BODLEVEL = 0 for ATmega8535. BODLEVEL = 1 is not applicable for ATmega8535. A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detec- tion level is defined in Table 15 ...

Page 39

External Reset Brown-out Detection 2502K–AVR–10/06 An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see Table 15) will generate a reset, even if the clock is not running. ...

Page 40

Watchdog Reset MCU Control and Status Register – MCUCSR ATmega8535(L) 40 When the Watchdog times out, it will generate a short reset pulse of one CK cycle dura- tion. On the falling edge of this pulse, the delay timer starts ...

Page 41

Internal Voltage Reference Voltage Reference Enable Signals and Start-up Time Watchdog Timer 2502K–AVR–10/06 ATmega8535 features an internal bandgap reference. This reference is used for Brown- out Detection, and it can be used as an input to the Analog Comparator or ...

Page 42

Watchdog Timer Control Register – WDTCR ATmega8535(L) 42 Table 17. WDT Configuration as a Function of the Fuse Settings of S8538C and WDTON S8535C WDTON Unprogrammed Unprogrammed Unprogrammed Programmed Programmed Unprogrammed Programmed Programmed Figure 21. Watchdog Timer WATCHDOG OSCILLATOR Bit ...

Page 43

WDCE bit has logic level one. To disable an enabled Watchdog Timer, the follow- ing procedure must be followed the same operation, write a logic one to WDCE and WDE. A logic one must be ...

Page 44

ATmega8535(L) 44 The following code example shows one assembly and one C function for turning off the WDT. The example assumes that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these ...

Page 45

Timed Sequences for Changing the Configuration of the Watchdog Timer Safety Level 0 Safety Level 1 Safety Level 2 2502K–AVR–10/06 The sequence for changing the Watchdog Timer configuration differs slightly between the three safety levels. Separate procedures are described for ...

Page 46

Interrupts Interrupt Vectors in ATmega8535 ATmega8535(L) 46 This section describes the specifics of the interrupt handling as performed in ATmega8535. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 13. Table 19. ...

Page 47

Table 20. Reset and Interrupt Vectors Placement (1) BOOTRST IVSEL Reset Address 1 0 0x0000 1 1 0x0000 0 0 Boot Reset Address 0 1 Boot Reset Address Note: 1. The Boot Reset Address is shown in Table 93 ...

Page 48

ATmega8535(L) 48 AddressLabels Code 0x000 RESET: ldi r16,high(RAMEND) ; Main program start 0x001 out SPH,r16 0x002 ldi r16,low(RAMEND) 0x003 out SPL,r16 0x004 sei 0x005 <instr> xxx ; .org 0xC01 0xC01 rjmp EXT_INT0 0xC02 rjmp EXT_INT1 ... .... .. 0xC14 rjmp ...

Page 49

Moving Interrupts Between Application and Boot Space General Interrupt Control Register – GICR 2502K–AVR–10/06 The General Interrupt Control Register controls the placement of the Interrupt Vector table. Bit INT1 INT0 INT2 Read/Write R/W R/W R/W Initial Value ...

Page 50

ATmega8535(L) 50 Assembly Code Example Move_interrupts: ; Enable change of interrupt vectors ldi r16, (1<<IVCE) out GICR, r16 ; Move interrupts to boot Flash section ldi r16, (1<<IVSEL) out GICR, r16 ret C Code Example void Move_interrupts(void Enable ...

Page 51

I/O-Ports Introduction 2502K–AVR–10/06 All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without uninten- tionally changing the direction of any other pin with ...

Page 52

Ports as General Digital I/O Configuring the Pin ATmega8535(L) 52 The ports are bi-directional I/O ports with optional internal pull-ups. Figure 23 shows a functional description of one I/O-port pin, here generically called Pxn. (1) Figure 23. General Digital I/O ...

Page 53

Reading the Pin Value 2502K–AVR–10/06 0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully acceptable high-impedant environment will not notice the dif- ference between a strong high driver and a ...

Page 54

ATmega8535(L) 54 ceeding positive clock edge. As indicated by the two arrows t signal transition on the pin will be delayed between ½ and 1½ system clock period depending upon the time of assertion. When reading back a software assigned ...

Page 55

Digital Input Enable and Sleep Modes 2502K–AVR–10/06 The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from input with pull-ups assigned ...

Page 56

Unconnected pins ATmega8535(L) 56 when resuming from the above mentioned sleep modes, as the clamping in these sleep modes produces the requested logic change. If some pins are unused recommended to ensure that these pins have a defined ...

Page 57

Alternate Port Functions 2502K–AVR–10/06 Most port pins have alternate functions in addition to being general digital I/Os. Figure 26 shows how the port pin control signals from the simplified Figure 23 can be overrid- den by alternate functions. The overriding ...

Page 58

ATmega8535(L) 58 Table 22 summarizes the function of the overriding signals. The pin and port indexes from Figure 26 are not shown in the succeeding tables. The overriding signals are gen- erated internally in the modules having the alternate function. ...

Page 59

Special Function IO Register – SFIOR Alternate Functions of Port A 2502K–AVR–10/06 Bit ADTS2 ADTS1 ADTS0 Read/Write R/W R/W R/W Initial Value • Bit 2 – PUD: Pull-up disable When this bit is written ...

Page 60

Alternate Functions Of Port B ATmega8535(L) 60 Table 25. Overriding Signals for Alternate Functions in PA3..PA0 Signal Name PA3/ADC3 PUOE 0 PUOV 0 DDOE 0 DDOV 0 PVOE 0 PVOV 0 DIEOE 0 DIEOV 0 DI – AIO ADC3 INPUT ...

Page 61

MOSI – Port B, Bit 5 MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as a Slave, this pin is configured as an input regardless of the setting of DDB5. ...

Page 62

Alternate Functions of Port C ATmega8535(L) 62 Table 27. Overriding Signals for Alternate Functions in PB7..PB4 Signal Name PB7/SCK PB6/MISO PUOE SPE • MSTR SPE • MSTR PUOV PORTB7 • PUD PORTB6 • PUD DDOE SPE • MSTR SPE • ...

Page 63

TOSC2, Timer Oscillator pin 2: When the AS2 bit in ASSR is set (one) to enable asyn- chronous clocking of Timer/Counter2, pin PC7 is disconnected from the port, and becomes the inverting output of the Oscillator amplifier. In this ...

Page 64

Alternate Functions of Port D ATmega8535(L) 64 Table 31. Overriding Signals for Alternate Functions in PC1..PC0 Signal Name PC1/SDA PUOE TWEN PUOV PORTC1 • PUD DDOE TWEN DDOV SDA_OUT PVOE TWEN PVOV 0 DIEOE 0 DIEOV 0 DI – AIO ...

Page 65

The OC1A pin is also the output pin for the PWM mode timer function. • OC1B – Port D, Bit 4 OC1B, Output Compare Match B output: The PD4 pin can serve ...

Page 66

Register Description for I/O-Ports Port A Data Register – PORTA Port A Data Direction Register – DDRA Port A Input Pins Address – PINA Port B Data Register – PORTB Port B Data Direction Register – DDRB ATmega8535(L) 66 Table ...

Page 67

Port B Input Pins Address – PINB Port C Data Register – PORTC Port C Data Direction Register – DDRC Port C Input Pins Address – PINC Port D Data Register – PORTD Port D Data Direction Register – DDRD ...

Page 68

External Interrupts MCU Control Register – MCUCR ATmega8535(L) 68 The External Interrupts are triggered by the INT0, INT1, and INT2 pins. Observe that, if enabled, the interrupts will trigger even if the INT0..2 pins are configured as outputs. This feature ...

Page 69

MCU Control and Status Register – MCUCSR General Interrupt Control Register – GICR 2502K–AVR–10/06 The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set. The level and edges ...

Page 70

General Interrupt Flag Register – GIFR ATmega8535(L) 70 The corresponding interrupt of External Interrupt Request 1 is executed from the INT1 Interrupt Vector. • Bit 6 – INT0: External Interrupt Request 0 Enable When the INT0 bit is set (one) ...

Page 71

Timer/Counter0 with PWM Overview Registers 2502K–AVR–10/06 Timer/Counter0 is a general purpose, single channel, 8-bit Timer/Counter module. The main features are: • Single Channel Counter • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse Width Modulator ...

Page 72

Definitions Timer/Counter Clock Sources Counter Unit ATmega8535(L) 72 The double buffered Output Compare Register (OCR0) is compared with the Timer/Counter value at all times. The result of the compare can be used by the Wave- form Generator to generate a ...

Page 73

Output Compare Unit 2502K–AVR–10/06 top Signalize that TCNT0 has reached maximum value. bottom Signalize that TCNT0 has reached minimum value (zero). Depending of the mode of operation used, the counter is cleared, incremented, or dec- remented at each timer clock ...

Page 74

Force Output Compare Compare Match Blocking by TCNT0 Write Using the Output Compare Unit ATmega8535(L) 74 The OCR0 Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare ...

Page 75

Compare Match Output Unit Compare Output Mode and Waveform Generation 2502K–AVR–10/06 The Compare Output mode (COM01:0) bits have two functions. The Waveform Genera- tor uses the COM01:0 bits for defining the Output Compare (OC0) state at the next Compare Match. ...

Page 76

Modes of Operation Normal Mode Clear Timer on Compare Match (CTC) Mode ATmega8535(L) 76 The mode of operation, i.e., the behavior of the Timer/Counter and the output compare pins, is defined by the combination of the Waveform Generation mode (WGM01:0) ...

Page 77

Fast PWM Mode 2502K–AVR–10/06 when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to OCR0 is ...

Page 78

ATmega8535(L) 78 Figure 32. Fast PWM Mode, Timing Diagram TCNTn OCn OCn Period The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches MAX. If the interrupt is enabled, the interrupt handler routine can be ...

Page 79

Phase Correct PWM Mode 2502K–AVR–10/06 The phase correct PWM mode (WGM01 provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual- slope operation. The counter counts repeatedly from ...

Page 80

Timer/Counter Timing Diagrams ATmega8535(L) 80 OCR0 and TCNT0 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: f OCnPCPWM The “N” variable represents the prescale factor (1, ...

Page 81

Figure 35. Timer/Counter Timing Diagram, with Prescaler (f clk I/O clk Tn (clk /8) I/O TCNTn MAX - 1 TOVn Figure 36 shows the setting of OCF0 in all modes except CTC mode. Figure 36. Timer/Counter Timing Diagram, Setting ...

Page 82

ATmega8535(L) 82 Figure 37. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with Prescaler (f /8) clk_I/O clk I/O clk Tn (clk /8) I/O TCNTn TOP - 1 (CTC) OCRn OCFn TOP BOTTOM TOP 2502K–AVR–10/06 BOTTOM + 1 ...

Page 83

Timer/Counter Register Description Timer/Counter Control Register – TCCR0 2502K–AVR–10/06 Bit FOC0 WGM00 COM01 Read/Write W R/W R/W Initial Value • Bit 7 – FOC0: Force Output Compare The FOC0 bit is only active ...

Page 84

ATmega8535(L) 84 When OC0 is connected to the pin, the function of the COM01:0 bits depends on the WGM01:0 bit setting. Table 40 shows the COM01:0 bit functionality when the WGM01:0 bits are set to a normal or CTC mode ...

Page 85

Timer/Counter Register – TCNT0 Output Compare Register – OCR0 Timer/Counter Interrupt Mask Register – TIMSK 2502K–AVR–10/06 • Bit 2:0 – CS02:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter. Table 43. ...

Page 86

Timer/Counter Interrupt Flag Register – TIFR ATmega8535(L) 86 • Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable When the TOIE0 bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is ...

Page 87

Timer/Counter0 and Timer/Counter1 Prescalers Internal Clock Source Prescaler Reset External Clock Source 2502K–AVR–10/06 Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counter1 and Timer/Counter0. The Timer/Counter ...

Page 88

Special Function IO Register – SFIOR ATmega8535(L) 88 Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the ...

Page 89

Timer/Counter1 Overview 2502K–AVR–10/06 The 16-bit Timer/Counter unit allows accurate program execution timing (event man- agement), wave generation, and signal timing measurement. The main features are: • True 16-bit Design (i.e., Allows 16-bit PWM) • Two Independent Output Compare Units ...

Page 90

Registers ATmega8535(L) 90 Figure 40. 16-bit Timer/Counter Block Diagram Count Clear Control Logic Direction Timer/Counter TCNTn = OCRnA = OCRnB ICRn TCCRnA Note: 1. Refer to Figure 1 on page 2, Table 26 on page 60, and Table 32 on ...

Page 91

Definitions Compatibility 2502K–AVR–10/06 Waveform Generator to generate a PWM or variable frequency output on the Output Compare Pin (OC1A/B). See “Output Compare Units” on page 98. The Compare Match event will also set the Compare Match Flag (OCF1A/B) which can ...

Page 92

Accessing 16-bit Registers ATmega8535(L) 92 The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations. Each ...

Page 93

The following code examples show how atomic read of the TCNT1 Register contents. Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle. (1) Assembly Code Example TIM16_ReadTCNT1: ; Save ...

Page 94

Re-using the Temporary High Byte Register ATmega8535(L) 94 The following code examples show how atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle. ...

Page 95

Timer/Counter Clock Sources Counter Unit 2502K–AVR–10/06 The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the Clock Select logic which is controlled by the Clock Select (CS12:0) bits located in ...

Page 96

Input Capture Unit ATmega8535(L) 96 TCCR1B). There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare outputs OC1x. For more details about advanced counting sequences and waveform generation, see “Modes of ...

Page 97

Input Capture Trigger Source Noise Canceler Using the Input Capture Unit 2502K–AVR–10/06 byte is copied into the high byte temporary register (TEMP). When the CPU reads the ICR1H I/O location it will access the TEMP Register. The ICR1 Register can ...

Page 98

Output Compare Units ATmega8535(L) 98 measuring frequency only, the clearing of the ICF1 Flag is not required (if an interrupt handler is used). The 16-bit comparator continuously compares TCNT1 with the Output Compare Regis- ter (OCR1x). If TCNT equals OCR1x ...

Page 99

Force Output Compare Compare Match Blocking by TCNT1 Write Using the Output Compare Unit 2502K–AVR–10/06 sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCR1x Register access may seem complex, but this ...

Page 100

Compare Match Output Unit Compare Output Mode and Waveform Generation ATmega8535(L) 100 The Compare Output Mode (COM1x1:0) bits have two functions. The waveform genera- tor uses the COM1x1:0 bits for defining the Output Compare (OC1x) state at the next Compare ...

Page 101

Modes of Operation Normal Mode Clear Timer on Compare Match (CTC) Mode 2502K–AVR–10/06 A change of the COM1x1:0 bits state will have effect at the first Compare Match after the bits are written. For non-PWM modes, the action can be ...

Page 102

Fast PWM Mode ATmega8535(L) 102 Figure 45. CTC Mode, Timing Diagram TCNTn OCnA (Toggle) Period interrupt can be generated each time the counter value reaches the TOP value by either using the OCF1A or ICF1 Flag according ...

Page 103

High frequency allows physically small sized external components (coils, capacitors), hence reducing total system cost. The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution ...

Page 104

Phase Correct PWM Mode ATmega8535(L) 104 The counter will then have to count to the MAX value (0xFFFF) and wrap around start- ing at 0x0000 before the Compare Match can occur. The OCR1A Register however, is double buffered. This feature ...

Page 105

OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution can be calculated in bits by using the following equation: R PCPWM In phase correct PWM mode, the counter is ...

Page 106

Phase and Frequency Correct PWM Mode ATmega8535(L) 106 ing slope is determined by the previous TOP value, while the length of the rising slope is determined by the new TOP value. When these two values differ the two slopes of ...

Page 107

In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the value in ICR1 (WGM13:0 = 8), or the value in OCR1A (WGM13:0 = 9). The counter has then reached the TOP ...

Page 108

Timer/Counter Timing Diagrams ATmega8535(L) 108 In phase and frequency correct PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins. Setting the COM1x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output ...

Page 109

Figure 50. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (f clk I/O clk Tn (clk /8) I/O TCNTn OCRnx - 1 OCRnx OCFnx Figure 51 shows the count sequence close to TOP in various modes. When using phase ...

Page 110

Timer/Counter Register Description Timer/Counter1 Control Register A – TCCR1A ATmega8535(L) 110 Figure 52. Timer/Counter Timing Diagram, with Prescaler (f clk I/O clk Tn (clk /8) I/O TCNTn TOP - 1 (CTC and FPWM) TCNTn TOP - 1 (PC and ...

Page 111

Table 46 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the fast PWM mode. Table 46. Compare Output Mode, Fast PWM COM1A1/ COM1A0/ COM1B1 COM1B0 Description 0 0 Normal port operation, OC1A/OC1B disconnected ...

Page 112

Table 48. Waveform Generation Mode Bit Description WGM12 WGM11 Mode WGM13 (CTC1) (PWM11 ...

Page 113

Timer/Counter1 Control Register B – TCCR1B 2502K–AVR–10/06 Bit ICNC1 ICES1 – Read/Write R/W R/W R Initial Value • Bit 7 – ICNC1: Input Capture Noise Canceler Setting this bit (to one) activates the Input ...

Page 114

Timer/Counter1 – TCNT1H and TCNT1L Output Compare Register 1 A – OCR1AH and OCR1AL Output Compare Register 1 B – OCR1BH and OCR1BL Input Capture Register 1 – ICR1H and ICR1L ATmega8535(L) 114 Bit Read/Write R/W R/W ...

Page 115

Timer/Counter Interrupt Mask (1) Register – TIMSK 2502K–AVR–10/06 Bit OCIE2 TOIE2 TICIE1 Read/Write R/W R/W R/W Initial Value Note: 1. This register contains interrupt control bits for several Timer/Counters, but only Timer1 bits are ...

Page 116

Timer/Counter Interrupt Flag (1) Register – TIFR ATmega8535(L) 116 Bit OCF2 TOV2 ICF1 Read/Write R/W R/W R/W Initial Value Note: 1. This register contains flag bits for several Timer/Counters, but only Timer1 bits are ...

Page 117

Timer/Counter2 with PWM and Asynchronous Operation Overview 2502K–AVR–10/06 Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. The main features are: • Single Channel Counter • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse ...

Page 118

Registers Definitions Timer/Counter Clock Sources ATmega8535(L) 118 The Timer/Counter (TCNT2) and Output Compare Register (OCR2) are 8-bit registers. Interrupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR). All interrupts are individually masked with ...

Page 119

Counter Unit Output Compare Unit 2502K–AVR–10/06 The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 54 shows a block diagram of the counter and its surrounding environment. Figure 54. Counter Unit Block Diagram DATA BUS ...

Page 120

Force Output Compare Compare Match Blocking by TCNT2 Write Using the Output Compare Unit ATmega8535(L) 120 Figure 55. Output Compare Unit, Block Diagram OCRn top bottom FOCn The OCR2 Register is double buffered when using any of the pulse width ...

Page 121

Compare Match Output Unit Compare Output Mode and Waveform Generation 2502K–AVR–10/06 Be aware that the COM21:0 bits are not double buffered together with the compare value. Changing the COM21:0 bits will take effect immediately. The Compare Output mode (COM21:0) bits ...

Page 122

Modes of Operation Normal Mode Clear Timer on Compare Match (CTC) Mode ATmega8535(L) 122 A change of the COM21:0 bits state will take effect at the first Compare Match after the bits are written. For non-PWM modes, the action can ...

Page 123

Fast PWM Mode 2502K–AVR–10/06 An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2 Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. ...

Page 124

ATmega8535(L) 124 Figure 58. Fast PWM Mode, Timing Diagram TCNTn OCn OCn Period The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches MAX. If the interrupt is enabled, the interrupt handler routine can be ...

Page 125

Phase Correct PWM Mode 2502K–AVR–10/06 The Phase Correct PWM mode (WGM21 provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual- slope operation. The counter counts repeatedly from ...

Page 126

Timer/Counter Timing Diagrams ATmega8535(L) 126 between OCR2 and TCNT2 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: f OCnPCPWM The “N” variable represents the prescale factor ...

Page 127

Figure 61. Timer/Counter Timing Diagram, with Prescaler (f clk I/O clk Tn (clk /8) I/O TCNTn MAX - 1 TOVn Figure 62 shows the setting of OCF2 in all modes except CTC mode. Figure 62. Timer/Counter Timing Diagram, Setting ...

Page 128

Timer/Counter Register Description Timer/Counter Control Register – TCCR2 ATmega8535(L) 128 Figure 63. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with Prescaler (f /8) clk_I/O clk I/O clk Tn (clk /8) I/O TCNTn TOP - 1 (CTC) OCRn ...

Page 129

Table 51. Waveform Generation Mode Bit Description WGM21 WGM20 Timer/Counter Mode Mode (CTC2) (PWM2) of Operation Normal PWM, Phase Correct CTC Fast PWM Note: 1. The CTC2 ...

Page 130

Timer/Counter Register – TCNT2 ATmega8535(L) 130 Table 54 shows the COM21:0 bit functionality when the WGM21:0 bits are set to phase correct PWM mode. Table 54. Compare Output Mode, Phase Correct PWM Mode COM21 COM20 Description 0 0 Normal port ...

Page 131

Output Compare Register – OCR2 Asynchronous Operation of the Timer/Counter Asynchronous Status Register – ASSR 2502K–AVR–10/06 Bit Read/Write R/W R/W R/W Initial Value The Output Compare Register contains an 8-bit value that is continuously ...

Page 132

Asynchronous Operation of Timer/Counter2 ATmega8535(L) 132 When Timer/Counter2 operates asynchronously, some considerations must be taken. • Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the timer registers TCNT2, OCR2, and TCCR2 might be corrupted. A safe procedure for ...

Page 133

Timer/Counter Interrupt Mask Register – TIMSK 2502K–AVR–10/06 down or Standby mode due to unstable clock signal upon start-up, no matter whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin. • Description of wake-up ...

Page 134

Timer/Counter Interrupt Flag Register – TIFR Timer/Counter Prescaler ATmega8535(L) 134 Bit OCF2 TOV2 ICF1 Read/Write R/W R/W R/W Initial Value • Bit 7 – OCF2: Output Compare Flag 2 The OCF2 bit is set ...

Page 135

Special Function IO Register – SFIOR 2502K–AVR–10/06 Bit ADTS2 ADTS1 ADTS0 Read/Write R/W R/W R/W Initial Value • Bit 1 – PSR2: Prescaler Reset Timer/Counter2 When this bit is written to one, the Timer/Counter2 ...

Page 136

Serial Peripheral Interface – SPI ATmega8535(L) 136 The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega8535 and peripheral devices or between several AVR devices. The ATmega8535 SPI includes the following features: • Full Duplex, Three-wire Synchronous ...

Page 137

SPI Data Register starts the SPI Clock Generator, and the hardware shifts the eight bits into the Slave. After shifting one byte, the SPI clock gener- ator stops, setting the end of Transmission ...

Page 138

ATmega8535(L) 138 (1) Table 56. SPI Pin Overrides Pin Direction, Master SPI MOSI User Defined MISO Input SCK User Defined SS User Defined Note: 1. See “Alternate Functions Of Port B” on page 60 for a detailed description of how ...

Page 139

SPI_MasterInit: ; Set MOSI and SCK output, all others input ldi r17,(1<<DD_MOSI)|(1<<DD_SCK) out DDR_SPI,r17 ; Enable SPI, Master, set clock rate fck/16 ldi r17,(1<<SPE)|(1<<MSTR)|(1<<SPR0) out SPCR,r17 ret SPI_MasterTransmit: ; Start transmission of data (r16) out SPDR,r16 Wait_Transmit: ; Wait ...

Page 140

ATmega8535(L) 140 The following code examples show how to initialize the SPI as a Slave and how to per- form a simple reception. (1) Assembly Code Example SPI_SlaveInit: ; Set MISO output, all others input ldi r17,(1<<DD_MISO) out DDR_SPI,r17 ; ...

Page 141

SS Pin Functionality Slave Mode Master Mode SPI Control Register – SPCR 2502K–AVR–10/06 When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO ...

Page 142

ATmega8535(L) 142 be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Master mode. • Bit 3 – CPOL: Clock Polarity When this bit is written to one, SCK is ...

Page 143

SPI Status Register – SPSR SPI Data Register – SPDR 2502K–AVR–10/06 Bit SPIF WCOL – Read/Write Initial Value • Bit 7 – SPIF: SPI Interrupt Flag When a serial transfer is ...

Page 144

Data Modes ATmega8535(L) 144 There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure 67 and Figure 68. ...

Page 145

USART Overview 2502K–AVR–10/06 The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART highly flexible serial communication device. The main features are: • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • ...

Page 146

AVR USART vs. AVR UART – Compatibility Clock Generation ATmega8535(L) 146 The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): Clock Generator, Transmitter and Receiver. Control registers are shared by ...

Page 147

Internal Clock Generation – The Baud Rate Generator 2502K–AVR–10/06 Figure 70. Clock Generation Logic, Block Diagram UBRR Prescaling Down-Counter OSC Sync Register xcki XCK xcko Pin DDR_XCK Signal description: txclk Transmitter clock (Internal Signal). rxclk Receiver base clock (Internal Signal). ...

Page 148

Double Speed Operation (U2X) External Clock ATmega8535(L) 148 Table 61. Equations for Calculating Baud Rate Register Setting Equation for Calculating Operating Mode Asynchronous Normal Mode (U2X = 0) BAUD Asynchronous Double Speed Mode (U2X = 1) BAUD Synchronous Master Mode ...

Page 149

Synchronous Clock Operation When Synchronous mode is used (UMSEL = 1), the XCK pin will be used as either clock Frame Formats 2502K–AVR–10/06 input (Slave) or clock output (Master). The dependency between the clock edges and data sampling or data ...

Page 150

Parity Bit Calculation USART Initialization ATmega8535(L) 150 Sp Stop bit, always high. IDLE No transfers on the communication line (RxD or TxD). An IDLE line must be high. The frame format used by the USART is set by the UCSZ2:0, ...

Page 151

The following simple USART initialization code examples show one assembly and one C function that are equal in functionality. The examples assume asynchronous opera- tion using polling (no interrupts enabled) and a fixed frame format. The baud rate is ...

Page 152

Data Transmission – The USART Transmitter Sending Frames with Data Bits ATmega8535(L) 152 The USART Transmitter is enabled by setting the Transmit Enable (TXEN) bit in the UCSRB Register. When the Transmitter is enabled, the normal port ...

Page 153

Sending Frames with 9 Data Bits Transmitter Flags and Interrupts 2502K–AVR–10/06 If 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8 bit in UCSRB before the low byte of the character is written ...

Page 154

Parity Generator Disabling the Transmitter ATmega8535(L) 154 interrupt-driven data transmission is used, the Data Register Empty interrupt routine must either write new data to UDR in order to clear UDRE or disable the Data Register Empty interrupt, otherwise a new ...

Page 155

Data Reception – The USART Receiver Receiving Frames with Data Bits 2502K–AVR–10/06 The USART Receiver is enabled by writing the Receive Enable (RXEN) bit in the UCSRB Register to one. When the Receiver is enabled, the normal ...

Page 156

Receiving Frames with 9 Data Bits ATmega8535(L) 156 If 9-bit characters are used (UCSZ=7) the ninth bit must be read from the RXB8 bit in UCSRB before reading the low bits from the UDR. This rule applies to the FE, ...

Page 157

Receive Compete Flag and Interrupt Receiver Error Flags Parity Checker 2502K–AVR–10/06 Note: 1. See “About Code Examples” on page 7. The receive function example reads all the I/O Registers into the Register File before any computation is done. This gives ...

Page 158

Disabling the Receiver Flushing the Receive Buffer Asynchronous Data Reception Asynchronous Clock Recovery ATmega8535(L) 158 stored in the receive buffer together with the received data and stop bits. The Parity Error (PE) Flag can then be read by software to ...

Page 159

Asynchronous Data Recovery 2502K–AVR–10/06 Figure 73. Start Bit Sampling RxD IDLE Sample (U2X = 0) Sample (U2X = 1) When the clock recovery logic detects a high (idle) to low (start) ...

Page 160

Asynchronous Operational Range ATmega8535(L) 160 Figure 75. Stop Bit Sampling and Next Start Bit Sampling RxD Sample (U2X = Sample (U2X = The same majority voting is done to the ...

Page 161

Table 62. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2X = (Data+Parity Bit) R (%) R slow 5 93.20 6 94.12 7 94.81 8 95.36 9 95.81 10 96.17 Table 63. Recommended Maximum ...

Page 162

Multi-processor Communication Mode Using MPCM ATmega8535(L) 162 Setting the Multi-processor Communication Mode (MPCM) bit in UCSRA enables a fil- tering function of incoming frames received by the USART Receiver. Frames that do not contain address information will be ignored and ...

Page 163

Accessing UBRRH/UCSRC Registers Write Access 2502K–AVR–10/06 The UBRRH Register shares the same I/O location as the UCSRC Register. Therefore some special consideration must be taken when accessing this I/O location. When doing a write access of this I/O location, the ...

Page 164

Read Access USART Register Description USART I/O Data Register – UDR ATmega8535(L) 164 Doing a read access to the UBRRH or the UCSRC Register is a more complex opera- tion. However, in most applications rarely necessary to read ...

Page 165

USART Control and Status Register A – UCSRA 2502K–AVR–10/06 For 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the Transmitter and set to zero by the Receiver. The transmit buffer can only be written when ...

Page 166

USART Control and Status Register B – UCSRB ATmega8535(L) 166 • Bit 1 – U2X: Double the USART Transmission Speed This bit only has effect for the asynchronous operation. Write this bit to zero when using synchronous operation. Writing this ...

Page 167

USART Control and Status (1) Register C – UCSRC 2502K–AVR–10/06 TXB8 is the ninth data bit in the character to be transmitted when operating with serial frames with nine data bits. Must be written before writing the low bits to ...

Page 168

ATmega8535(L) 168 • Bit 5:4 – UPM1:0: Parity Mode These bits enable and set type of parity generation and check. If enabled, the Transmit- ter will automatically generate and send the parity of the transmitted data bits within each frame. ...

Page 169

USART Baud Rate Registers – (1) UBRRL and UBRRH 2502K–AVR–10/06 This bit is used for Synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOL bit sets the relationship between data output change and data ...

Page 170

Examples of Baud Rate Setting Table 69. Examples of UBRR Settings for Commonly Used Oscillator Frequencies f = 1.0000 MHz osc Baud U2X = 0 U2X = 1 Rate (bps) UBRR Error UBRR 2400 25 0.2% 51 4800 12 0.2% ...

Page 171

Table 70. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued 3.6864 MHz osc Baud U2X = 0 Rate (bps) UBRR Error UBRR 2400 95 0.0% 191 4800 47 0.0% 95 9600 23 0.0% 47 14.4k 15 ...

Page 172

Table 71. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued 8.0000 MHz osc Baud U2X = 0 U2X = 1 Rate (bps) UBRR Error UBRR 2400 207 0.2% 416 4800 103 0.2% 207 9600 51 0.2% ...

Page 173

Table 72. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued 16.0000 MHz osc Baud U2X = 0 Rate (bps) UBRR Error UBRR 2400 416 -0.1% 832 4800 207 0.2% 416 9600 103 0.2% 207 14.4k 68 ...

Page 174

Two-wire Serial Interface Features Two-wire Serial Interface Bus Definition TWI Terminology ATmega8535(L) 174 • Simple yet Powerful and Flexible Communication Interface, only Two Bus Lines Needed • Both Master and Slave Operation Supported • Device can Operate as Transmitter or ...

Page 175

Electrical Interconnection Data Transfer and Frame Format Transferring Bits START and STOP Conditions 2502K–AVR–10/06 As depicted in Figure 76, both bus lines are connected to the positive supply voltage through pull-up resistors. The bus drivers of all TWI-compliant devices are ...

Page 176

Address Packet Format Data Packet Format ATmega8535(L) 176 Figure 78. START, REPEATED START, and STOP Conditions SDA SCL START All address packets transmitted on the TWI bus are nine bits long, consisting of seven address bits, one READ/WRITE control bit ...

Page 177

Combining Address and Data Packets into a Transmission Multi-master Bus Systems, Arbitration and Synchronization 2502K–AVR–10/06 Figure 80. Data Packet Format Data MSB Aggregate SDA SDA From Transmitter SDA From Receiver SCL From Master 1 2 SLA+R/W A transmission basically consists ...

Page 178

ATmega8535(L) 178 period equal to the one from the Master with the shortest high period. The low period of the combined clock is equal to the low period of the Master with the longest low period. Note that all masters ...

Page 179

Overview of the TWI Module SCL and SDA Pins 2502K–AVR–10/06 Note that arbitration is not allowed between: • A REPEATED START condition and a data bit • A STOP condition and a data bit • A REPEATED START and a ...

Page 180

Bit Rate Generator Unit Bus Interface Unit Address Match Unit Control Unit ATmega8535(L) 180 This unit controls the period of SCL when operating in a Master mode. The SCL period is controlled by settings in the TWI Bit Rate Register ...

Page 181

TWI Register Description TWI Bit Rate Register – TWBR TWI Control Register – TWCR 2502K–AVR–10/06 • After the TWI has transmitted a START/REPEATED START condition. • After the TWI has transmitted SLA+R/W. • After the TWI has transmitted an address ...

Page 182

ATmega8535(L) 182 By writing the TWEA bit to zero, the device can be virtually disconnected from the Two- wire Serial Bus temporarily. Address recognition can then be resumed by writing the TWEA bit to one again. • Bit 5 – ...

Page 183

TWI Status Register – TWSR TWI Data Register – TWDR TWI (Slave) Address Register – TWAR 2502K–AVR–10/06 Bit TWS7 TWS6 TWS5 Read/Write Initial Value • Bits 7..3 – TWS: TWI Status ...

Page 184

ATmega8535(L) 184 Read/Write R/W R/W R/W Initial Value The TWAR should be loaded with the 7-bit slave address (in the seven most significant bits of TWAR) to which the TWI will respond when programmed as a Slave ...

Page 185

Using the TWI Figure 85. Interfacing the Application to the TWI in a Typical Transmission 1. Application writes 3. Check TWSR to see if START was to TWCR to initiate sent. Application loads SLA+W into transmission of TWDR, and loads ...

Page 186

ATmega8535(L) 186 load SLA+W into TWDR. Remember that TWDR is used both for address and data. After TWDR has been loaded with the desired SLA+W, a specific value must be written to TWCR, instructing the TWI hardware to transmit the ...

Page 187

Assembly Code Example ldi r16, (1<<TWINT)|(1<<TWSTA)| 1 (1<<TWEN) out TWCR, r16 wait1 r16,TWCR sbrs r16,TWINT rjmp wait1 in r16,TWSR 3 andi r16, 0xF8 cpi r16, START brne ERROR ldi r16, SLA_W out TWDR, r16 ldi r16, (1<<TWINT) | ...

Page 188

Transmission Modes ATmega8535(L) 188 The TWI can operate in one of four major modes. These are named Master Transmitter (MT), Master Receiver (MR), Slave Transmitter (ST), and Slave Receiver (SR). Several of these modes can be used in the same ...

Page 189

Master Transmitter Mode 2502K–AVR–10/06 In the Master Transmitter mode, a number of data bytes are transmitted to a Slave Receiver (see Figure 86). In order to enter a Master mode, a START condition must be transmitted. The format of the ...

Page 190

Table 75. Status Codes for Master Transmitter Mode Status Code (TWSR) Status of the Two-wire Serial Prescaler Bits Bus and Two-wire Serial Inter- are 0 face Hardware 0x08 A START condition has been transmitted 0x10 A repeated START condition has ...

Page 191

Figure 87. Formats and States in the Master Transmitter Mode MT Successfull S SLA W transmission to a slave receiver $08 Next transfer started with a repeated start condition Not acknowledge received after the slave address Not acknowledge received ...

Page 192

Master Receiver Mode ATmega8535(L) 192 In the Master Receiver mode, a number of data bytes are received from a Slave Trans- mitter (see Figure 88). In order to enter a Master mode, a START condition must be transmitted. The format ...

Page 193

Table 76. Status Codes for Master Receiver Mode Status Code (TWSR) Status of the Two-wire Serial Prescaler Bits Bus and Two-wire Serial Inter- are 0 face Hardware 0x08 A START condition has been transmitted 0x10 A repeated START condition has ...

Page 194

Slave Receiver Mode ATmega8535(L) 194 Figure 89. Formats and States in the Master Receiver Mode MR Successfull S SLA R A reception from a slave receiver $08 $40 Next transfer started with a repeated start condition Not acknowledge A received ...

Page 195

To initiate the Slave Receiver mode, TWAR and TWCR must be initialized as follows: TWAR TWA6 TWA5 Value The upper seven bits are the address to which the Two-wire Serial Interface will respond when addressed by a Master. If ...

Page 196

Table 77. Status Codes for Slave Receiver Mode Status Code (TWSR) Prescaler Bits Status of the Two-wire Serial Bus are 0 and Two-wire Serial Interface Hardware 0x60 Own SLA+W has been received; ACK has been returned 0x68 Arbitration lost in ...

Page 197

Figure 91. Formats and States in the Slave Receiver Mode Reception of the own S SLA slave address and one or more data bytes. All are acknowledged Last data byte received is not acknowledged Arbitration lost as master and ...

Page 198

Slave Transmitter Mode ATmega8535(L) 198 In the Slave Transmitter mode, a number of data bytes are transmitted to a Master Receiver (see Figure 92). All the status codes mentioned in this section assume that the prescaler bits are zero or ...

Page 199

Table 78. Status Codes for Slave Transmitter Mode Status Code (TWSR) Status of the Two-wire Serial Bus Prescaler Bits and Two-wire Serial Interface are 0 Hardware 0xA8 Own SLA+R has been received; ACK has been returned 0xB0 Arbitration lost in ...

Page 200

Miscellaneous States Table 79. Miscellaneous States Status Code (TWSR) Status of the Two-wire Serial Prescaler Bits Bus and Two-wire Serial Inter- are 0 face Hardware 0xF8 No relevant state information available; TWINT = “0” 0x00 Bus error due to an ...