ATA6617-P3QW Atmel, ATA6617-P3QW Datasheet
ATA6617-P3QW
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ATA6617-P3QW Summary of contents
Page 1
... Package 1. Description ® Atmel ATA6616/ATA6617 is a System-in-Package (SiP) product, which is particu- larly suited for complete LIN-bus node applications. It supports highly integrated solutions for in-vehicle LIN networks. The first chip is the LIN-system-basis-chip (LIN-SBC) ATA6624, which has an integrated LIN transceiver regulator and a window watchdog. The second chip is an automotive microcontroller from Atmel ® ...
Page 2
... Atmel ATA6616/ATA6617 LIN System in Package Solution (SIP) 2.1 Pinning Atmel ATA6616/ATA6617 Figure 2-1. Pinning QFN38 Table 2-1. Pin Description Pin Symbol 1 PB2 2 PB1 3 PB0 4 PA0 5 PA1 6 PA2 (1) 7 RXD (1) 8 INH (1) 9 TXD (1) 10 NRES (1) 11 WD_OSC ( (1) 13 MODE (1) 14 KL_15 ...
Page 3
... AVR supply voltage System ground Ground (optional) Ground (optional) Port B 3 I/O line (PCINT11/OC1BV) Heat slug is connected to GND ® ATA6624 Symbol case R thjc R thja Atmel ATA6616/ATA6617 Min. Typ. Max. ±3 ±1 ±150 –55 +150 –40 +125 6 30 150 165 170 150 ...
Page 4
... The LIN-SBC is designed to handle the low-speed data communication in vehicles, e.g., in convenience electronics. Improved slope control at the LIN-driver ensures secure data com- munication up to 20kBaud. Sleep Mode and Silent Mode guarantee very low current consumption. Atmel ATA6616/ATA6617 27V S = 5.0V ±2% ...
Page 5
... Receiver - + Wake-up Bus Timer Slew Rate Control Control Unit Mode Select Internal Testing Watchdog Unit PVCC MODE TM NTRIG Atmel ATA6616/ATA6617 Normal Mode RF Filter Short Circuit and Overtemperature Protection Normal/Silent/ Fail-safe Mode 3.3/5V /50 mA/±2% Undervoltage Reset OUT Adjustable Watchdog ...
Page 6
... LIN output transistor is turned off, and the bus is in recessive state. During Fail-safe Mode, this pin is used as output current-limited to < 8mA. and is latched to low if the last wake-up event was from pin WAKE or KL_15. Atmel ATA6616/ATA6617 27V. An undervoltage detection is implemented to dis- ...
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... To debug the software of the connected microcontroller, connect the MODE pin to VCC and the watchdog is switched off. 3.3.13 TM Input Pin The TM pin is used for final production measurements at Atmel. In normal application, it must always be connected to GND. 9132D–AUTO–12/10 Atmel ATA6616/ATA6617 typ. 57µA. The VS > 6ms, DOM = 0V). S ...
Page 8
... Wake-up Events from Sleep or Silent Mode • LIN-bus • WAKE pin • EN pin • KL_15 Atmel ATA6616/ATA6617 possible to switch the IC into Sleep or Silent Mode. Connect the Batt . To protect this pin against voltage transients, a serial resistor and a KL_15 and, therefore, the sensitivity against transients on the ignition Kl.15. ...
Page 9
... LIN specification LIN 2.x. The voltage regulator is active and can source up to 50mA. The undervoltage detection is activated. The watchdog needs a trigger signal from NTRIG to avoid resets at NRES. If NRES is switched to low, the IC changes its state to Fail-safe Mode. 9132D–AUTO–12/10 Atmel ATA6616/ATA6617 Unpowered Mode ...
Page 10
... A falling edge at the LIN pin followed by a dominant bus level maintained for a certain time period (t remote wake-up request. The device switches from Silent Mode to Fail-safe Mode. The remote wake-up request is indicated by a low level at the RXD pin to interrupt the microcon- troller (see Atmel ATA6616/ATA6617 10 Switch to Silent Mode Normal Mode EN ...
Page 11
... High TXD Watchdog off Silent mode 3.3V/5V/50mA EN Undervoltage detection active from V is typically 10µA. VSsleep Batt Atmel ATA6616/ATA6617 Fail-safe mode Low Start watchdog lead time t d Fail safe mode 3.3V/5V/50mA Normal mode (Figure 3-5 on page 12). In order to avoid any Normal mode ...
Page 12
... The VCC output voltage reaches its nominal value after t VCC capacitor and the load. The NRES is low for the reset time delay t possible. Atmel ATA6616/ATA6617 12 ) and a following rising edge at pin LIN results in a remote wake-up request. The bus Switch to Sleep Mode ...
Page 13
... Watchdog 9132D–AUTO–12/10 LIN Wake-up from Sleep Mode Bus wake-up filtering time t bus Low or floating Off state EN Floating Watchdog off Atmel ATA6616/ATA6617 Fail-safe Mode Low On state Regulator wake-up time Reset time Microcontroller start-up time delay Start watchdog lead time t d Normal Mode ...
Page 14
... RXD pin) as well as the wake-up source flag (signalled on the TXD pin) is immediately reset if the microcontroller sets the EN pin to high (see 3-3 on page 10 source flag is stored and signalled in Fail-safe Mode at the TXD pin. Atmel ATA6616/ATA6617 14 ) and a rising edge at pin LIN result in a remote wake-up request. The device BUS ) results in a local wake-up request ...
Page 15
... C > 1.8µF and a ceramic capacitor with C = 100nF. The values of these capacitors can be var- ied by the customer, depending on the application. The main power dissipation of the IC is created from the VCC output current I needed for the application. In ATA6616/ATA6617 is shown. 9132D–AUTO–12/10 , the output limits the output current to I Battery is disconnected ...
Page 16
... Figure 3-7. Figure 3-8. For programming purposes of the microcontroller it is potentially necessary to supply the V output via an external power supply while the V This behavior is no problem for the system basis chip. Atmel ATA6616/ATA6617 16 VCC Voltage Regulator: Ramp-up and Undervoltage Detection VS 12V 5.5V/3.8V VCC 5V/3 ...
Page 17
... A triggering sig Atmel ATA6616/ATA6617 . The trigger signal must exceed a minimum time adjustable via the external osc . After wake up from Sleep or Silent Mode, the d = 51k ±1%, the typical parameters of the ...
Page 18
... The ideal watchdog time 1,min t 2,min t wdmax t wdmin t = 29.3ms ±4.5ms (±15 microcontroller with an oscillator tolerance of ±15% is sufficient to correctly supply the trig- ger inputs. Table 3-2. R WD_OSC 120 Atmel ATA6616/ATA6617 18 = 51k WD_OSC t = 155ms 20.6ms > 200ns trig = 51 k WD_OSC is between the maximum 0 16.5ms 1.2 1 1,max = 0 ...
Page 19
... ESD according to IBEE LIN EMC Test Spec. 1.0 following IEC 61000-4-2 - Pin VS, LIN to GND - Pin WAKE (33k serial resistor) to GND ESD HBM following STM5.1 with 1.5k 100pF - Pin VS, LIN, WAKE to GND Junction temperature Storage temperature 9132D–AUTO–12/10 Atmel ATA6616/ATA6617 Symbol Min. Typ. V –0 ...
Page 20
... V current Fail-safe Mode Low-level output sink V 3.5 current at local wake-up V request V *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter Atmel ATA6616/ATA6617 20 < 150°C, unless otherwise specified. All values refer to GND pins j Pin VS > V – 0.5V VS LIN S < 14V (T = 25° ...
Page 21
... INH RXD LIN = 7V VS LIN = 500 load = 18V VS LIN = 500 load = 7.0V VS LIN = 1000 load = 18V VS LIN = 1000 load LIN slave LIN = 10mA Atmel ATA6616/ATA6617 Symbol Min. Typ. Max. V –0.3 +0.8 ENL ENH 0. 125 200 EN I – –0.3 +0.8 NTRIGL V CC ...
Page 22
... EN pin Time delay for mode change from Normal 10.3 V Mode to Sleep Mode via EN pin *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter Atmel ATA6616/ATA6617 22 < 150°C, unless otherwise specified. All values refer to GND pins j Pin LIN LIN I ...
Page 23
... S RXD = t – t rx_pdr rx_pdf 5. 1mA NRES = 250µA CC NRES = 0V CC 5.5V S NRES = 20pF NRES 5.5V S NRES = 20pF NRES Atmel ATA6616/ATA6617 Symbol Min. Typ. Max dom s_n D1 0.396 D2 0.581 D3 0.417 D4 0.590 t SLOPE_fall 3.5 22.5 t SLOPE_rise t 6 rx_pd t – ...
Page 24
... High-level leakage V 16.4 current V Time of low pulse for 16.5 V wake-up via WAKE pin *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter Atmel ATA6616/ATA6617 24 < 150°C, unless otherwise specified. All values refer to GND pins j Pin = –200µA WD_ 4V OSC VS ...
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... VCC VCC = 10µF VCC VCC = 14V –15mA S VCC > 5.5V VCC S VCC VCC > 5.5V S VCC > 5. 2.2µF VCC VCC = –5mA at VCC Atmel ATA6616/ATA6617 Symbol Min. Typ. Max. VCC 4.9 5.1 nor VCC V – V 5.1 low 250 D1 V 400 600 D2 V ...
Page 26
... Figure 3-10. Definition of Bus Timing Characteristics TXD (Input to transmitting node) TH Rec(max Dom(max) (Transceiver supply of transmitting node) TH Rec(min) TH Dom(min) RXD (Output of receiving node1) t rx_pdf(1) RXD (Output of receiving node2) Atmel ATA6616/ATA6617 Bit Bit t Bus_dom(max) LIN Bus Signal t Bus_dom(min) t rx_pdr(2) t Bit t Bus_rec(min) Thresholds of receiving node1 Thresholds of ...
Page 27
... Atmel ATtiny87/ATtiny167 Microcontroller Block for Atmel ATA6616/ATA6617 4.1 Features • High Performance, Low Power AVR 8-bit Microcontroller • Advanced RISC Architecture – 123 Powerful Instructions – Most Single Clock Cycle Execution – 32 – Fully Static Operation • Non-volatile Program and Data Memories – ...
Page 28
... On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI serial interface conventional non-volatile memory programmer On-chip boot code running on the AVR core. The Boot program can use any interface to download the appli- cation program in the Flash memory. Atmel ATA6616/ATA6617 28 Table 4-1. ...
Page 29
... Typical values contained in this data sheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min. and Max val- ues will be available after the device is characterized. 9132D–AUTO–12/10 Atmel ATA6616/ATA6617 ® ATtiny87/167 is a powerful microcontroller that provides a highly flexible and ® ...
Page 30
... Block Diagram Figure 4-1. 4.2.6 Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. Atmel ATA6616/ATA6617 30 Block Diagram Watchdog Power Timer Supervision POR / BOD & Watchdog RESET Oscillator Oscillator Flash Circuits / Clock Generation EEPROM ...
Page 31
... The CPU must therefore be able to access mem- ories, perform calculations, control peripherals, and handle interrupts. Figure 4-2. 9132D–AUTO–12/10 Atmel ATA6616/ATA6617 ® core architecture in general. The main function of the CPU Block Diagram of the AVR Architecture ...
Page 32
... The I/O memory space contains 64 addresses for CPU peripheral functions as Control Regis- ters, SPI, and other I/O functions. The I/O memory can be accessed directly the Data Space locations following those of the Register File, 0x20 - 0x5F. Atmel ATA6616/ATA6617 32 ® uses a Harvard architecture – ...
Page 33
... Bit 3 – V: Two’s Complement Overflow Flag The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction Set Description” for detailed information. 9132D–AUTO–12/10 Atmel ATA6616/ATA6617 ® ALU operates in direct connection with all the 32 general pur- 7 ...
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... Data Space. Although not being physically imple- mented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file. Atmel ATA6616/ATA6617 34 shows the structure of the 32 general purpose working registers in the CPU. ...
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... AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present 9132D–AUTO–12/10 The X-, Y-, and Z-registers R27 (0x1B R29 (0x1D R31 (0x1F) ® Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of Atmel ATA6616/ATA6617 Figure 4-4 on page R26 (0x1A R28 (0x1C R30 (0x1E) 35 ...
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... MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. Figure 4-5. Figure 4-6 ALU operation using two register operands is executed, and the result is stored back to the destination register. Figure 4-6. Atmel ATA6616/ATA6617 SP15 SP14 ...
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... CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence. 9132D–AUTO–12/10 ® provides several different interrupt sources. These interrupts and the separate Atmel ATA6616/ATA6617 Section 4.8 “Interrupts” on page 82. 37 ...
Page 38
... A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. Atmel ATA6616/ATA6617 38 in r16, SREG ...
Page 39
... Size Internal Start Address SRAM End Address Size EEPROM Start Address End Address 1. Byte address. Table 4-3 on page Section 4.22 “Memory Programming” on page 250 36. Atmel ATA6616/ATA6617 ® ATtiny87/167. The AVR Mnemonic ATtiny87 Flash size 8Kbytes - 0x0000 (1) 0x1FFF Flash end (4.4.1) ...
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... The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers and the internal data SRAM in the Atmel ATtiny87/167 are all accessible through all these addressing modes. The Register File is described in File” on page Atmel ATA6616/ATA6617 40 Program Memory Map Program Memory ® ...
Page 41
... On-chip Data SRAM Access Cycles T1 clk CPU Address Compute Address Data WR Data RD Memory Access Instruction ® ATtiny87/167 contains EEPROM memory (see “E2 size” in Atmel ATA6616/ATA6617 0x0000 - 0x001F 0x0020 - 0x005F 0x0060 - 0x00FF ISRAM start ISRAM end cycles as described in Figure CPU T2 T3 Address valid Next Instruction ...
Page 42
... If the location to be written has not been erased before write, the data that is stored must be considered as lost. While the device is busy with programming not possible to do any other EEPROM operations. Atmel ATA6616/ATA6617 42 “Preventing EEPROM Corruption” on page 44 “ ...
Page 43
... Set Programming mode */ EECR = (0<<EEPM1)|(0<<EEPM0); /* Set up address and data registers */ EEAR = ucAddress; EEDR = ucData; /* Write logical one to EEMPE */ EECR |= (1<<EEMPE); /* Start eeprom write by setting EEPE */ EECR |= (1<<EEPE); } Atmel ATA6616/ATA6617 Section 4.5.5.1 “OSCCAL – Oscillator 43 ...
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... BOD does not match the needed detection level, an external low Vcc reset protection circuit can be used reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient. Atmel ATA6616/ATA6617 44 EEPROM_read: ; Wait for completion of previous write ...
Page 45
... ATtiny87/167 is shown in 290. ® ATtiny87/167 contains three General Purpose I/O Registers. These registers can EEAR7 EEAR6 EEAR5 EEAR4 R/W R/W R/W R Atmel ATA6616/ATA6617 Section 4.26 “Register Sum EEAR8 EEAR3 EEAR2 EEAR1 EEAR0 R/W R/W R ® ATtiny87/167. 0 EEARH EEARL 0 R/W R/W ...
Page 46
... The Programming times for the different modes are shown in EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming. Table 4-4. EEPM1 Atmel ATA6616/ATA6617 46 For information only - ATtiny47: EEAR8 exists as register bit but it is not used for addressing ...
Page 47
... Read/Write Initial Value 4.4.5.5 General Purpose I/O Register 1 – GPIOR1 Bit Read/Write Initial Value 4.4.5.6 General Purpose I/O Register 0 – GPIOR0 Bit Read/Write Initial Value 9132D–AUTO–12/10 Atmel ATA6616/ATA6617 GPIOR27 GPIOR26 GPIOR25 GPIOR24 GPIOR23 GPIOR22 GPIOR21 GPIOR20 R/W R/W R/W R ...
Page 48
... Modes” on page 65 below. Figure 4-10. Clock Distribution Asynchronous Timer/Counter0 Atmel ATA6616/ATA6617 48 ® ATtiny87/167 provides a large number of clock sources. They can be divided into presents the principal clock systems in the AVR and “Dynamic Clock Switch” on page ...
Page 49
... Device Clocking Options Select 1. For all fuses “1” means unprogrammed while “0” means programmed 2. Flash Fuse bits 3. CLKSELR register bits Atmel ATA6616/ATA6617 ® core operation. (1) versus PB4 and PB5 Functionality (2) CKSEL3..0 (3) CSEL3 ...
Page 50
... The Watchdog Oscillator will still be used for the Watchdog Timer and for the Reset Time-out even when this Oscillator is used as the device clock. For more information on the pre-pro- grammed calibration value, see the section Atmel ATA6616/ATA6617 50 Table 4-6. Number of Watchdog Oscillator Cycles Typ ...
Page 51
... Power-down/save ( Flash Fuse bits 2. CLKSELR register bits 3. This setting is only available if RSTDISBL fuse is not set Atmel ATA6616/ATA6617 (1) (MHz) Additional Delay from Reset (Vcc = 5.0V) Recommended Usage 14CK 14CK + 4.1ms 14CK + 65ms Slowly rising power Reserved Table 4-5 on page Additional Delay from Reset (Vcc = 5.0V) ...
Page 52
... The operating mode is selected by CKSEL3..1 fuses or by CSEL3..1 field as shown in Table Table 4-10. CKSEL3..1 CSEL3..1 Notes: The CKSEL0 Fuse together with the SUT1..0 Fuses or CSEL0 together with CSUT1..0 field select the start-up times as shown in Atmel ATA6616/ATA6617 52 Table C2 C1 4-10. Crystal Oscillator Operating Modes (1) ...
Page 53
... They can also be used with crystals when not operating close to the maximum frequency of the device, and if frequency stability at start-up is not important for the application. 5. This setting is only available if RSTDISBL fuse is not set. 49. The crystal should be connected as shown in Atmel ATA6616/ATA6617 Additional Delay from Reset (Vcc = 5.0V) Recommended Usage ...
Page 54
... Figure 4-13. External Clock Drive Configuration When this clock source is selected, start-up times are determined by the SUT Fuses or CSUT field as shown in high or low frequency Crystal Oscillator is not running page Atmel ATA6616/ATA6617 22pF 32.768KHz 22pF 12 - 22pF capacitors may be necessary if parasitic impedance (pads, wires & ...
Page 55
... Clock Source’, – ‘Enable Clock Source’, – ‘Request Clock Availability’, – ‘Clock Source Switching’, – ‘Recover System Clock Source’, – ‘Enable Watchdog in Automatic Reload Mode’. Atmel ATA6616/ATA6617 Additional Delay from Reset (Vcc = 5.0V) Recommended Usage (3) 14CK (+ 4.1ms ) 14CK + 4 ...
Page 56
... Clock Source’, ‘Request for Clock Availability’ or ‘Clock Source Switching’ commands. Source Recovering The ‘Recover System Clock Source’ command updates the CKSEL field of CLKSELR register (See “System Clock Source Recovering” on page Atmel ATA6616/ATA6617 56 Fuse: Register: CLKSELR ...
Page 57
... Calibrated internal RC oscillator 8.0MHz, 2. Internal watchdog oscillator 128kHz, 3. External clock, 4. External low-frequency oscillator, 5. External Crystal/Ceramic Resonator. 9132D–AUTO–12/10 Atmel ATA6616/ATA6617 for using. Table 4-5 on page 49. The CKSEL field of CLKSELR register is then Section 4.5.2.7 “Clock Output 57 ...
Page 58
... CLOCK #define CLOCK #define CLOCK #define CLOCK unsigned char previous } Warning: In the Atmel at a given time. Moreover, the enables of the external clock and of the external low-frequency oscillator are shared with the asynchronous timer. Atmel ATA6616/ATA6617 58 _ RECOVER 0x05 _ ENABLE 0x02 _ SWITCH ...
Page 59
... The WDP3..0 bits of the WDTCSR register always determine the watch- dog timer prescaling. As the watchdog will not be active before executing the ‘Enable Watchdog in Automatic Reload Mode’ command recommended to activate this command before switching to an external clock source (See following notes). 9132D–AUTO–12/10 Atmel ATA6616/ATA6617 57.). WD Interrupt WatchDog WD ...
Page 60
... CLOCK #define WD #define WD unsigned char previous } } Atmel ATA6616/ATA6617 60 1. ONLY the reset (watchdog reset included) disables this function. The Watchdog System Reset Flag (WDRF bit of MCUSR register) can be used to monitor the reset cause. 2. ONLY clock frequencies (4 * WatchDog Clock frequency) can be monitored. ...
Page 61
... ATtiny87/167 system clock can be divided by setting the Clock Prescaler Register Table 4-14 on page CAL7 CAL6 CAL5 CAL4 R/W R/W R/W R/W Device Specific Calibration Value Atmel ATA6616/ATA6617 , clk , clk I/O ADC CPU 63 CAL3 CAL2 CAL1 CAL0 R/W R/W ...
Page 62
... Note that any value can be written to the CLKPS bits regardless of the CKDIV8 Fuse setting. The Application software must ensure that a sufficient division factor is chosen if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed. Atmel ATA6616/ATA6617 CLKPCE – ...
Page 63
... Clock Prescaler Select CLKPS2 CLKPS1 CLKCCE – – R Atmel ATA6616/ATA6617 CLKPS0 Clock Division Factor 128 0 256 1 Reserved 0 Reserved 1 Reserved 0 Reserved 1 Reserved 0 Reserved 1 Reserved CLKRDY CLKC3 CLKC2 CLKC1 R R/W R/W R ® ATtiny87/167 and will always read as zero CLKC0 CLKCSR R ...
Page 64
... In case of ‘Enable/Disable Clock Source’ command, CSUT field provides the code of the clock start-up time. Refer to subdivisions of clock start-up times. In case of ‘Recover System Clock Source’ command, CSUT field is not affected (no recover- ing of SUT code). Atmel ATA6616/ATA6617 64 63.). CLKCSR to zero. bit. ...
Page 65
... Atmel Active Clock Domains and Wake-up Sources in the Different Sleep Modes Active Clock Domains Idle For INT1 and INT0, only level interrupt Table 4-17 on page 70 Atmel ATA6616/ATA6617 for clock source codes. Figure 4-10 on page for more details. Oscillators Wake-up Sources ...
Page 66
... Watchdog Interrupt, a Brown-out Reset, a USI start condition interrupt, an asynchronous Timer/Counter interrupt, an SPM/EEPROM ready interrupt, an external level interrupt on INT0 or INT1 or a pin change interrupt can wake up the MCU from ADC Noise Reduction mode. Atmel ATA6616/ATA6617 66 70. Setting it to one turns off the BOD in relevant 70 ...
Page 67
... Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall power consumption. In all other sleep modes, the clock is already stopped. 9132D–AUTO–12/10 Atmel ATA6616/ATA6617 for details. Section 4.5.2 “Clock Sources” on page , allowing operation only of asynchro- ASY “ ...
Page 68
... The Internal Current Source is not needed in the deeper sleep modes. This module should be turned off to reduce significantly to the total current consumption. Refer to “AMISCR – Analog Miscellaneous Control Register” on page 213 the Internal Current Source. Atmel ATA6616/ATA6617 68 ® controlled system. In general, sleep modes should be used as much as possible, for details on ADC operation. Section 4.19 “ ...
Page 69
... Section 4.18.12.6 “DIDR1 – Digital Input Disable Register 1” on page 234 – – – ® ATtiny87/167, and will always read as zero. Atmel ATA6616/ATA6617 for details on how to configure ) are stopped, the input buffers of the device will ADC – – SM1 SM0 R R R/W ...
Page 70
... PRR – Power Reduction Register Bit Read/Write Initial Value • Bit 7 - Res: Reserved bit This bit is reserved in Atmel • Bit 6 - Res: Reserved bit This bit is reserved in Atmel ATtiny87/167 and will always read as zero. Atmel ATA6616/ATA6617 70 Sleep Mode Select SM1 SM0 Sleep Mode 0 0 ...
Page 71
... SUT and CKSEL Fuses. The different selections for the delay period are presented in Sources” on page 9132D–AUTO–12/10 Atmel ATA6616/ATA6617 Figure 4-16 shows the reset circuit. Tables in defines the electrical parameters of the reset circuitry. ...
Page 72
... Brown-out Reset. The MCU is reset when the supply voltage Vcc is below the Brown-out Reset threshold (V Figure 4-16. Reset Circuit BODLEVEL [2..0] Pull-up Resistor RSTDISBL Spike Filter Atmel ATA6616/ATA6617 72 ® ATtiny87/167 has four sources of reset: ). POT ) and the Brown-out Detector is enabled. BOT ...
Page 73
... POR RESET RESET Table 4-83 on page TOUT Table 4-70 on page Atmel ATA6616/ATA6617 270. The POR is activated whenever Vcc is below the V RST t TOUT 270) will generate a reset, even if the clock is – on its positive edge, the delay counter starts RST – has expired. The External Reset can be disabled 251 ...
Page 74
... TOUT The BOD circuit will only detect a drop in Vcc if the voltage stays below the trigger level for lon- ger than t Figure 4-20. Brown-out Reset During Operation Atmel ATA6616/ATA6617 74 CC ® ATtiny87/167 has an On-chip Brown-out Detection (BOD) circuit for monitoring the Vcc ...
Page 75
... Reset Flags. 9132D–AUTO–12/10 page 76 for details on operation of the Watchdog Timer – – – ® Atmel ATA6616/ATA6617 – WDRF BORF EXTRF R R/W R/W R/W 0 See Bit Description ATtiny87/167, and will always read as zero. . TOUT 0 ...
Page 76
... Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode 4.7.3.1 Watchdog Timer Behavior The Watchdog Timer (WDT timer counting cycles of a separate on-chip 128 KHz oscillator. Atmel ATA6616/ATA6617 76 ® ATtiny87/167 features an internal bandgap reference. This reference is used for Table 4-87 on page ACIRS bit in ACSR). ® ...
Page 77
... WDP1 WDP2 WDP3 CLOCK MONITORING WDE WDIF WDIE and WDE. A logic one must be written to WDE regardless of the previous value of the WDE bit. as desired, but with the WDCE bit cleared. This must be done in one operation. Atmel ATA6616/ATA6617 WATCHDOG PRESCALER MCU RESET INTERRUPT 77 ...
Page 78
... The following code example shows one assembly and one C function for turning off the Watchdog Timer. The example assumes that interrupts are controlled (e.g. by disabling inter- rupts globally) so that no interrupts will occur during the execution of these functions. Assembly Code Example C Code Example Notes: Atmel ATA6616/ATA6617 78 (1) WDT_off: ; Turn off global interrupt cli ...
Page 79
... Section 4.2.7 “About Code Examples” on page 31 2. The Watchdog Timer should be reset before any change of the WDP bits, since a change in the WDP bits can result in a time-out when switching to a shorter time-out period. Atmel ATA6616/ATA6617 Section 4.5.3.8 “Clock Monitoring” on page 79 ...
Page 80
... Bit 4 - WDCE: Watchdog Change Enable This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE bit, and/or change the prescaler bits, WDCE must be set. Once written to one, hardware will clear WDCE after four clock cycles. Atmel ATA6616/ATA6617 ...
Page 81
... Atmel ATA6616/ATA6617 Number of Typical Time-out at Vcc = 5.0V 2K (2048) cycles 4K (4096) cycles 8K (8192) cycles 0.125s Reserved 16ms 32ms 64ms 0.25s 0.5s 1.0s 2.0s 4.0s 8.0s 81 ...
Page 82
... Atmel ATA6616/ATA6617 82 37. ® ATtiny87/167 Source Interrupt Definition External Pin, Power-on Reset, Brown-out Reset and RESET Watchdog System Reset INT0 External Interrupt Request 0 INT1 External Interrupt Request 1 PCINT0 Pin Change Interrupt Request 0 ...
Page 83
... SPL,r16 sei <instr> xxx ... ... ... ... 16-bit address Atmel ATA6616/ATA6617 Comments ; Reset Handler ; IRQ0 Handler ; IRQ1 Handler ; PCINT0 Handler ; PCINT1 Handler ; Watchdog Timer Handler ; Timer1 Capture Handler ; Timer1 Compare A Handler ; Timer1 Compare B Handler ; Timer1 Overflow Handler ; Timer0 Compare A Handler ...
Page 84
... RESET: 0x0029 0x002A 0x002B 0x002C 0x002D Note: Atmel ATA6616/ATA6617 84 (1) Label Code jmp RESET jmp INT0addr jmp INT1addr jmp PCINT0addr jmp PCINT1addr jmp WDTaddr jmp ICP1addr jmp OC1Aaddr ...
Page 85
... The start-up time is defined by the SUT and CKSEL Fuses as described in 48. 9132D–AUTO–12/10 Atmel ATA6616/ATA6617 Section 4.5.1 “Clock Systems and their 48. Low level interrupts and the edge interrupt on INT1..0 are detected Section 4.5.1 “Clock Systems and their Distribution” on page ...
Page 86
... If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. Atmel ATA6616/ATA6617 86 0 pin_sync ...
Page 87
... Any logical change on INTn generates an interrupt request The falling edge of INTn generates an interrupt request The rising edge of INTn generates an interrupt request. Bit – – – Atmel ATA6616/ATA6617 – – – INT1 R ® ATtiny87/167, and will always read as zero. 0 INT0 EIMSK ...
Page 88
... When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 0 is enabled. Any change on any enabled PCINT7..0 pin will cause an inter- rupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0 Interrupt Vector. PCINT7..0 pins are enabled individually by the PCMSK0 Register. Atmel ATA6616/ATA6617 88 Bit 7 ...
Page 89
... Bit – – – Bit PCINT15 PCINT14 PCINT13 PCINT12 PCINT11 PCINT10 R/W R/W R Bit PCINT7 PCINT6 PCINT5 R/W R/W R Atmel ATA6616/ATA6617 – – – PCIF1 R ® ATtiny87/167, and will always read as zero PCINT9 R/W R/W R/W R PCINT4 PCINT3 ...
Page 90
... Functions” on page alternate functions. Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. Atmel ATA6616/ATA6617 90 ® ports have true Read-Modify-Write functionality when used as general digital I/O Section 4.23 “ ...
Page 91
... I/O CLOCK I/O 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk SLEEP, and PUD are common to all ports. 109, the DDxn bits are accessed at the DDRx I/O Atmel ATA6616/ATA6617 Figure 4- DDxn Q CLR ...
Page 92
... Figure 4-26. Break Before Make, Switching between Input and Output SYSTEM CLOCK INSTRUCTIONS PORTx DDRx Px0 Px1 Atmel ATA6616/ATA6617 92 99. When switching the DDRxn bit from output to input there is 0x02 0x01 out DDRx, r16 nop 0x55 0x01 0x02 ...
Page 93
... Or port-wise PUDx bit in PORTCR register. Figure 4-25, the PINxn Register bit and the preceding latch SYSTEM CLK INSTRUCTIONS XXX SYNC LATCH PINxn r17 Atmel ATA6616/ATA6617 Pull-up Comment No Tri-state (Hi-Z) Yes Pxn will source current if ext. pulled low. No Tri-state (Hi-Z) No Output Low (Sink) ...
Page 94
... The result- ing pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. Atmel ATA6616/ATA6617 94 Figure 4-28. The out instruction sets the “ ...
Page 95
... For the assembly program, two temporary registers are used to minimize the time from pull-ups are set on pins and 7, until the direction bits are correctly set, defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers. Atmel ATA6616/ATA6617 95 ...
Page 96
... The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR Atmel ATA6616/ATA6617 96 Figure 4-25, the digital input signal can be clamped to ground at the input of the “ ...
Page 97
... DIxn: DIGITAL INPUT PIN n ON PORTx AIOxn: ANALOG INPUT/OUTPUT PIN n ON PORTx 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk SLEEP, and PUD are common to all ports. All other signals are unique for each pin. Atmel ATA6616/ATA6617 PUD Q D ...
Page 98
... The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function description for fur- ther details. Atmel ATA6616/ATA6617 98 summarizes the function of the overriding signals. The pin and port indexes from are not shown in the succeeding tables ...
Page 99
... DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn 1). The Port-Wise Pull-up Disable bits are ORed with the global Pull-up Disable bit (PUD) from the MCUCR register. See details about this feature. 9132D–AUTO–12/10 Atmel ATA6616/ATA6617 – ...
Page 100
... Alternate Functions of Port A The Port A pins with alternate functions are shown in Table 4-24. Atmel ATA6616/ATA6617 100 Port A Pins Alternate Functions Port Pin Alternate Function PCINT7 (Pin Change Interrupt 7) ADC7 (ADC Input Channel 7) PA7 AIN1 (Analog Comparator Positive Input) XREF (Internal Voltage Reference Output) ...
Page 101
... PORTA6 bit. pin is configured as an input regardless of the setting of DDA5. When the SPI is enabled as a master, the data direction of this pin is controlled by DDA5. When the pin is forced input, the pull-up can still be controlled by the PORTA5 bit. Timer/Counter1. Atmel ATA6616/ATA6617 101 ...
Page 102
... TXLIN: LIN Transmit pin. When the LIN is enabled, this pin is configured as an output regard • PCINT0/ADC0/RXD/RXLIN – Port A, Bit 0 PCINT0: Pin Change Interrupt, source 0. ADC0: Analog to Digital Converter, channel 0. Atmel ATA6616/ATA6617 102 Three-wire Mode USI Data Input. USI Three-wire mode does not override normal port functions, so pin must be configure as an input for DI function. ...
Page 103
... PCMSK07) PCMSK06) PCIE0 & PCIE0 & PCMSK07 PCMSK06 PCINT7 PCINT6 -/- SS ADC7 -/- AIN1 -/- ADC6 -/- AIN0 XREF -/- AREF Atmel ATA6616/ATA6617 PA5/PCINT5/ADC5/ PA4/PCINT4/ADC4/ T1/USCK/SCL/SCK ICP1/DI/SDA/MOSI SPE & MSTR SPE & MSTR PORTA5 & PUD PORTA4 & PUD (SPE & MSTR) | (SPE & MSTR) | (USI_2_WIRE & ...
Page 104
... Table 4-26. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Atmel ATA6616/ATA6617 104 Overriding Signals for Alternate Functions in PA3..PA0 PA3/PCINT3/ADC3 / PA2/PCINT2/ADC2/ ISRC/INT1 OC0A/DO/MISO 0 SPE & MSTR PORTA3 & PUD PORTA2 & PUD 0 SPE & MSTR 0 0 (SPE & MSTR) | (USI_2_WIRE & ...
Page 105
... DI (Three-wire Mode USI Default Data Input) SDA (Two-wire Mode USI Default Data Input / Output) configured as an output (DDB7 set (one)) to serve this function. The OC1BX pin is also the output pin for the PWM mode timer function (c.f. OC1BX bit of TCCR1D register). Atmel ATA6616/ATA6617 Table 4-27. 105 ...
Page 106
... XTAL1: Chip clock Oscillator pin 1. Used for all chip clock sources except internal calibrated CLKI: External clock input. When used as a clock pin, the pin can not be used as an I/O pin. Note: Atmel ATA6616/ATA6617 106 normal I/O pin, and the part will have to rely on Power-on Reset and Brown-out Reset as its reset sources ...
Page 107
... PWM mode timer function (c.f. OC1AU bit of TCCR1D register). Three-wire Mode USI Data Input. USI Three-wire mode does not override normal port functions, so pin must be configure as an input for DI function. and Table 4-29 relate the alternate functions of Port B to the overriding signals Figure 4-29 on page 97. Atmel ATA6616/ATA6617 one ( ). 107 ...
Page 108
... PVOV PTOE DIEOE DIEOV DI AIO Table 4-29. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Atmel ATA6616/ATA6617 108 Overriding Signals for Alternate Functions in PB7..PB4 PB7/PCINT15/ADC10/ PB6/PCINT14/ADC9/ OC1BX/RESET/dW OC1AX/INT0 OC1B_ENABLE & OC1A_ENABLE & OC1BX OC1AX OC1B OC1A ...
Page 109
... Port B Data Register – PORTB Bit Read/Write Initial Value 4.10.4.5 Port B Data Direction Register – DDRB Bit Read/Write Initial Value 4.10.4.6 Port B Input Pins Register – PINB Bit Read/Write Initial Value 9132D–AUTO–12/10 Atmel ATA6616/ATA6617 PORTA7 PORTA6 PORTA5 PORTA4 R/W R/W R/W R ...
Page 110
... Timer/Counter0 output compare channel A value and so on. A simplified block diagram of the 8-bit Timer/Counter is shown in I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Regis- ter and bit locations are listed in the Atmel ATA6616/ATA6617 110 Figure “8-bit Timer/Counter Register Description” on page 4-30 ...
Page 111
... BOTTOM TOP Prescaler = 0 = 0xFF Synchronized Status flags Synchronization Unit ASSRn asynchronous mode select (ASn for details. The compare match event will also set the compare Atmel ATA6616/ATA6617 TOVn (Int.Req.) XTAL2 Oscillator XTAL1 clk OCnx I/O (Int.Req.) Waveform OCnx Generation clk I/O ...
Page 112
... The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. ure 4-31 Figure 4-31. Counter Unit Block Diagram Signal description (internal signals): Atmel ATA6616/ATA6617 112 The counter reaches the BOTTOM when it becomes zero (0x00). The counter reaches its MAXimum when it becomes 0xFF (decimal 255). ...
Page 113
... A CPU write overrides (has priority over) all T0 116. (“Modes of Operation” on page 116). shows a block diagram of the Output Compare unit. DATA BUS OCRnx = (8-bit Comparator ) top bottom Waveform Generator FOCn WGMn1:0 Atmel ATA6616/ATA6617 TCNTn OCFnx (Int.Req.) OCnx COMnX1:0 113 ...
Page 114
... I/O pins in the figure are shown in bold. Only the parts of the general I/O port control registers (DDR and PORT) that are affected by the COM0A1:0 bits are shown. When referring to the OC0A state, the reference is for the internal OC0A Register, not the OC0A pin. Atmel ATA6616/ATA6617 114 Figure 4-33 shows a 9132D– ...
Page 115
... COMnx0 D Generator FOCnx D PORT D clk I/O See ”8-bit Timer/Counter Register Description” on page 124. Table 4-30 on page 124, and for phase correct PWM refer to Atmel ATA6616/ATA6617 Q 1 OCnx Pin OCnx DDR 124. For fast PWM mode, refer to Table 4-32 on page 125. ...
Page 116
... The timing diagram for the CTC mode is shown in increases until a compare match occurs between TCNT0 and OCR0A, and then counter (TCNT0) is cleared. Figure 4-34. CTC Mode, Timing Diagram TCNTn OCnx (Toggle) Period Atmel ATA6616/ATA6617 116 (See ”Compare Match Output Unit” on page “Timer/Counter Timing Diagrams” on page Figure 114 ...
Page 117
... PWM outputs. The small horizontal line marks on the TCNT0 slopes represent com- pare matches between OCR0A and TCNT0. 9132D–AUTO–12/10 /2 when OCR0A is set to zero (0x00). The waveform frequency is defined by the follow- f clk_I/O = ------------------------------------------------------- - OCRnx Figure 4-35. The TCNT0 value is in the timing diagram shown as a Atmel ATA6616/ATA6617 = OC0A 117 ...
Page 118
... OC0A to toggle its logical level on each compare match (COM0A1:0 = 1). The wave- form generated will have a maximum frequency of f This feature is similar to the OC0A toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode. Atmel ATA6616/ATA6617 118 1 2 ...
Page 119
... OC0A pin. Setting the COM0A1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM0A1:0 to three (See 125). The actual OC0A value will only be visible on the port pin if the data direction for the port pin is set as output. 9132D–AUTO–12/10 Atmel ATA6616/ATA6617 Fig- ...
Page 120
... TCNTn TOVn Figure 4-38 Figure 4-38. Timer/Counter Timing Diagram, with Prescaler (f clk clk (clk TCNTn TOVn Atmel ATA6616/ATA6617 120 f clk_I/O = -------------------- - N 510 ) is therefore shown as a clock enable signal. In asynchronous mode, clk Figure 4-37 contains timing data for basic Timer/Counter operation. The ...
Page 121
... OCF0A in all modes except CTC mode. clk I/O clk Tn (clk /8) I/O TCNTn OCRnx - 1 OCRnx OCFnx shows the setting of OCF0A and the clearing of TCNT0 in CTC mode. Prescaler (f /8) clk_I/O I/O Tn /8) I/O TOP - 1 Atmel ATA6616/ATA6617 OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value TOP BOTTOM TOP /8) clk_I/O BOTTOM + 1 121 ...
Page 122
... XTAL1 edge. The phase of the XTAL1 clock after waking up from Power-save mode is essentially unpredictable depends on the wake-up time. The recommended procedure for reading TCNT0 is thus as follows: Atmel ATA6616/ATA6617 122 ) again becomes active, TCNT0 will read as the I/O ...
Page 123
... ASn PSRn CSn0 CSn1 CSn2 . By setting the AS0 bit in ASSR, Timer/Counter0 is asynchro- IO /128, clk /256, and clk /1024. Additionally, clk T0S T0S Atmel ATA6616/ATA6617 clk TnS 10-BIT T/C PRESCALER Clear 0 TIMER/COUNTERn CLOCK SOURCE clk Tn . clk is by default connected to the T0S T0S ...
Page 124
... When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the WGM01:0 bit setting. bits are set to a normal or CTC mode (non-PWM). Table 4-30. COM0A1 Table 4-31 mode. Table 4-31. COM0A1 Note: Atmel ATA6616/ATA6617 124 COM0A1 COM0A0 – R/W R/W R ...
Page 125
... Waveform Generation Mode Bit Description WGM01 WGM00 Timer/Counter (CTC0) (PWM0) Mode of Operation PWM, Phase Correct Fast PWM 1. MAX = 0xFF 2. BOTTOM = 0x00 Atmel ATA6616/ATA6617 (1) “Phase Correct PWM Table Update of TOP OCR0A at Normal 0xFF Immediate 0xFF TOP CTC OCR0A Immediate 0xFF TOP 4-33. Modes of (See ...
Page 126
... The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes) the Com- pare Match on the following timer clock. Modifying the counter (TCNT0) while the counter is running, introduces a risk of missing a Compare Match between TCNT0 and the OCR0x Register. Atmel ATA6616/ATA6617 126 FOC0A – ...
Page 127
... OCR0A7 OCR0A6 OCR0A5 OCR0A4 OCR0A3 OCR0A2 OCR0A1 OCR0A0 R/W R/W R/W R – EXCLK AS0 TCN0UB OCR0AUB R R/W R ® ATtiny87/167 and will always read as zero. (Section 4.5.2.6 “External Clock” on page Atmel ATA6616/ATA6617 R/W R/W R/W R – TCR0AUB TCR0BUB 53) or from external clock on 54) depending on EXCLK setting. When 0 OCR0A 0 0 ...
Page 128
... When the TOIE0 bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter0 Inter- rupt Flag Register – TIFR0. Atmel ATA6616/ATA6617 128 7 6 ...
Page 129
... The bit will not be cleared by hardware if the TSM bit is set. Refer to the description of the Timer/Counter Synchronization Mode” on page 132 Synchronization mode. 9132D–AUTO–12/10 Atmel ATA6616/ATA6617 – ...
Page 130
... The edge detector generates one clk (CSn2 edge it detects. Figure 4-42. T1 Pin Sampling Atmel ATA6616/ATA6617 130 ). Alternatively, one of four taps from the prescaler can be CLK_I/O /256 /1024 ...
Page 131
... ExtClk clk_I/O /2.5. clk_I/O CLK I/O PSRn Tn Synchronization CSn0 CSn1 CSn2 1. The synchronization logic on the input pin (T1) is shown in Atmel ATA6616/ATA6617 /2) given a 50/50 % duty cycle. Since the edge detec- (1) 10-BIT T/C PRESCALER Clear 0 clk Tn TIMER/COUNTERn CLOCK SOURCE Figure 4-42. 131 ...
Page 132
... When the TSM bit is written to zero, the PSR0 and PSR1 bits are cleared by hardware, and the Timer/Counters start counting simultaneously. • Bit 0 – PSR1: Prescaler Reset Timer/Counter1 When this bit is one, Timer/Counter1 prescaler will be reset. This bit is normally cleared imme- diately by hardware, except if the TSM bit is set. Atmel ATA6616/ATA6617 132 ...
Page 133
... A simplified block diagram of the 16-bit Timer/Counter is shown in ble I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the 157. 9132D–AUTO–12/10 Atmel ATA6616/ATA6617 Figure 4-44. CPU accessi- “16-bit Timer/Counter Register Description” on page 133 ...
Page 134
... Figure 4-44. 16-bit Timer/Counter1 Block Diagram Note: Atmel ATA6616/ATA6617 134 Count Clear Control Logic Direction TOP Timer/Counter TCNTn = OCRnA = OCRnB ICRn TCCRnA TCCRnB 1. Refer to Table 4-27 on page 105, and ment and description. (1) TOVn (Int.Req.) clk Clock Select Tn Edge Detector BOTTOM ( From Prescaler ) ...
Page 135
... The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be one of the fixed values: 0x00FF, 0x01FF, or 0x03FF the value stored in the OCR assignment is dependent of the mode of operation. Atmel ATA6616/ATA6617 “Accessing 16-bit Registers” 236). The Input Capture unit includes 1 ...
Page 136
... The same principle can be used directly for access- ing the OCR1A/B and ICR1 Registers. Note that when using “C”, the compiler handles the 16-bit access. Assembly Code Examples C Code Examples Note: Atmel ATA6616/ATA6617 136 (1) ... 1 ; Set TCNT ...
Page 137
... Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Read TCNT1 into TCNT1; /* Restore global interrupt flag */ SREG = sreg; return i; 1. The example code assumes that the part specific header file is included. Atmel ATA6616/ATA6617 137 ...
Page 138
... If writing to more than one 16-bit register where the high byte is the same for all registers writ- ten, then the high byte only needs to be written once. However, note that the same rule of atomic operation described previously also applies in this case. Atmel ATA6616/ATA6617 138 (1) ...
Page 139
... TOP Signalize that TCNT1 has reached maximum value. BOTTOM Signalize that TCNT1 has reached minimum value (zero). ). The clk present or not. A CPU write overrides (has priority over) all T 1 Atmel ATA6616/ATA6617 130. TOVn (Int.Req.) Clock Select Count Edge Detector Clear clk ...
Page 140
... TCNT1 value is copied into ICR1 Register. If enabled (ICIE1 = 1), the Input Capture Flag generates an Input Capture interrupt. The ICF1 flag is automatically cleared when the interrupt is executed. Alternatively the ICF1 flag can be cleared by software by writing a logical one to its I/O bit location. Atmel ATA6616/ATA6617 140 DATA BUS TEMP (8-bit) ...
Page 141
... Even though the Input Capture interrupt has relatively high priority, the maximum interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests. 9132D–AUTO–12/10 Atmel ATA6616/ATA6617 136. “Accessing 16-bit Regis- (Figure 4-42 on page 130) ...
Page 142
... Waveform Generator. Figure 4-47 gram that are not directly a part of the Output Compare unit are gray shaded. Atmel ATA6616/ATA6617 142 (See “Modes of Operation” on page shows a block diagram of the Output Compare unit. The elements of the block dia- 147.) 9132D– ...
Page 143
... TEMP (8-bit) OCRnxH Buf.(8-bit) OCRnxL Buf.(8-bit) OCRnx Buffer (16-bit Register) OCRnxH (8-bit) OCRnxL (8-bit) OCRnx (16-bit Register) TOP BOTTOM 136. Atmel ATA6616/ATA6617 DATA BUS (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) = (16-bit Comparator ) OCFnx (Int.Req.) Waveform Generator ...
Page 144
... COM1A/B1:0 and OCnxi bits are shown. When referring to the OC1A/B state, the reference is for the internal OC1A/B Register, not the OC1A/Bi pin system reset occur, the OC1A/B Register is reset to “0”. Atmel ATA6616/ATA6617 144 shows a simplified schematic of the logic affected by the COM1A/B1:0 and OCnxi ...
Page 145
... COM1A1 OCF1A Waveform = Generation WGM10 TCNT1 WGM11 WGM12 16-bit Counter WGM13 Waveform = Generation OCF1B COM1B0 COM1B1 OCR1B 16-bit Register ( ) OC1xi: TCCR1D register bit * Atmel ATA6616/ATA6617 OC1AU ( ) * PINB0 1 20 PB0 / OC1AU 0 PORTB0 DDB0 OC1AV ( ) * PINB2 1 18 PB2 / OC1AV PORTB2 0 DDB2 OC1AW ( ) * ...
Page 146
... A change of the COM1A/B1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC1A/B strobe bits. Atmel ATA6616/ATA6617 146 OCnxi COMnx1 Waveform ...
Page 147
... The timing diagram for the CTC mode is shown in increases until a compare match occurs with either OCR1A or ICR1, and then counter (TCNT1) is cleared. 9132D–AUTO–12/10 Atmel ATA6616/ATA6617 (See ”Compare Match Output Unit” on page “Timer/Counter Timing Diagrams” on page Figure 4-50. The counter value (TCNT1) 144 ...
Page 148
... OCnA The N variable represents the prescaler factor (1, 8, 64, 256, or 1024). As for the Normal mode of operation, the TOV1 flag is set in the same timer clock cycle that the counter counts from MAX to 0x0000. Atmel ATA6616/ATA6617 148 ...
Page 149
... Figure 4-51. Fast PWM Mode, Timing Diagram TCNTn OCnxi OCnxi Period 9132D–AUTO–12/10 log TOP + 1 = ---------------------------------- - log Atmel ATA6616/ATA6617 OCRnx/TOP Update and TOVn Interrupt Flag Set and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) (COMnx1 (COMnx1 Figure 149 ...
Page 150
... PWM waveform output in the fast PWM mode. If the OCR1A/B is set equal to BOTTOM (0x0000) the output will be a narrow spike for each TOP+1 timer clock cycle. Setting the OCR1A/B equal to TOP will result in a constant high or low output (depending on the polarity of the output set by the COM1A/B1:0 bits.) Atmel ATA6616/ATA6617 150 f clk_I/O ...
Page 151
... The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes represent compare matches between OCR1A/B and TCNT1. The OC1A/B interrupt flag will be set when a compare match occurs. 9132D–AUTO–12/10 log TOP ---------------------------------- - log 2 Atmel ATA6616/ATA6617 = f /2 when OCR1A is set to OC clk_I Figure 4-52. 151 ...
Page 152
... It is recommended to use the phase and frequency correct mode instead of the phase correct mode when changing the TOP value while the Timer/Counter is running. When using a static TOP value there are practically no differences between the two modes of operation. Atmel ATA6616/ATA6617 152 1 2 ...
Page 153
... OCR1A set to MAX). The PWM resolution in bits can be calculated using the following equation: R PFCPWM 9132D–AUTO–12/10 158). The actual OC1A/B value will only be visible on the port pin if the data direction for f clk_I/O = --------------------------------- - 2 N TOP and Figure 4-53). log TOP ---------------------------------- - log 2 Atmel ATA6616/ATA6617 Table on Fig- 153 ...
Page 154
... ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. How- ever, if the base PWM frequency is actively changed by changing the TOP value, using the OCR1A as TOP is clearly a better choice due to its double buffer feature. Atmel ATA6616/ATA6617 154 Figure 4-53. The figure shows phase and frequency ...
Page 155
... OCR1A/B Register is updated with the OCR1A/B buffer value (only for modes utilizing double buffering). of OCF1A/B. Figure 4-54. Timer/Counter Timing Diagram, Setting of OCF1A/B, No Prescaling 9132D–AUTO–12/10 Atmel ATA6616/ATA6617 Table on page 158). The actual OC1A/B value will only be visible on the port pin f clk_I/O ...
Page 156
... TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOV1 flag at BOTTOM. Figure 4-56. Timer/Counter Timing Diagram, no Prescaling Atmel ATA6616/ATA6617 156 shows the same timing data, but with the prescaler enabled. ...
Page 157
... Normal port operation, OC1A/OC1B disconnected Toggle OC1A/OC1B on Compare Match. Clear OC1A/OC1B on Compare Match (Set output to low 1 0 level Set OC1A/OC1B on Compare Match (Set output to high level). Atmel ATA6616/ATA6617 /8) clk_I/O TOP BOTTOM BOTTOM + 1 TOP TOP - 1 TOP - 2 New OCRnx Value – – ...
Page 158
... Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. 147.). Atmel ATA6616/ATA6617 158 shows the COM1A/B1:0 bit functionality when the WGM13:0 bits are set to the fast Compare Output Mode, Fast PWM ...
Page 159
... CTC 0 1 (Reserved Fast PWM 1 1 Fast PWM ICNC1 ICES1 – WGM13 R/W R Atmel ATA6616/ATA6617 Update of TOP OCR1A/B at 0xFFFF Immediate 0x00FF TOP 0x01FF TOP 0x03FF TOP OCR1A Immediate 0x00FF TOP 0x01FF TOP 0x03FF TOP ICR1 BOTTOM OCR1A BOTTOM ICR1 TOP ...
Page 160
... COM1A/B1:0 bits that determine the effect of the forced compare. A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCR1A as TOP. The FOC1A/FOC1B bits are always read as zero. Atmel ATA6616/ATA6617 160 and Figure 4-55 ...
Page 161
... OC1A/B pin. 9132D–AUTO–12/ OC1BX OC1BW OC1BV R/W R/W R 146. 146 R/W R/W R R/W R/W R R/W R/W R Atmel ATA6616/ATA6617 OC1BU OC1AX OC1AW OC1AV R/W R/W R/W R TCNT1[15:8] TCNT1[7:0] R/W R/W R/W R OCR1A[15:8] OCR1A[7:0] R/W R/W R/W R ...
Page 162
... When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The correspond- ing Interrupt Vector when the OCF1A flag, located in TIFR1, is set. Atmel ATA6616/ATA6617 162 See “Accessing 16-bit Registers” on page 136. 7 ...
Page 163
... TOV1 flag is set when the timer overflows. Refer to flag behavior when using another WGM13:0 bit setting. TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is exe- cuted. Alternatively, TOV1 can be cleared by writing a logic one to its bit location. 9132D–AUTO–12/10 Atmel ATA6616/ATA6617 – ...
Page 164
... Write Collision Flag Protection • Wake-up from Idle Mode • Double Speed (CK/2) Master SPI Mode Figure 4-58. SPI Block Diagram /2/4/8/16/32/64/128 Note: Atmel ATA6616/ATA6617 164 ® ATtiny87/167 and peripheral devices or between several AVR (1) clk IO DIVIDER 1. Refer to Table 4-24 on page 100 for SPI pin placement. ® ...
Page 165
... In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure correct sampling of the clock signal, the frequency of the SPI clock should never exceed f /4. clkio 9132D–AUTO–12/10 Atmel ATA6616/ATA6617 Figure 4-59. The SHIFT ENABLE 165 ...
Page 166
... SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direc- tion bits for these pins. E.g. if MOSI is placed on pin PB2, replace DD_MOSI with DDB2 and DDR_SPI with DDRB. Atmel ATA6616/ATA6617 166 Table 4-40. For more details on automatic port overrides, refer to ...
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... Enable SPI, Master, set clock rate fck/16 */ SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0); /* Start transmission */ SPDR = cData; /* Wait for transmission complete */ while(!(SPSR & (1<<SPIF))); 1. The example code assumes that the part specific header file is included. Atmel ATA6616/ATA6617 167 ...
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... The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception. Assembly Code Example SPI_SlaveInit: SPI_SlaveReceive: C Code Example void SPI_SlaveInit(void char SPI_SlaveReceive(void Note: Atmel ATA6616/ATA6617 168 (1) ; Set MISO output, all others input ldi r17,(1<<DD_MISO) DDR_SPI,r17 out ; Enable SPI ldi r17,(1<<SPE) out SPCR,r17 ret ...
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... When the DORD bit is written to zero, the MSB of the data word is transmitted first. 9132D–AUTO–12/10 of the SPI becoming a Slave, the MOSI and SCK pins become inputs. SREG is set, the interrupt routine will be executed SPIE SPE DORD R/W R/W R Atmel ATA6616/ATA6617 MSTR CPOL CPHA SPR1 R/W R/W R/W R ...
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... Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0 These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between SCK and the clk shown in the following table: Table 4-43. Atmel ATA6616/ATA6617 170 Figure 4-60 and Figure 4-61 ...
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... Section 4.22.8 “Serial Downloading” on page 262 SPD7 SPD6 SPD5 SPD4 R/W R/W R/W R and Figure 4-61. Data bits are shifted out and latched in on opposite edges of the Table 4-41 and Table 4-42, as done below: Atmel ATA6616/ATA6617 – – – – SPD3 ...
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... Table 4-44. Figure 4-60. SPI Transfer Format with CPHA = 0 Figure 4-61. SPI Transfer Format with CPHA = 1 Atmel ATA6616/ATA6617 172 CPOL Functionality Leading Edge CPOL=0, CPHA=0 Sample (Rising) CPOL=0, CPHA=1 Setup (Rising) CPOL=1, CPHA=0 Sample (Falling) CPOL=1, CPHA=1 Setup (Falling) SCK (CPOL = 0) ...
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... Data Register Output and output pin, which delays the change of data output to the opposite clock edge of the data input sampling. The serial input is always sampled from the Data Input (DI) pin independent of the configuration. 9132D–AUTO–12/10 Atmel ATA6616/ATA6617 “Register Descriptions” on page ...
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... The Counter Overflow (interrupt) Flag, or USIOIF, can therefore be used to determine when a transfer is completed. The clock is generated by the Master device software by toggling the USCK pin via the PORT Register or by writing a one to the USITC bit in USICR. Atmel ATA6616/ATA6617 174 Bit7 Bit6 ...
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... The overflow interrupt will wake up the proces- sor set to Idle mode. Depending of the protocol used the slave device can now set its output to high impedance. sts USIDR,r16 r16,(1<<USIOIF) ldi sts USISR,r16 ldi r16,(1<<USIWM0)|(1<<USICS1)|(1<<USICLK)|(1<<USITC) Atmel ATA6616/ATA6617 LSB 3 2 ...
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... The fourth and fifth instruction set Three-wire mode, positive edge Shift Register clock, count at USITC strobe, and toggle USCK. The loop is repeated 16 times. The following code demonstrates how to use the USI module as a SPI Master with maximum speed (fsck = fck/4): SPITransfer_Fast: Atmel ATA6616/ATA6617 176 sts USICR,r16 lds ...
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... Pin names used by this mode are SCL and SDA. 9132D–AUTO–12/10 ldi r16,(1<<USIWM0)|(1<<USICS1) USICR,r16 sts sts USIDR,r16 ldi r16,(1<<USIOIF) USISR,r16 sts lds r16, USISR sbrs r16, USIOIF SlaveSPITransfer_loop rjmp r16,USIDR lds ret Atmel ATA6616/ATA6617 177 ...
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... The clock is generated by the master by toggling the USCK pin via the PORT Register. The data direction is not given by the physical layer. A protocol, like the one used by the TWI-bus, must be implemented to control the data flow. Atmel ATA6616/ATA6617 178 Bit7 Bit6 ...
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... If the bit is set, a master read operation is in progress (i.e., the slave drives the SDA line) The slave can hold the SCL line low after the acknowledge (E). given by the Master (F new start condition is given. SDA SCL Write( USISIF) Atmel ATA6616/ATA6617 ACK DATA ...
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... The Overflow Flag and Interrupt Enable bit are then used for the external interrupt. This fea- ture is selected by the USICS1 bit. 4.15.4.5 Software Interrupt The counter overflow interrupt can be used as a software interrupt triggered by a clock strobe. Atmel ATA6616/ATA6617 180 Section 4.5.1 “Clock Systems and their Distribution” on page 9132D–AUTO–12/10 ...
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... Buffer can be accessed when the CPU reads the received data. This gives the CPU time to handle other program tasks too as the controlling of the USI is not so timing critical. The USI flags as set same as when reading the USIDR register. 9132D–AUTO–12/10 Atmel ATA6616/ATA6617 ...
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... USITC strobe bit. This feature is enabled by write a one to the USICLK bit while setting an external clock source (USICS1 = 1). Note that even when no wire mode is selected (USIWM1.. the external clock input (USCK/SCL) are can still be used by the counter. Atmel ATA6616/ATA6617 182 ...
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... Data and clock inputs are not affected by the mode selected and will always have the same function. The counter and USI Data Register can therefore be clocked externally, and data input sampled, even when outputs are disabled. The relations between USIWM1:0 and the USI operation is summarized in 9132D–AUTO–12/10 Atmel ATA6616/ATA6617 ...
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... USITC strobe bit. Table 4-46 on page 185 and clock source used for the USI Data Register and the 4-bit counter. Atmel ATA6616/ATA6617 184 Relations between USIWM1..0 and the USI Operation 0 Outputs, clock hold, and start detector disabled ...
Page 185
... External, negative edge ® ATtiny87/167 and always reads as zero. Atmel ATA6616/ATA6617 4-bit Counter Clock Source No Clock Software clock strobe (USICLK) Timer/Counter0 Compare Match External, both edges External, both edges Software clock strobe (USITC) Software clock strobe (USITC) Table 4-46 USIPOS R ...
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... Asynchronous Operation • High Resolution Baud Rate Generator • Hardware Support of 8 Data Bits, Odd/Even/No Parity Bit, 1 Stop Bit Frames • Data Over-Run and Framing Error Detection Atmel ATA6616/ATA6617 186 USI Pin Position USIPOS USI Pin Position DI, SDA PB0 - (PCINT8/OC1AU) PortB ...
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... HEADER RESPONSE FRAME SLOT PROTECTED IDENTIFIER DATA-0 Field Field Response Space Atmel ATA6616/ATA6617 slave node 1 n slave task slave task LIN bus HEADER RESPONSE DATA-n CHECKSUM Field Field Inter-Byte Space Each byte field is transmitted as a serial byte, LSB first ...
Page 188
... Tx LIN Header function, • Rx LIN Header function, • LIN Response function. These functions mainly use two services: • Rx service, • Tx service. Because these two services are basically UART services, the controller is also able to switch into an UART function. Atmel ATA6616/ATA6617 188 9132D–AUTO–12/10 ...
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... The UART has an enhanced baud rate generator providing a maximum error of 2% whatever the clock frequency and the targeted baud rate. 9132D–AUTO–12/10 Atmel ATA6616/ATA6617 Section 4.16.3.4 on page 188). The Atmel ® ...
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... LIN/UART Controller Structure Figure 4-71. LIN/UART Controller Block Diagram 4.16.4.4 LIN/UART Command Overview Figure 4-72. LIN/UART Command Dependencies Atmel ATA6616/ATA6617 190 Prescaler CLK IO Sample /bit BAUD_RATE Get Byte RxD RX Synchronization Monitoring Data FIFO Tx Header IDOK Rx Header LIN Abort Automatic Return ...
Page 191
... Table 4-48 on page 191, four functions controlled by the LCMD[1..0] bits of Figure 4-72 on page (See ”Break-in-data” on page Atmel ATA6616/ATA6617 Command Comment Disable peripheral Rx Header - LIN Abort LIN Withdrawal Tx Header LCMD[2..0]=000 after Tx Rx Response LCMD[2..0]=000 after Rx Tx Response LCMD[2..0]=000 after Tx ...
Page 192
... The initialization of the checksum operator, • The transmission or the reception of ‘ • The transmission or the checking of the CHECKSUM field, • The checking of the Frame_Time_Out, • The checking of the LIN communication integrity. Atmel ATA6616/ATA6617 192 ’ data with the update of the checksum calculation, n 9132D–AUTO–12/10 ...
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... LTXOK flag of LINSIR register is cleared. It will rise at the end of the serial transmission new character has to be sent, LTXOK flag can be cleared separately (see specific flag management described in There is no transmit buffering. No error is detected by this service. 9132D–AUTO–12/10 Atmel ATA6616/ATA6617 203). 190). 205). Section 4.16.6.2 on page Table 4-48 on page 191 ...
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... LIN13 = 1: LIN 1.3 protocol. The controller checks the LIN13 bit in computing the checksum (enhanced checksum in LIN2.1 / classic checksum in LIN 1.3). This bit is irrelevant for UART commands. Atmel ATA6616/ATA6617 194 ® core reset logic signal also resets the LIN/UART controller. Another form of reset ...
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... Tx LIN LISTEN internal Rx LIN FRAME SLOT HEADER PROTECTED SYNC IDENTIFIER Field Field Node providing neither the master task, neither a slave task LIDOK Atmel ATA6616/ATA6617 4-50): TXLIN 1 RXLIN 0 RESPONSE DATA-0 DATA-n Field Field Node providing a slave task LCMD= Response CHECKSUM Field ...
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... LBT[5..0]: Least significant bits of - LINBTR register- (0-63) is the number of samplings in a LIN or UART bit (default value 32). Equation for calculating baud rate: Equation for setting LINDIV value: Note that in reception a majority vote on three samplings is made. Atmel ATA6616/ATA6617 196 , the abort command is taken into account at the end of the byte System I/O clock frequency, i/o as input clock ...
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... Write in LINBTR register LENA ? =1 =0 (LINCR bit 4) LDISR to write LBT[5..0] forced to 0x20 LDISR forced to 0 Enable re-synch. in LIN mode Atmel ATA6616/ATA6617 =1 =0 LBT[5..0] = LBT[5..0] to write (LBT[5..0] =8) min LDISR forced to 1 Disable re-synch. in LIN mode Figure 4-75 on 197 ...
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... LTXDL field will count the number of received bytes (during busy signal), • error occurs, Rx stops, the corresponding error flag is set and LTXDL will give the number of received bytes without error, • error occurs, LRXOK is set after the reception of the CHECKSUM, LRXDL will be unchanged (and LTXDL = LRXDL). Atmel ATA6616/ATA6617 198 nd rd Byte ...
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... Byte 3 DATA-1 DATA Byte DATA-0 LIN bus 4 0 LRXDL 4 LTXDL LBUSY LCMD=Tx Response Information on response (ex: error on byte) is only available at the end of the serializa- tion/de-serialization of the byte. Atmel ATA6616/ATA6617 th Byte 4 Byte DATA-3 CHECKSUM 2 3 LCMD2..0=000 Byte 3 Byte DATA-1 DATA-2 ERROR ERROR ...
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... LTOERR = LIN Time Out ERRor. A time-out error will be flagged if the MESSAGE frame is not fully completed within the maximum length T IDENTIFIER fields (see Atmel ATA6616/ATA6617 200 Section 4.16.5.13 “Interrupts” on page 202). There are eight flags: 209). A LIN slave application does not distinguish between ...