DSPIC33FJ06GS101-E/SO Microchip Technology, DSPIC33FJ06GS101-E/SO Datasheet

IC DSPIC MCU/DSP 6K 18-SOIC

DSPIC33FJ06GS101-E/SO

Manufacturer Part Number
DSPIC33FJ06GS101-E/SO
Description
IC DSPIC MCU/DSP 6K 18-SOIC
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr

Specifications of DSPIC33FJ06GS101-E/SO

Program Memory Type
FLASH
Program Memory Size
6KB (6K x 8)
Package / Case
18-SOIC (7.5mm Width)
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
13
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
13
Data Ram Size
256 B
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC33FJ06GS101-E/SO
Manufacturer:
Microchip Technology
Quantity:
135
Part Number:
DSPIC33FJ06GS101-E/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
dsPIC33FJ06GS101/X02 and
dsPIC33FJ16GSX02/X04
Data Sheet
High-Performance,
16-bit Digital Signal Controllers
Preliminary
© 2009 Microchip Technology Inc.
DS70318D

Related parts for DSPIC33FJ06GS101-E/SO

DSPIC33FJ06GS101-E/SO Summary of contents

Page 1

... Microchip Technology Inc. High-Performance, 16-bit Digital Signal Controllers Preliminary Data Sheet DS70318D ...

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... PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

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... On-Chip Flash and SRAM: • Flash Program Memory ( Kbytes) • Data SRAM ( Kbytes) • Boot and General Security for Program Flash © 2009 Microchip Technology Inc. dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Peripheral Features: • Timer/Counters Three 16-Bit Timers: - Can pair up to make one 32-bit timer • ...

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... High-Speed PWM Module Features: • Four PWM Generators with Four to Eight Outputs • Individual Time Base and Duty Cycle for each of the Eight PWM Outputs • Dead Time for Rising and Falling Edges • Duty Cycle Resolution of 1.04 ns • ...

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... Renewable Power/Pure Sine Wave Inverters • Uninterruptible Power Supply (UPS) Packaging: • 18-Pin SOIC • 28-Pin SPDIP/SOIC/QFN-S • 44-Pin TQFP/QFN See the dsPIC33FJ06GS101/X02 and Note: dsPIC33FJ16GSX02/X04 Families table for the exact peripheral features per device. © 2009 Microchip Technology Inc. ...

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... PRODUCT FAMILIES The device names, pin counts, memory sizes and peripheral availability of each device are listed below. The following pages show their pinout diagrams. dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Controller Families Device dsPIC33FJ06GS101 18 6 256 dsPIC33FJ06GS102 28 6 256 ...

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... AN0/CMP1A/RA0 AN1/CMP1B/RA1 AN2/CMP1C/CMP2A/RA2 AN3/CMP1D/CMP2B/RP0 AN4/CMP2C/RP9 AN5/CMP2D/RP10 OSC1/CLKIN/RP1 OSC2/CLKO/RP2 PGED2/DACOUT/INT0/RP3 PGEC2/EXTREF/RP4 PGED3/RP8 The RPn pins can be used by any remappable peripheral. See the “dsPIC33FJ06GS101/X02 and Note 1: dsPIC33FJ16GSX02/X04 Controller Families” table for the list of available peripherals © 2009 Microchip Technology Inc. MCLR AN0/RA0 V ...

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... AN0/CMP1A/RA0 AN1/CMP1B/RA1 AN2/CMP1C/CMP2A/RA2 AN3/CMP1D/CMP2B/RP0 AN4/CMP2C/CMP3A/RP9 (1) AN5/CMP2D/CMP3B/RP10 OSC1/CLKIN/AN6/CMP3C/CMP4A/RP1 OSC2/CLKO/AN7/CMP3D/CMP4B/RP2 (1) PGED2/DACOUT/INT0/RP3 /CN3/RB3 PGEC2/EXTREF/RP4 CN8/RB8/PGED3/RP8 (1) /CN8/RB8 The RPn pins can be used by any remappable peripheral. See the “dsPIC33FJ06GS101/X02 and Note 1: dsPIC33FJ16GSX02/X04 Controller Families” table for the list of available peripherals DS70318D-page 6 MCLR AN0/RA0 AN1/RA1 PWM1L/RA3 ...

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... OSC1/CLKIN/RP1 (1) (1) OSC2/CLKO/RP2 The RPn pins can be used by any remappable peripheral. See the “dsPIC33FJ06GS101/X02 and Note 1: dsPIC33FJ16GSX02/X04 Controller Families” table for the list of available peripherals. The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to ...

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... AN5/CMP2D/CMP3B/RP10 OSC1/CLKIN/AN6/CMP3C/CMP4A/RP1 OSC2/CLKO/AN7/CMP3D/CMP4B/RP2 The RPn pins can be used by any remappable peripheral. See the “dsPIC33FJ06GS101/X02 and Note 1: dsPIC33FJ16GSX02/X04 Controller Families” table for the list of available peripherals. The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to ...

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... PWM2L/RP14 (1) /CN14/RB14 The RPn pins can be used by any remappable peripheral. See the “dsPIC33FJ06GS101/X02 and Note 1: dsPIC33FJ16GSX02/X04 Controller Families” table for the list of available peripherals. The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to ...

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... PWM2L/RP14 (1) /CN14/RB14 11 The RPn pins can be used by any remappable peripheral. See the “dsPIC33FJ06GS101/X02 and Note 1: dsPIC33FJ16GSX02/X04 Controller Families” table for the list of available peripherals. The metal plane at the bottom of the device is not connected to any pins and is recommended to connect externally. ...

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... RP19 (1) /CN19/RC3 CAP DD ORE (1) TMS/PWM3H/RP11 /CN11/RB11 (1) TCK/PWM3L/RP12 /CN12/RB12 (1) PWM2H/RP13 /CN13/RB13 PWM2L/RP14 (1) /CN14/RB14 The RPn pins can be used by any remappable peripheral. See the “dsPIC33FJ06GS101/X02 and Note 1: dsPIC33FJ16GSX02/X04 Controller Families” table for the list of available peripherals © 2009 Microchip Technology Inc dsPIC33FJ16GS404 ...

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... DD ORE 7 TMS/PWM3H/RP11 (1) /CN11/RB11 8 TCK/PWM3L/RP12 (1) /CN12/RB12 9 (1) PWM2H/RP13 /CN13/RB13 10 (1) PWM2L/RP14 /CN14/RB14 11 The RPn pins can be used by any remappable peripheral. See the “dsPIC33FJ06GS101/X02 and Note 1: dsPIC33FJ16GSX02/X04 Controller Families” table for the list of available peripherals DS70318D-page 12 OSC2/CLKO/AN7/CMP3D/CMP4B/RP2 33 OSC1/CLKI/AN6/CMP3C/CMP4A/RP1 32 AN8/CMP4C/RP17 dsPIC33FJ16GS504 AN10/RP26 28 AN11/RP25 ...

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... Table of Contents dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Product Families .......................................................................................... 4 1.0 Device Overview ........................................................................................................................................................................ 15 2.0 Guidelines for Getting Started with 16-bit Digital Signal Controllers .......................................................................................... 19 3.0 CPU............................................................................................................................................................................................ 29 4.0 Memory Organization ................................................................................................................................................................. 41 5.0 Flash Program Memory.............................................................................................................................................................. 81 6.0 Resets ....................................................................................................................................................................................... 87 7.0 Interrupt Controller ..................................................................................................................................................................... 95 8.0 Oscillator Configuration ......................................................................................................................................................... 135 9 ...

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... TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. ...

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... X04 devices contain extensive Digital Signal Processor (DSP) functionality with a high-performance, 16-bit microcontroller (MCU) architecture. Figure 1-1 shows a general block diagram of the core and peripheral modules in the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 devices. Table 1-1 lists the functions of the various pins shown in the pinout diagrams. ...

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... FIGURE 1-1: dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 BLOCK DIAGRAM PSV & Table Data Access Control Block Interrupt Controller 8 23 PCH PCL PCU 23 Program Counter Stack Control Logic 23 Address Latch Program Memory Data Latch 24 Instruction Decode & Control Control Signals to Various Blocks ...

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... TABLE 1-1: PINOUT I/O DESCRIPTIONS Pin Buffer Pin Name Type Type AN0-AN11 I Analog CLKI I ST/CMOS CLKO O — OSC1 I ST/CMOS OSC2 I/O — CN0-CN29 I ST IC1-IC2 I ST OCFA I ST OC1-OC2 O — INT0 I ST INT1 I ST INT2 I ST RA0-RA4 I/O ...

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... TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Buffer Pin Name Type Type CMP1A I Analog CMP1B I Analog CMP1C I Analog CMP1D I Analog CMP2A I Analog CMP2B I Analog CMP2C I Analog CMP2D I Analog CMP3A I Analog CMP3B I Analog CMP3C I Analog CMP3D I Analog CMP4A I Analog ...

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... Microchip (www.microchip.com). 2.1 Basic Connection Requirements Getting started with the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 family of 16-bit Digital Signal Controllers (DSC) requires attention to a minimal set of device pin connections before proceeding with development. The following is a list of pin names, which must always be connected: • ...

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... FIGURE 2-1: RECOMMENDED MINIMUM CONNECTION MCLR C dsPIC33F 0.1 μF Ceramic 0.1 μF Ceramic 10 Ω 2.2.1 TANK CAPACITORS On boards with power traces running longer than six inches in length suggested to use a tank capacitor for integrated circuits including DSCs to supply a local power source ...

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... ICSP Pins The PGECx and PGEDx pins are used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is ...

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... Oscillator Value Conditions on Device Start-up If the PLL of the target device is enabled and configured for the device start-up oscillator, the maximum oscillator source frequency must be limited to 4 MHz < F < 8 MHz to comply with device PLL IN start-up conditions. This means that if the external oscillator frequency is outside this range, the application must start up in the FRC mode first ...

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... FIGURE 2-4: DIGITAL PFC ADC Channel FIGURE 2-5: BOOST CONVERTER IMPLEMENTATION k 1 ADC Channel © 2009 Microchip Technology Inc. I PFC | FET k 2 Driver ADC Channel PWM Output dsPIC33FJ06GS101 I PFC V INPUT FET k 2 Driver ADC PWM Channel Output dsPIC33FJ06GS101 ...

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... FIGURE 2-6: SINGLE-PHASE SYNCHRONOUS BUCK CONVERTER 12V Input k 7 ADC Channel FIGURE 2-7: MULTI-PHASE SYNCHRONOUS BUCK CONVERTER 12V Input FET k 7 Driver ADC Channel dsPIC33FJ06GS502 DS70318D-page 24 5V Output I 5V FET k Driver 1 Analog ADC Comp. Channel dsPIC33FJ06GS202 FET Driver ...

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... FIGURE 2-8: OFF-LINE UPS Push-Pull Converter V BAT GND FET FET k Driver Driver 2 PWM PWM ADC or Analog Comp ADC ADC k 6 Battery Charger © 2009 Microchip Technology Inc GND FET FET FET FET k Driver Driver Driver Driver 1 ADC PWM ...

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... FIGURE 2-9: INTERLEAVED PFC | ADC Channel ADC Channel DS70318D-page FET FET Driver Driver ADC ADC ADC PWM PWM Channel Channel Channel dsPIC33FJ06GS202 Preliminary V + OUT OUT © 2009 Microchip Technology Inc. ...

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... FIGURE 2-10: PHASE-SHIFTED FULL-BRIDGE CONVERTER Gate 3 Gate 1 S1 Gate Gate 1 FET Driver S1 Gate 2 © 2009 Microchip Technology Inc. S3 Gate 4 Gate 5 Analog Ground Gate 3 FET Driver S3 Gate 4 Preliminary Gate OUT V - OUT Gate 5 FET k 2 Driver k 1 PWM ADC PWM ...

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... DS70318D-page 28 PWM PWM PWM PWM PWM PWM PWM PWM PWM PWM Preliminary © 2009 Microchip Technology Inc. ...

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... CPU. The instruction set includes many addressing modes and is designed for optimum C compiler efficiency. For most instructions, the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 is capable of execut- ing a data (or program data) memory read, a work- ing register (data) read, a data memory write and a program (instruction) memory read per instruction cycle ...

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... Using a 17-bit by 17-bit multiplier for 16-bit by 16-bit multiplication not only allows you to perform mixed sign multiplication, it also achieves accurate results for special operations, such as (-1.0) x (-1.0). FIGURE 3-1: dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 CPU CORE BLOCK DIAGRAM PSV & Table Data Access Control Block ...

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... FIGURE 3-2: dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 PROGRAMMER’S MODEL DSP Operand Registers DSP Address Registers AD39 DSP ACCA Accumulators ACCB PC22 0 7 TBLPAG Data Table Page Address 7 0 PSVPAG OAB SAB DA SRH © 2009 Microchip Technology Inc. D15 D0 W0/WREG ...

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... CPU Control Registers REGISTER 3-1: SR: CPU STATUS REGISTER R-0 R-0 R/C bit 15 (2) (3) R/W-0 R/W-0 R/W-0 (2) IPL<2:0> bit 7 Legend Clearable bit R = Readable bit S = Settable bit W = Writable bit ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 OA: Accumulator A Overflow Status bit ...

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... REGISTER 3-1: SR: CPU STATUS REGISTER (CONTINUED) bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits 111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) ...

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... REGISTER 3-2: CORCON: CORE CONTROL REGISTER U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 R/W-1 SATA SATB SATDW bit Clearable bit Legend Readable bit W = Writable bit 0’ = Bit is cleared ‘x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ ...

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... The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 is a single-cycle instruction flow architecture; there- fore, concurrent operation of the DSP engine with MCU instruction flow is not possible. However, some MCU ALU and DSP engine resources can be used concurrently by the same instruction (for example, ED, EDAC) ...

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... TABLE 3-1: DSP INSTRUCTIONS SUMMARY Instruction CLR ED EDAC MAC MAC MOVSAC MPY MPY MPY.N MSC FIGURE 3-3: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In DS70318D-page 36 Algebraic Operation – y – y change – – 40-bit Accumulator A 40-bit Accumulator B Saturate Adder ...

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... MULTIPLIER The 17-bit x 17-bit multiplier is capable of signed or unsigned operation and can multiplex its output using a scaler to support either 1.31 fractional (Q31) or 32-bit integer results. Unsigned operands are zero-extended into the 17th bit of the multiplier input value. Signed operands are sign-extended into the 17th bit of the multiplier input value ...

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... The SA and SB bits are modified each time data passes through the adder/subtracter, but can only be cleared by the user application. When set, they indicate that the accumulator has overflowed its maximum range (bit 31 for 32-bit saturation or bit 39 for 40-bit saturation) and will be saturated (if saturation is enabled) ...

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... Data Space Write Saturation In addition to adder/subtracter saturation, writes to data space can also be saturated, but without affecting the contents of the source accumulator. The data space write saturation logic block accepts a 16-bit, 1.15 fractional value from the round logic block as its input, together with overflow status from the original source (accumulator) and the 16-bit round adder ...

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... NOTES: DS70318D-page 40 Preliminary © 2009 Microchip Technology Inc. ...

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... The exception is the use of TBLRD/TBLWT operations, which use TBLPAG<7> to permit access to the Configuration bits and Device ID sections of the configuration memory space. The memory maps for the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 devices are shown in Figure 4-1. dsPIC33FJ16GS402/404/502/504 0x000000 0x000002 ...

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... A GOTO instruction is programmed by the user application at 0x000000, with the actual address for the start of code at 0x000002. The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 devices also have two interrupt vector tables, located from 0x000004 to 0x0000FF and 0x000100 to 0x0001FF. These vector tables allow each of the device interrupt sources to be handled by separate Interrupt Service Routines (ISRs) ...

Page 45

... The first 2 Kbytes of the near data space, from 0x0000 to 0x07FF, is primarily occupied by Special Function Registers (SFRs). dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 core and peripheral modules for controlling the operation of the device. SFRs are distributed among the modules that they control, and are generally grouped together by module. ...

Page 46

... FIGURE 4-3: DATA MEMORY MAP FOR dsPIC33FJ06GS101/102 DEVICES WITH 256 BYTES OF RAM MSB Address 0x0001 2-Kbyte SFR Space 0x07FF 0x0801 0x087F 0x0881 256 bytes SRAM Space 0x08FF 0x0901 0x1FFF 0x2001 0x8001 Optionally Mapped into Program Memory 0xFFFF DS70318D-page 44 ...

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... FIGURE 4-4: DATA MEMORY MAP FOR dsPIC33FJ06GS202 DEVICE WITH 1-Kbyte RAM MSB Address 0x0001 2-Kbyte SFR Space 0x07FF 0x0801 0x09FF 0x0A01 1-Kbyte SRAM Space 0x0BFF 0x0C01 0x1FFF 0x2001 0x8001 Optionally Mapped into Program Memory 0xFFFF © 2009 Microchip Technology Inc. ...

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... FIGURE 4-5: DATA MEMORY MAP FOR dsPIC33FJ16GS402/404/502/504 DEVICES WITH 2-Kbyte RAM MSB Address 0x0001 2-Kbyte SFR Space 0x07FF 0x0801 0x0BFF 0x0C01 2-Kbyte SRAM Space 0x0FFF 0x1001 0x1FFF 0x2001 0x8001 Optionally Mapped into Program Memory 0xFFFF DS70318D-page 46 LSB 16 bits ...

Page 49

... X AND Y DATA SPACES The core has two data spaces, X and Y. These data spaces can be considered either separate (for some DSP instructions one unified linear address range (for MCU instructions). The data spaces are accessed using two Address Generation Units (AGUs) and separate data paths ...

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... DS70318D-page 48 Preliminary © 2009 Microchip Technology Inc. ...

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... DS70318D-page 50 Preliminary © 2009 Microchip Technology Inc. ...

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... DS70318D-page 52 Preliminary © 2009 Microchip Technology Inc. ...

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... SOFTWARE STACK In addition to its use as a working register, the W15 register in the dsPIC33FJ06GS101/X02 dsPIC33FJ16GSX02/X04 devices is also used as a software Stack Pointer. The Stack Pointer always points to the first available free word and grows from lower to higher addresses. It predecrements for stack pops and post-increments for stack pushes, as shown in Figure 4-6 ...

Page 74

... TABLE 4-48: FUNDAMENTAL ADDRESSING MODES SUPPORTED Addressing Mode File Register Direct Register Direct Register Indirect Register Indirect Post-Modified Register Indirect Pre-Modified Register Indirect with Register Offset (Register Indexed) Register Indirect with Literal Offset 4.3.3 MOVE AND ACCUMULATOR INSTRUCTIONS ...

Page 75

... Modulo Addressing Modulo Addressing mode is a method used to provide an automated means to support circular data buffers using hardware. The objective is to remove the need for software to perform data address boundary checks when executing tightly looped code typical in many DSP algorithms. ...

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... MODULO ADDRESSING APPLICABILITY Modulo Addressing can be applied to the Effective Address (EA) calculation associated with any W register. Address boundaries check for addresses equal to: • The upper boundary addresses for incrementing buffers • The lower boundary addresses for decrementing buffers ...

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... FIGURE 4-8: BIT-REVERSED ADDRESS EXAMPLE b15 b14 b13 b12 b11 b10 b9 b8 b15 b14 b13 b12 b11 b10 b9 b8 TABLE 4-49: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address © 2009 Microchip Technology Inc. Sequential Address Bit Locations Swapped Left-to-Right ...

Page 78

... Harvard scheme, meaning that data can also be present in the program space. To use this data success- fully, it must be accessed in a way that preserves the alignment of information in both spaces. Aside from normal execution, the dsPIC33FJ06GS101/ X02 and dsPIC33FJ16GSX02/X04 provides two methods by which program space can be accessed during operation: • ...

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... FIGURE 4-9: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION (1) Program Counter (2) Table Operations (1) Program Space Visibility (Remapping) User/Configuration Space Select Note 1: The Least Significant bit (LSb) of program space addresses is always fixed as ‘0’ to maintain word alignment of data in the program and data spaces. ...

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... DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lower word of any address within the program space without going through data space. The TBLRDH and TBLWTH instructions are the only method to read or write the upper 8 bits of a program space word as data ...

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... READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into any 16K word page of the program space. This option provides transparent access to stored constant data from the data space without the need to use special instructions (such as TBLRDL/H) ...

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... NOTES: DS70318D-page 80 Preliminary © 2009 Microchip Technology Inc. ...

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... Reference Manual”, Section 5. “Flash Programming” (DS70191), which is available from the Microchip web site (www.microchip.com). The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 devices contain internal Flash program memory for storing and executing application code. The memory is readable, writable and erasable during normal operation over the entire V range ...

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... RTSP Operation The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 Flash program memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user application to erase a page of memory, which consists of eight rows (512 instructions time, and to program one row or one word at a time. Table 24-12 shows typical erase and programming times ...

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... REGISTER 5-1: NVMCON: FLASH MEMORY CONTROL REGISTER (1) (1) R/SO-0 R/W-0 R/W-0 WR WREN WRERR bit 15 (1) U-0 R/W-0 U-0 — ERASE bit Settable Only bit Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 WR: Write Control bit 1 = Initiates a Flash memory program or erase operation ...

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... REGISTER 5-2: NVMKEY: NONVOLATILE MEMORY KEY REGISTER U-0 U-0 U-0 — — — bit 15 W-0 W-0 W-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 NVMKEY<7:0>: Key Register bits (write-only) ...

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... PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY One row of program Flash memory can be programmed at a time. To achieve this necessary to erase the 8-row erase page that contains the desired row. The general process is: 1. Read eight rows of program (512 instructions) and store in data RAM. ...

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... EXAMPLE 5-2: LOADING THE WRITE BUFFERS ; Set up NVMCON for row programming operations MOV #0x4001, W0 MOV W0, NVMCON ; Set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled MOV #0x0000, W0 MOV W0, TBLPAG MOV #0x6000, W0 ...

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... RESETS This data sheet summarizes the features Note: of the dsPIC33FJ06GS101/X02 dsPIC33FJ16GSX02/X04 devices not intended comprehensive reference source. complement the information in this data sheet, refer to the “dsPIC33F Family Reference Manual”, Section 8. “Reset” (DS70192), which is available from the Microchip web site (www ...

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... REGISTER 6-1: RCON: RESET CONTROL REGISTER R/W-0 R/W-0 U-0 TRAPR IOPUWR — bit 15 R/W-0 R/W-0 R/W-0 EXTR SWR SWDTEN bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 TRAPR: Trap Reset Flag bit Trap Conflict Reset has occurred ...

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... REGISTER 6-1: RCON: RESET CONTROL REGISTER bit 1 BOR: Brown-out Reset Flag bit Brown-out Reset has occurred Brown-out Reset has not occurred bit 0 POR: Power-on Reset Flag bit Power-up Reset has occurred Power-up Reset has not occurred Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not cause a device Reset the FWDTEN Configuration bit is ‘ ...

Page 92

... System Reset The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 families of devices have two types of Reset: • Cold Reset • Warm Reset A cold Reset is the result of a Power-on Reset (POR Brown-out Reset (BOR cold Reset, the FNOSC Configuration bits in the FOSC Configuration register select the device clock source ...

Page 93

... FIGURE 6-2: SYSTEM RESET TIMING V POR POR 1 POR Reset 2 BOR Reset SYSRST Oscillator Clock FSCM Device Status Note 1: POR Reset: A POR circuit holds the device in Reset when the power supply is turned on. The POR circuit is active until V crosses the V ...

Page 94

... TABLE 6-2: OSCILLATOR DELAY Symbol V POR threshold POR T POR extension time POR V BOR threshold BOR T BOR extension time BOR T Programmable power-up time delay PWRT T Fail-Safe Clock Monitor delay FSCM When the device exits Note: condition (begins normal operation), the device operating parameters (voltage, frequency, temperature, etc ...

Page 95

... FIGURE 6-3: BROWN-OUT SITUATIONS V DD SYSRST V DD SYSRST V dips before PWRT expires SYSRST 6.3 External Reset (EXTR) The external Reset is generated by driving the MCLR pin low. The MCLR pin is a Schmitt trigger input with an additional glitch filter. Reset pulses that are longer than the minimum pulse width will generate a Reset. Refer to Section 24.0 “ ...

Page 96

... Configuration Mismatch Reset To maintain the integrity of the Peripheral Pin Select Control registers, they are constantly monitored with shadow registers in hardware unexpected change in any of the registers occur (such as cell disturbances caused by ESD or other external events), a Configuration Mismatch Reset occurs. ...

Page 97

... Reset Sequence A device Reset is not a true exception because the interrupt controller is not involved in the Reset process. The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 device clears its registers in response to a Reset, which forces the PC to zero. The digital signal controller then begins program execution at location 0x000000. A GOTO instruction at the Reset address can redirect program execution to the appropriate start-up routine ...

Page 98

... FIGURE 7-1: dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 INTERRUPT VECTOR TABLE Reset – GOTO Instruction Reset – GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 ...

Page 99

... TABLE 7-1: INTERRUPT VECTORS Interrupt Vector Request IVT Address Number (IQR 0x000014 9 1 0x000016 10 2 0x000018 11 3 0x00001A 12 4 0x00001C 13 5 0x00001E 14 6 0x000020 15 7 0x000022 16 8 0x000024 17 9 0x000026 18 10 0x000028 19 11 0x00002A 20 12 0x00002C 21 13 0x00002E ...

Page 100

... TABLE 7-1: INTERRUPT VECTORS (CONTINUED) Interrupt Vector Request IVT Address Number (IQR) 112 104 0x0000E4 113 105 0x0000E6 114 106 0x0000E8 115 107 0x0000EA 116 108 0x0000EC 117 109 0x0000EE 118 110 0x0000F0 119 111 0x0000F2 120 112 ...

Page 101

... Interrupt Control and Status Registers The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 devices implement 27 registers for the interrupt controller: • INTCON1 • INTCON2 • IFSx • IECx • IPCx • INTTREG 7.3.1 INTCON1 AND INTCON2 Global interrupt control functions are controlled from INTCON1 and INTCON2 ...

Page 102

... REGISTER 7-1: SR: CPU STATUS REGISTER R-0 R-0 R/C bit 15 (3) (3) R/W-0 R/W-0 R/W-0 (2) (2) IPL2 IPL1 IPL0 bit 7 Legend Clearable bit R = Readable bit S = Settable bit W = Writable bit ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits ...

Page 103

... REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 NSTDIS OVAERR OVBERR bit 15 R/W-0 R/W-0 U-0 SFTACERR DIV0ERR — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 NSTDIS: Interrupt Nesting Disable bit 1 = Interrupt nesting is disabled ...

Page 104

... REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 (CONTINUED) bit 2 STKERR: Stack Error Trap Status bit 1 = Stack error trap has occurred 0 = Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘ ...

Page 105

... REGISTER 7-4: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-0 R-0 U-0 ALTIVT DISI — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit ...

Page 106

... Unimplemented: Read as ‘0’ bit 3 T1IF: Timer1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Note 1: This bit is not implemented in dsPIC33FJ06GS101/102 devices. 2: These bits are not implemented in dsPIC33FJ06GS202 devices. DS70318D-page 104 R/W-0 R/W-0 R/W-0 U1TXIF ...

Page 107

... Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Note 1: This bit is not implemented in dsPIC33FJ06GS101/102 devices. 2: These bits are not implemented in dsPIC33FJ06GS202 devices. © 2009 Microchip Technology Inc. (1) Preliminary ...

Page 108

... Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SI2C1IF: I2C1 Slave Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Note 1: This bit is not implemented in dsPIC33FJ16GS402/404 and dsPIC33FJ06GS101/102 devices. DS70318D-page 106 U-0 U-0 U-0 — ...

Page 109

... REGISTER 7-7: IFS3: INTERRUPT FLAG STATUS REGISTER 3 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-10 Unimplemented: Read as ‘0’ ...

Page 110

... Interrupt request has not occurred bit 14 PWM1IF: PWM1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 13-0 Unimplemented: Read as ‘0’ Note 1: This bit is not implemented in dsPIC33FJ06GS101/102 devices. DS70318D-page 108 U-0 U-0 U-0 — — ...

Page 111

... Interrupt request has occurred 0 = Interrupt request has not occurred Note 1: These bits are unimplemented in dsPIC33FJ06GS202 devices. 2: These bits are unimplemented in dsPIC33FJ06GS101 and dsPIC33FJ16GS502 devices. 3: These bits are unimplemented in dsPIC33FJ16GS402/404/502 devices. 4: These bits are unimplemented in dsPIC33FJ06101/102/202 devices. © 2009 Microchip Technology Inc. ...

Page 112

... ADCP2IF: ADC Pair 2 Conversion Done Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Note 1: These bits are not implemented in dsPIC33FJ06GS101/102/202 and dsPIC33FJ16GS402/402/502 devices. 2: This bit is not implemented in dsPIC33FJ06GS102/202 devices. 3: This bit is not implemented in dsPIC33FJ06GS101 devices. ...

Page 113

... Interrupt request not enabled bit 4 Unimplemented: Read as ‘0’ bit 3 T1IE: Timer1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Note 1: These bits are unimplemented in dsPIC33FJ06GS101/102 devices. 2: These bits are unimplemented in dsPIC33FJ06GS202 devices. © 2009 Microchip Technology Inc. R/W-0 R/W-0 U1TXIE U1RXIE ...

Page 114

... Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Note 1: These bits are unimplemented in dsPIC33FJ06GS101/102 devices. 2: These bits are unimplemented in dsPIC33FJ06GS202 devices. DS70318D-page 112 (1) Preliminary © 2009 Microchip Technology Inc. ...

Page 115

... Interrupt request enabled 0 = Interrupt request not enabled bit 0 SI2C1IE: I2C1 Slave Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Note 1: This bit is not implemented in dsPIC33FJ06GS101/102 and dsPIC33FJ16GS402/404 devices. © 2009 Microchip Technology Inc. U-0 U-0 U-0 — — ...

Page 116

... REGISTER 7-14: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-10 Unimplemented: Read as ‘0’ ...

Page 117

... Interrupt request is enabled 0 = Interrupt request is not enabled bit 14 PWM1IE: PWM1 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 13-0 Unimplemented: Read as ‘0’ Note 1: This bit is unimplemented in dsPIC33FJ06GS101/102 devices. © 2009 Microchip Technology Inc. U-0 U-0 U-0 — — — ...

Page 118

... PWM3IE: PWM3 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled Note 1: These bits are unimplemented in dsPIC33FJ06GS202 devices. 2: These bits are unimplemented in dsPIC33FJ06GS101 and dsPIC33FJ16GS502 devices. 3: These bits are unimplemented in dsPIC33FJ16GS402/404/502 devices. 4: These bits are unimplemented in dsPIC33FJ06101/102/202 devices. DS70318D-page 116 ...

Page 119

... ADCP2IE: ADC Pair 2 Conversion Done Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled Note 1: These bits are not implemented in dsPIC33FJ06GS101/102/202 and dsPIC33FJ16GS402/402/502 devices. 2: This bit is not implemented in dsPIC33FJ06GS102/202 devices. 3: This bit is not implemented in dsPIC33FJ06GS101 devices. © 2009 Microchip Technology Inc. ...

Page 120

... Unimplemented: Read as ‘0’ bit 2-0 INT0IP<2:0>: External Interrupt 0 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled Note 1: These bits are unimplemented in dsPIC33FJ06GS101/102 devices. DS70318D-page 118 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 (1) — ...

Page 121

... Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ Note 1: These bits are not implemented in dsPIC33FJ06GS101/202 devices. 2: These bits are not implemented in dsPIC33FJ06GS102 devices. © 2009 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 ...

Page 122

... Unimplemented: Read as ‘0’ bit 2-0 T3IP<2:0>: Timer3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled Note 1: These bits are not implemented in dsPIC33FJ06GS101/102/202 devices. DS70318D-page 120 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — ...

Page 123

... REGISTER 7-22: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3 U-0 U-0 U-0 — — — bit 15 U-0 R/W-1 R/W-0 — ADIP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 ADIP< ...

Page 124

... SI2C1IP<2:0>: I2C1 Slave Events Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled Note 1: These bits are not implemented in dsPIC33FJ06GS101/102 and dsPIC33FJ16GS402/404 devices. DS70318D-page 122 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — ...

Page 125

... REGISTER 7-24: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-3 Unimplemented: Read as ‘0’ ...

Page 126

... REGISTER 7-26: IPC14: INTERRUPT PRIORITY CONTROL REGISTER 14 U-0 U-0 U-0 — — — bit 15 U-0 R/W-1 R/W-0 — PSEMIP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 PSEMIP< ...

Page 127

... PWM1IP<2:0>: PWM1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7-0 Unimplemented: Read as ‘0’ Note 1: These bits are not implemented in dsPIC33FJ06GS101/102 devices. © 2009 Microchip Technology Inc. R/W-0 U-0 R/W-1 (1) — U-0 U-0 — ...

Page 128

... REGISTER 7-29: IPC24: INTERRUPT PRIORITY CONTROL REGISTER 24 U-0 U-0 U-0 — — — bit 15 U-0 R/W-1 R/W-0 — PWM4IP bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 PWM4IP< ...

Page 129

... Interrupt is priority 7 (highest priority) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11-01 Unimplemented: Read as ‘0’ Note 1: These bits are not implemented in dsPIC33FJ06GS101/102 and dsPIC33FJ16GS402/404 devices. © 2009 Microchip Technology Inc. R/W-0 U-0 U-0 (1) — U-0 ...

Page 130

... AC3IP<2:0>: Analog Comparator 3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled Note 1: These bits are not implemented in dsPIC33FJ06GS202 and dsPIC33FJ16GS402/404 devices. 2: These bits are not implemented in dsPIC33FJ06GS101/102 devices. DS70318D-page 128 U-0 U-0 U-0 — — R/W-0 ...

Page 131

... REGISTER 7-32: IPC27: INTERRUPT PRIORITY CONTROL REGISTER 27 U-0 R/W-1 R/W-0 — ADCP1IP<2:0> bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 ADCP1IP< ...

Page 132

... Interrupt is priority 1 000 = Interrupt source is disabled Note 1: These bits are not implemented in dsPIC33FJ06GS101 devices. 2: These bits are not implemented in dsPIC33FJ06GS102 devices. 3: These bits are not implemented in dsPIC33FJ06GS202 devices. 4: These bits are implemented in dsPIC33FJ16GS504 devices only. DS70318D-page 130 ...

Page 133

... REGISTER 7-34: IPC29: INTERRUPT PRIORITY CONTROL REGISTER 29 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-3 Unimplemented: Read as ‘0’ ...

Page 134

... REGISTER 7-35: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER U-0 U-0 U-0 — — — bit 15 U-0 R-0 R-0 — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 ILR< ...

Page 135

... Interrupt Setup Procedures 7.4.1 INITIALIZATION Complete the following steps to configure an interrupt source at initialization: 1. Set the NSTDIS bit (INTCON1<15>) if nested interrupts are not desired. 2. Select the user-assigned priority level for the interrupt source by writing the control bits in the appropriate IPCx register ...

Page 136

... NOTES: DS70318D-page 134 Preliminary © 2009 Microchip Technology Inc. ...

Page 137

... Microchip web site (www.microchip.com). The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 oscillator system provides: • External and internal oscillator options as clock sources FIGURE 8-1: dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 OSCILLATOR SYSTEM DIAGRAM Primary Oscillator OSC1 (2) R OSC2 POSCMD<1:0> FRC ...

Page 138

... The output of the oscillator (or the output of the PLL if a PLL mode has been selected generate the device instruction clock (F peripheral clock time base (F operating speed of the device and speeds MHz are supported by the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 architecture. Instruction execution speed or device operating frequency given by Equation 8-1. ...

Page 139

... PLL output frequency ( the range of 12.5 MHz to 80 MHz, which OSC generates device operating speeds of 6.25-40 MIPS. FIGURE 8-2: dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 PLL BLOCK DIAGRAM Source (Crystal, External PLLPRE Clock or Internal RC) Divide by Note 1: This frequency range must be satisfied at all times. ...

Page 140

... REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER U-0 R-0 R-0 — COSC<2:0> bit 15 R/W-0 R/W-0 R-0 CLKLOCK IOLOCK LOCK bit Value set from Configuration bits on POR Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ ...

Page 141

... REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER bit 3 CF: Clock Fail Detect bit (read/clear by application FSCM has detected clock failure 0 = FSCM has not detected clock failure bit 2-1 Unimplemented: Read as ‘0’ bit 0 OSWEN: Oscillator Switch Enable bit 1 = Request oscillator switch to selection specified by NOSC<2:0> bits 0 = Oscillator switch is complete Note 1: Writes to this register require an unlock sequence. Refer to Section 42. “ ...

Page 142

... REGISTER 8-2: CLKDIV: CLOCK DIVISOR REGISTER R/W-0 R/W-0 R/W-1 ROI DOZE<2:0> bit 15 R/W-0 R/W-1 U-0 PLLPOST<1:0> — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 ROI: Recover on Interrupt bit 1 = Interrupts will clear the DOZEN bit and the processor clock/peripheral clock ratio is set to 1:1 ...

Page 143

... REGISTER 8-3: PLLFBD: PLL FEEDBACK DIVISOR REGISTER U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 R/W-1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-9 Unimplemented: Read as ‘0’ bit 8-0 PLLDIV<8:0>: PLL Feedback Divisor bits (also denoted as ‘M’, PLL multiplier) ...

Page 144

... REGISTER 8-4: OSCTUN: FRC OSCILLATOR TUNING REGISTER U-0 U-0 U-0 — — — bit 15 U-0 U-0 R/W-0 — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 TUN< ...

Page 145

... REGISTER 8-5: ACLKCON: AUXILIARY CLOCK DIVISOR CONTROL REGISTER R/W-0 R-0 R/W-0 ENAPLL APLLCK SELACLK bit 15 R/W-0 R/W-0 U-0 ASRCSEL FRCSEL — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 ENAPLL: Auxiliary PLL Enable bit ...

Page 146

... REGISTER 8-6: REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER R/W-0 U-0 R/W-0 ROON — ROSIDL bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 ROON: Reference Oscillator Output Enable bit ...

Page 147

... Applications are free to switch among any of the four clock sources (primary, LP, FRC and LPRC) under software control at any time. To limit the possible side effects of this flexibility, dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 devices have a safeguard lock built into the switch process. Primary oscillator mode has three different ...

Page 148

... NOTES: DS70318D-page 146 Preliminary © 2009 Microchip Technology Inc. ...

Page 149

... PWRSAV #IDLE_MODE ; Put the device into IDLE mode © 2009 Microchip Technology Inc. 9.2 Instruction-Based Power-Saving Modes The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ and X04 devices have two special power-saving modes that families of are entered through the execution of a special PWRSAV instruction. Sleep mode stops clock operation and halts all To code execution ...

Page 150

... IDLE MODE The following occur in Idle mode: • The CPU stops executing instructions. • The WDT is automatically cleared. • The system clock source remains active. By default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see Section 9.4 “ ...

Page 151

... REGISTER 9-1: PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1 U-0 U-0 R/W-0 — — T3MD bit 15 R/W-0 U-0 R/W-0 I2C1MD — U1MD bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ ...

Page 152

... REGISTER 9-2: PMD2: PERIPHERAL MODULE DISABLE CONTROL REGISTER 2 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-10 Unimplemented: Read as ‘0’ ...

Page 153

... REGISTER 9-3: PMD3: PERIPHERAL MODULE DISABLE CONTROL REGISTER 3 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-11 Unimplemented: Read as ‘0’ ...

Page 154

... REGISTER 9-5: PMD6: PERIPHERAL MODULE DISABLE CONTROL REGISTER 6 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-12 Unimplemented: Read as ‘0’ ...

Page 155

... REGISTER 9-6: PMD7: PERIPHERAL MODULE DISABLE CONTROL REGISTER 7 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-12 Unimplemented: Read as ‘0’ ...

Page 156

... NOTES: DS70318D-page 154 Preliminary © 2009 Microchip Technology Inc. ...

Page 157

... I/O PORTS This data sheet summarizes the features Note: of the dsPIC33FJ06GS101/X02 dsPIC33FJ16GSX02/X04 devices not intended comprehensive reference source. complement the information in this data sheet, refer to the “dsPIC33F Family Reference Manual”, Section 10. “I/O Ports” (DS70193), which is available on Microchip web site (www ...

Page 158

... OPEN-DRAIN CONFIGURATION In addition to the PORT, LAT and TRIS registers for data control, some digital-only port pins can also be individually configured for either digital or open-drain output. This is controlled by the Open-Drain Control register, ODCx, associated with each port. Setting any of the bits configures the corresponding pin to act as an open-drain output ...

Page 159

... Peripheral Pin Select Peripheral pin select configuration enables peripheral set selection and placement on a wide range of I/O pins. By increasing the pinout options available on a particular device, programmers can better tailor the microcontroller to their entire application, rather than trimming the application to fit the device ...

Page 160

... TABLE 10-1: SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION) Input Name External Interrupt 1 External Interrupt 2 Timer1 External Clock Timer2 External Clock Timer3 External Clock Input Capture 1 Input Capture 2 Output Compare Fault A UART1 Receive UART1 Clear To Send SPI Data Input 1 ...

Page 161

... Output Mapping In contrast to inputs, the outputs of the peripheral pin select options are mapped on the basis of the pin. In this case, a control register associated with a particular pin dictates the peripheral output to be mapped. The RPORx registers are used to control output mapping. ...

Page 162

... Virtual Pins dsPIC33FJ06GS101/X02 dsPIC33FJ16GSX02/X04 devices support four virtual RPn pins (RP32, RP33, RP34 and RP35), which are identical in functionality to all other RPn pins, with the exception of pinouts. These four pins are internal to the devices and are not connected to a physical device pin. ...

Page 163

... Peripheral Pin Select Registers The dsPIC33FJ06GS101/X02 dsPIC33FJ16GSX02/X04 families of devices implement 34 registers for remappable peripheral configuration: • 15 Input Remappable Peripheral Registers • 19 Output Remappable Peripheral Registers Input and output register values can only Note: be changed if OSCCON<IOLOCK> See Section 10.4.3.1 “Control Register Lock” ...

Page 164

... REGISTER 10-2: RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1 U-0 U-0 U-0 — — — bit 15 U-0 U-0 R/W-1 — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-6 Unimplemented: Read as ‘0’ ...

Page 165

... REGISTER 10-3: RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3 U-0 U-0 R/W-1 — — bit 15 U-0 U-0 R/W-1 — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 T3CKR< ...

Page 166

... REGISTER 10-4: RPINR7: PERIPHERAL PIN SELECT INPUT REGISTER 7 U-0 U-0 R/W-1 — — bit 15 U-0 U-0 R/W-1 — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 IC2R< ...

Page 167

... REGISTER 10-5: RPINR11: PERIPHERAL PIN SELECT INPUT REGISTER 11 U-0 U-0 U-0 — — — bit 15 U-0 U-0 R/W-1 — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-6 Unimplemented: Read as ‘0’ ...

Page 168

... REGISTER 10-6: RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18 U-0 U-0 R/W-1 — — bit 15 U-0 U-0 R/W-1 — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 U1CTSR< ...

Page 169

... REGISTER 10-7: RPINR20: PERIPHERAL PIN SELECT INPUT REGISTER 20 U-0 U-0 R/W-1 — — bit 15 U-0 U-0 R/W-1 — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 SCK1R< ...

Page 170

... REGISTER 10-8: RPINR21: PERIPHERAL PIN SELECT INPUT REGISTER 21 U-0 U-0 U-0 — — — bit 15 U-0 U-0 R/W-1 — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-6 Unimplemented: Read as ‘0’ ...

Page 171

... REGISTER 10-9: RPINR29: PERIPHERAL PIN SELECT INPUT REGISTER 29 U-0 U-0 R/W-1 — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ ...

Page 172

... REGISTER 10-10: RPINR30: PERIPHERAL PIN SELECT INPUT REGISTER 30 U-0 U-0 R/W-1 — — bit 15 U-0 U-0 R/W-1 — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 FLT3R< ...

Page 173

... REGISTER 10-11: RPINR31: PERIPHERAL PIN SELECT INPUT REGISTER 31 U-0 U-0 R/W-1 — — bit 15 U-0 U-0 R/W-1 — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 FLT5R< ...

Page 174

... REGISTER 10-12: RPINR32: PERIPHERAL PIN SELECT INPUT REGISTER 32 U-0 U-0 R/W-1 — — bit 15 U-0 U-0 R/W-1 — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 FLT7R< ...

Page 175

... REGISTER 10-13: RPINR33: PERIPHERAL PIN SELECT INPUT REGISTER 33 U-0 U-0 R/W-1 — — bit 15 U-0 U-0 R/W-1 — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 SYNCI1R< ...

Page 176

... REGISTER 10-14: RPINR34: PERIPHERAL PIN SELECT INPUT REGISTER 34 U-0 U-0 U-0 — — — bit 15 U-0 U-0 R/W-1 — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-6 Unimplemented: Read as ‘0’ ...

Page 177

... REGISTER 10-16: RPOR1: PERIPHERAL PIN SELECT OUTPUT REGISTER 1 U-0 U-0 R/W-0 — — bit 15 U-0 U-0 R/W-0 — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP3R< ...

Page 178

... REGISTER 10-18: RPOR3: PERIPHERAL PIN SELECT OUTPUT REGISTER 3 U-0 U-0 R/W-0 — — bit 15 U-0 U-0 R/W-0 — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP7R< ...

Page 179

... REGISTER 10-20: RPOR5: PERIPHERAL PIN SELECT OUTPUT REGISTER 5 U-0 U-0 R/W-0 — — bit 15 U-0 U-0 R/W-0 — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP11R< ...

Page 180

... REGISTER 10-22: RPOR7: PERIPHERAL PIN SELECT OUTPUT REGISTER 7 U-0 U-0 R/W-0 — — bit 15 U-0 U-0 R/W-0 — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP15R< ...

Page 181

... REGISTER 10-24: RPOR9: PERIPHERAL PIN SELECT OUTPUT REGISTER 9 U-0 U-0 R/W-0 — — bit 15 U-0 U-0 R/W-0 — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP19R< ...

Page 182

... REGISTER 10-26: RPOR11: PERIPHERAL PIN SELECT OUTPUT REGISTER 11 U-0 U-0 R/W-0 — — bit 15 U-0 U-0 R/W-0 — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP23R< ...

Page 183

... REGISTER 10-28: RPOR13: PERIPHERAL PIN SELECT OUTPUT REGISTER 13 U-0 U-0 R/W-0 — — bit 15 U-0 U-0 R/W-0 — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP27R< ...

Page 184

... REGISTER 10-30: RPOR16: PERIPHERAL PIN SELECT OUTPUT REGISTER 16 U-0 U-0 R/W-0 — — bit 15 U-0 U-0 R/W-0 — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP33R< ...

Page 185

... TIMER1 This data sheet summarizes the features of Note: the dsPIC33FJ06GS101/X02 dsPIC33FJ16GSX02/X04 devices not intended comprehensive reference complement the information in this data sheet, refer to the “dsPIC33F Family Reference Manual”, Section 11. “Timers” (DS70205), which is available from the Microchip web site (www ...

Page 186

... REGISTER 11-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 U-0 R/W-0 TON — TSIDL bit 15 U-0 R/W-0 R/W-0 — TGATE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 TON: Timer1 On bit 1 = Starts 16-bit Timer1 0 = Stops 16-bit Timer1 bit 14 Unimplemented: Read as ‘ ...

Page 187

... TIMER2/3 FEATURES This data sheet summarizes the features Note: of the dsPIC33FJ06GS101/X02 dsPIC33FJ16GSX02/X04 devices not intended comprehensive reference complement the information in this data sheet, refer to the “dsPIC33F Family Reference Manual”, Section 11. “Timers” (DS70205), which is available on the Micro- chip web site (www ...

Page 188

... The Timer2/3 module can operate in one of the following modes: • Timer mode • Gated Timer mode • Synchronous Counter mode In Timer and Gated Timer modes, the input clock is derived from the internal instruction cycle clock (F In Synchronous Counter mode, the input clock is derived from the external clock input at the TxCK pin ...

Page 189

... FIGURE 12-3: 32-BIT TIMER BLOCK DIAGRAM Gate Sync Prescaler F CY (/n) TCKPS<1:0> Prescaler Sync (/n) TxCK TCKPS<1:0> Note 1: Timerx is a Type B Timer (x = 2). 2: Timery is a Type C Timer (y = 3). © 2009 Microchip Technology Inc. Falling Edge Detect PRy PRx Comparator 10 lsw ...

Page 190

... REGISTER 12-1: TxCON: TIMER CONTROL REGISTER ( R/W-0 U-0 R/W-0 TON — TSIDL bit 15 U-0 R/W-0 R/W-0 — TGATE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 TON: Timerx On bit When T32 = 1 (in 32-Bit Timer mode): ...

Page 191

... REGISTER 12-2: TyCON: TIMER CONTROL REGISTER ( R/W-0 U-0 R/W-0 (2) TON — TSIDL bit 15 U-0 R/W-0 R/W-0 (2) — TGATE TCKPS<1:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set (2) bit 15 TON: Timery On bit 1 = Starts 16-bit Timer ...

Page 192

... NOTES: DS70318D-page 190 Preliminary © 2009 Microchip Technology Inc. ...

Page 193

... INPUT CAPTURE This data sheet summarizes the features Note: of the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 devices not intended comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33F Family Reference Manual”, Section 12. “Input Capture” (DS70198), which is available ...

Page 194

... Input Capture Registers REGISTER 13-1: ICxCON: INPUT CAPTURE x CONTROL REGISTER ( U-0 U-0 R/W-0 — — ICSIDL bit 15 R/W-0 R/W-0 R/W-0 ICTMR ICI<1:0> bit Hardware Clearable bit Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘ ...

Page 195

... OUTPUT COMPARE This data sheet summarizes the features Note: of the dsPIC33FJ06GS101/X02 dsPIC33FJ16GSX02/X04 devices not intended comprehensive reference source. complement the information in this data sheet, refer to the “dsPIC33F Family Reference Manual”, Section 13. “Output Compare” (DS70209), which is available ...

Page 196

... Output Compare Modes Configure the Output Compare modes by setting the appropriate Output Compare Mode (OCM<2:0>) bits in the Output Compare Control (OCxCON<2:0>) register. Table 14-1 lists the different bit settings for the Output Compare modes. Figure 14-2 illustrates the output compare operation for various modes ...

Page 197

... REGISTER 14-1: OCxCON: OUTPUT COMPARE x CONTROL REGISTER ( U-0 U-0 R/W-0 — — OCSIDL bit 15 U-0 U-0 U-0 — — — bit Hardware Clearable bit Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ ...

Page 198

... NOTES: DS70318D-page 196 Preliminary © 2009 Microchip Technology Inc. ...

Page 199

... HIGH-SPEED PWM This data sheet summarizes the features Note: of the dsPIC33FJ06GS101/X02 dsPIC33FJ16GSX02/X04 devices not intended comprehensive reference source. complement the information in this data sheet, refer to the “dsPIC33F Family Reference Manual”, “High- Speed PWM” (DS70323), which is available on the Microchip web site (www ...

Page 200

... FIGURE 15-1: SIMPLIFIED CONCEPTUAL BLOCK DIAGRAM OF HIGH-SPEED PWM Pin and Mode Control PWMCONx Control for Blanking External Input Signals LEBCONx ADC Trigger Control TRGCONx Dead-Time Control ALTDTRx, DTRx PWM Enable and Mode Control PTCON PDC1 MUX PWM GEN 1 ...

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