AT32UC3L016-D3UR Atmel, AT32UC3L016-D3UR Datasheet

MCU AVR32 16KB FLASH 48TLLGA

AT32UC3L016-D3UR

Manufacturer Part Number
AT32UC3L016-D3UR
Description
MCU AVR32 16KB FLASH 48TLLGA
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheet

Specifications of AT32UC3L016-D3UR

Core Processor
AVR
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, PWM, WDT
Number Of I /o
36
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-TLLGA
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SPI, TWI, USART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
36
Number Of Timers
7
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL
Development Tools By Supplier
AT32UC3L-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 9 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Features
High Performance, Low Power Atmel
picoPower
Multi-hierarchy Bus System
Internal High-speed Flash
Internal High-speed SRAM, Single-cycle Access at Full Speed
Interrupt Controller (INTC)
External Interrupt Controller (EIC)
Peripheral Event System for Direct Peripheral to Peripheral Communication
System Functions
Windowed Watchdog Timer (WDT)
Asynchronous Timer (AST) with Real-time Clock Capability
Frequency Meter (FREQM) for Accurate Measuring of Clock Frequency
Six 16-bit Timer/Counter (TC) Channels
PWM Channels on All I/O Pins (PWMA)
Four Universal Synchronous/Asynchronous Receiver/Transmitters (USART)
One Master/Slave Serial Peripheral Interfaces (SPI) with Chip Select Signals
Two Master and Two Slave Two-wire Interface (TWI), 400kbit/s I
One 8-channel Analog-to-digital Converter (ADC) with up to 12 Bits Resolution
– Compact Single-cycle RISC Instruction Set including DSP Instructions
– Read Modify Write Instructions and Atomic Bit Manipulation
– Performance
– Memory Protection Unit (MPU)
– High-performance Data Transfers on Separate Buses for Increased Performance
– 12 Peripheral DMA Channels improve Speed for Peripheral Communication
– 64Kbytes, 32Kbytes, and 16Kbytes Versions
– Single-cycle Access up to 25MHz
– FlashVault
– Prefetch Buffer Optimizing Instruction Execution at Maximum Speed
– 100,000 Write Cycles, 15-year Data Retention Capability
– Flash Security Locks and User Defined Configuration Area
– 16Kbytes (64Kbytes and 32Kbytes Flash), or 8Kbytes (16Kbytes Flash)
– Autovectored Low Latency Interrupt Service with Programmable Priority
– Power and Clock Manager
– SleepWalking
– Internal System RC Oscillator (RCSYS)
– 32KHz Oscillator
– Multipurpose Oscillator and Digital Frequency Locked Loop (DFLL)
– Counter or Calendar Mode Supported
– External Clock Inputs, PWM, Capture and Various Counting Capabilities
– 8-bit PWM up to 150MHz Source Clock
– Independent Baudrate Generator, Support for SPI
– Support for Hardware Handshaking
– Up to 15 SPI Slaves can be Addressed
– Internal Temperature Sensor
User Applications
• Up to 64DMIPS Running at 50MHz from Flash (1 Flash Wait State)
• Up to 36DMIPS Running at 25MHz from Flash (0 Flash Wait State)
• Secure Access Unit (SAU) providing User Defined Peripheral Protection
®
Technology for Ultra-low Power Consumption
Technology Allows Pre-programmed Secure Library Support for End
Power Saving Control
®
32-bit AVR
®
Microcontroller
2
C-compatible
32-bit AVR
Microcontroller
AT32UC3L064
AT32UC3L032
AT32UC3L016
Preliminary
32099F–11/2010
®

Related parts for AT32UC3L016-D3UR

AT32UC3L016-D3UR Summary of contents

Page 1

... SPI Slaves can be Addressed • Two Master and Two Slave Two-wire Interface (TWI), 400kbit/s I • One 8-channel Analog-to-digital Converter (ADC) with Bits Resolution – Internal Temperature Sensor ® ® 32-bit AVR Microcontroller 2 C-compatible ® 32-bit AVR Microcontroller AT32UC3L064 AT32UC3L032 AT32UC3L016 Preliminary 32099F–11/2010 ...

Page 2

... Single-pin Programming Trace and Debug Interface Muxed with Reset Pin ™ – NanoTrace Provides Trace Capabilities through JTAG or aWire Interface • 48-pin TQFP/QFN/TLLGA (36 GPIO Pins) • Five High-drive I/O Pins • Single 1.62-3.6 V Power Supply 32099F–11/2010 ® ® ® ® QTouch and Atmel AVR QMatrix AT32UC3L016/32/64 ® Touch Acquisition 2 ...

Page 3

... The AST can operate in counter mode or calendar mode. The Frequency Meter (FREQM) allows accurate measuring of a clock frequency by comparing known reference clock. 32099F–11/2010 ® ® AVR AT32UC3L is a complete System-on-chip microcontroller based on the AT32UC3L016/32/64 3 ...

Page 4

... The NanoTrace interface enables trace feature for aWire- or JTAG-based debuggers. The sin- gle-pin aWire interface allows all features available through the JTAG interface to be accessed through the RESET pin, allowing the JTAG pins to be used for GPIO or peripherals. 32099F–11/2010 ® ® (AKS ) technology for unambiguous detection of key events. The easy-to-use AT32UC3L016/32/64 4 ...

Page 5

... INTERFACE XOUT32 OSC0 DFLL INTERRUPT CONTROLLER EXTERNAL INTERRUPT EXTINT[5..1] CONTROLLER NMI PWM CONTROLLER PWMA[35..0] ASYNCHRONOUS TIMER WATCHDOG TIMER FREQUENCY METER AT32UC3L016/32/64 LOCAL BUS INTERFACE AVR32UC CPU MEMORY PROTECTION UNIT 16/8 KB SRAM INSTR DATA INTERFACE INTERFACE 64/32/16 KB HIGH SPEED FLASH BUS MATRIX ...

Page 6

... Max Frequency Packages 32099F–11/2010 Configuration Summary AT32UC3L064 64KB 16KB Digital Frequency Locked Loop 40-150MHz (DFLL) Crystal Oscillator 3-16MHz (OSC0) Crystal Oscillator 32KHz (OSC32K) RC Oscillator 120MHz (RC120M) RC Oscillator 115kHz (RCSYS) RC Oscillator 32kHz (RC32K) TQFP48/QFN48/TLLGA48 AT32UC3L016/32/64 AT32UC3L032 AT32UC3L016 32KB 16KB 16KB 8KB ...

Page 7

... The device pins are multiplexed with peripheral functions as described in Figure 3-1. PA15 PA16 PA17 PA19 PA18 VDDIO GND PB11 GND PA10 PA12 VDDIO 32099F–11/2010 TQFP48/QFN48 Pinout AT32UC3L016/32/64 Section 3.2. 24 PA21 23 PB10 22 RESET_N 21 PB04 20 PB05 19 GND 18 VDDCORE 17 VDDIN 16 PB01 15 PA07 14 PA01 13 PA02 7 ...

Page 8

... Figure 3-2. PA16 PA17 PA19 PA18 VDDIO GND PB11 GND PA10 PA12 VDDIO 32099F–11/2010 TLLGA48 Pinout AT32UC3L016/32/64 24 PA21 23 PB10 22 RESET_N 21 PB04 20 PB05 19 GND 18 VDDCORE 17 VDDIN 16 PB01 15 PA07 14 PA01 8 ...

Page 9

... GLOC AD[1] CLK1 IN[6] ADCIFB TC0 GLOC AD[2] CLK0 IN[5] TC0 USART2 TWIMS1 A1 CTS TWD ADCIFB TC0 GLOC AD[4] B1 IN[4] AT32UC3L016/32/64 GPIO Function PWMA SCIF PWMA[0] GCLK[0] PWMA ACIFB TWIMS0 PWMA[1] ACAP[0] TWALM PWMA ACIFB USART0 PWMA[2] ACBP[0] CLK PWMA ACIFB ...

Page 10

... TC1 USART1 USART3 CLK0 TXD CLK TC1 USART1 CLK1 RXD TC1 TWIMS1 CLK2 TWALM for a description of the various peripheral signals. ”Electrical Characteristics” on page 782 AT32UC3L016/32/64 TWIMS1 PWMA TWALM PWMA[19] GLOC PWMA SCIF IN[3] PWMA[20] RC32OUT ADCIFB PWMA PWMA TRIGGER PWMA[21] ...

Page 11

... JTAG debug port OSC0, OSC32 JTAG Pinout 48-pin Pin Name 11 PA00 14 PA01 13 PA02 4 PA03 Nexus OCD AUX Port Connections AXS=1 AXS=0 PA05 PB08 PA10 PB00 PA18 PB04 PA17 PB05 AT32UC3L016/32/64 for a description of the electrical proper- JTAG Pin TCK TMS TDO TDI 11 ...

Page 12

... PA20 Table 3-6 are not mapped to the normal GPIO functions.The aWire DATA Section 6.1.4 on page 40 Other Functions 48-pin Pin 27 PA11 22 RESET_N 11 PA00 AT32UC3L016/32/64 Pin Oscillator Function XIN0 XIN32 XIN32_2 XOUT0 XOUT32 XOUT32_2 for constraints on the WAKE_N pin. Function WAKE_N aWire DATA ...

Page 13

... ADC Interface - ADCIFB Analog Output Output Input aWire - AW I/O I/O Capacitive Touch Module - CAT I/O I/O Analog Output Input Output External Interrupt Controller - EIC Input Input Glue Logic Controller - GLOC Input Output JTAG module - JTAG Input Input Output AT32UC3L016/32/64 Active Level Comments 13 ...

Page 14

... Analog Analog Analog Serial Peripheral Interface - SPI I/O I/O I/O I/O Timer/Counter - TC0, TC1 I/O I/O I/O I/O I/O I/O Input Input Input Two-wire Interface - TWIMS0, TWIMS1 I/O I/O I/O AT32UC3L016/32/64 Low Not all channels support open drain mode Low Low 14 ...

Page 15

... Power Input Power Input Ground Ground Auxiliary Port - AUX Output Output Output Input Low Output Low General Purpose I/O pin I/O I/O AT32UC3L016/32/64 Comments 1.62V to 1.98V 1.62V to 3.6V. VDDIO should always be equal to or lower than VDDIN. 1.62V to 1.98V 1.62V to 1.98V (1) 1.62V to 3.6V 15 ...

Page 16

... High-Drive Pins The five pins PA02, PA06, PA08, PA09, and PB01 have high-drive output capabilities. Refer to Section 32. on page 782 32099F–11/2010 Section 3.2.3 on page 11 for the JTAG port connections. Section 3.2 on page for electrical characteristics. AT32UC3L016/32/64 9). As required by the SMBus specification, 16 ...

Page 17

... ADC inputs, the voltage applied to the pin must not exceed 1.98V. Internal circuitry ensures that the pin cannot be used as an analog input pin when the I/O drives to VDD. When the pins are not used for ADC inputs, the pins may be driven to the full I/O voltage range. 32099F–11/2010 AT32UC3L016/32/64 17 ...

Page 18

... The larger format increases performance, allowing an addition and a data move in the same instruction in a single cycle. Load and store instructions have several different formats in order to reduce code size and speed up execution. 32099F–11/2010 AT32UC3L016/32/64 TM technology 18 ...

Page 19

... Details on which devices that are mapped into the local bus space is given in the CPU Local Bus section in the Memories chapter. Figure 4-1 on page 20 32099F–11/2010 displays the contents of AVR32UC. AT32UC3L016/32/64 19 ...

Page 20

... Figure 4-2 on page 21 32099F–11/2010 Overview of the AVR32UC CPU OCD system AVR32UC CPU pipeline High Speed High Speed Bus master shows an overview of the AVR32UC pipeline stages. AT32UC3L016/32/64 Power/ Reset control MPU Data memory controller High CPU Local Speed Bus ...

Page 21

... AVR32UC does not support unaligned accesses, except for doubleword accesses. AVR32UC is able to perform word-aligned st.d and ld.d. Any other unaligned memory access will cause an 32099F–11/2010 The AVR32UC Pipeline Regfile IF ID Read Prefetch unit Decode unit AT32UC3L016/32/64 MUL Multiply unit Regfile ALU ALU unit write Load-store LS unit ...

Page 22

... The Architecture Revision field in the CONFIG0 system register identifies which architecture revision is implemented in a specific device. AVR32UC CPU revision 3 is fully backward-compatible with revisions 1 and 2, ie. code compiled for revision binary-compatible with revision 3 CPUs. 32099F–11/2010 Instructions with Unaligned Reference Support Supported Alignment Word Word AT32UC3L016/32/64 22 ...

Page 23

... 4-5. The lower word contains the and Q condition code flags and the R, T, The Status Register High Halfword - - - AT32UC3L016/32/64 INT2 INT3 Exception Bit 31 Bit 0 Bit 31 Bit 0 Bit 31 Bit SP_SYS SP_SYS SP_SYS R12 R12 R12 R11 R11 R11 R10 R10 R10 R9 R9 ...

Page 24

... Overview of Execution Modes, their Priorities and Privilege Levels. Mode Security Non Maskable Interrupt Privileged Exception Privileged Interrupt 3 Privileged Interrupt 2 Privileged Interrupt 1 Privileged Interrupt 0 Privileged Supervisor Privileged Application Unprivileged AT32UC3L016/32/64 Bit Bit name Initial value Carry Zero Sign Overflow Saturation Lock ...

Page 25

... Return Status Register for Debug mode 52 RAR_SUP Unused in AVR32UC 56 RAR_INT0 Unused in AVR32UC 60 RAR_INT1 Unused in AVR32UC 64 RAR_INT2 Unused in AVR32UC 68 RAR_INT3 Unused in AVR32UC 72 RAR_EX Unused in AVR32UC 76 RAR_NMI Unused in AVR32UC 80 RAR_DBG Return Address Register for Debug mode 84 JECR Unused in AVR32UC 88 JOSP Unused in AVR32UC 92 JAVA_LV0 Unused in AVR32UC AT32UC3L016/32/64 25 ...

Page 26

... MPU Address Register region 3 336 MPUAR4 MPU Address Register region 4 340 MPUAR5 MPU Address Register region 5 344 MPUAR6 MPU Address Register region 6 348 MPUAR7 MPU Address Register region 7 352 MPUPSR0 MPU Privilege Select Register region 0 356 MPUPSR1 MPU Privilege Select Register region 1 AT32UC3L016/32/64 26 ...

Page 27

... Secure State Stack Pointer System Register 436 SS_SP_APP Secure State Stack Pointer Application Register 440 SS_RAR Secure State Return Address Register 444 SS_RSR Secure State Return Status Register 448-764 Reserved Reserved for future use 768-1020 IMPL IMPLEMENTATION DEFINED Table 4-4 on page AT32UC3L016/32/64 31. Most of the handlers are 27 ...

Page 28

... Program Counter. If the rete instruction returns from INT0, INT1, INT2, or INT3, registers R8-R12 and LR are also popped from the system stack. The restored Status Register contains information allowing the core to resume operation in the previous execution mode. This concludes the event handling. 32099F–11/2010 31, is loaded into the Program Counter. AT32UC3L016/32/64 Table 4 ...

Page 29

... If several events occur on the same instruction, they are handled in a prioritized way. The priority ordering is presented in locations in the pipeline, the events on the oldest instruction are always handled before any events on any younger instruction, even if the younger instruction has events of higher priority 32099F–11/2010 AT32UC3L016/32/64 Table 4-4 on page 31. If events occur on several instructions at different 29 ...

Page 30

... An instruction B is younger than an instruction was sent down the pipeline later than A. The addresses and priority of simultaneous events are shown in the exceptions are unused in AVR32UC since it has no MMU, coprocessor interface, or floating- point unit. 32099F–11/2010 AT32UC3L016/32/64 Table 4-4 on page 31. Some of 30 ...

Page 31

... MPU DTLB Miss (Write) MPU DTLB Protection (Read) MPU DTLB Protection (Write) MPU DTLB Modified UNUSED AT32UC3L016/32/64 Stored Return Address Undefined First non-completed instruction PC of offending instruction PC of offending instruction First non-completed instruction First non-completed instruction First non-completed instruction First non-completed instruction ...

Page 32

... Memories 5.1 Embedded Memories • Internal High-Speed Flash – 64Kbytes (AT32UC3L064) – 32Kbytes (AT32UC3L032) – 16Kbytes (AT32UC3L016) • Internal High-Speed SRAM, Single-cycle access at full speed – 16Kbytes (AT32UC3L064, AT32UC3L032) – 8Kbytes (AT32UC3L016) 5.2 Physical Memory Map The system bus is implemented as a bus matrix. All system bus addresses are fixed, and they are never remapped in any way, not even in boot ...

Page 33

... FREQM Frequency Meter - FREQM GPIO General Purpose Input/Output Controller - GPIO Universal Synchronous/Asynchronous USART0 Receiver/Transmitter - USART0 Universal Synchronous/Asynchronous USART1 Receiver/Transmitter - USART1 Universal Synchronous/Asynchronous USART2 Receiver/Transmitter - USART2 Universal Synchronous/Asynchronous USART3 Receiver/Transmitter - USART3 SPI Serial Peripheral Interface - SPI TWIM0 Two-wire Master Interface - TWIM0 AT32UC3L016/32/64 33 ...

Page 34

... Two-wire Slave Interface - TWIS0 TWIS1 Two-wire Slave Interface - TWIS1 PWMA Pulse Width Modulation Controller - PWMA TC0 Timer/Counter - TC0 TC1 Timer/Counter - TC1 ADCIFB ADC Interface - ADCIFB ACIFB Analog Comparator Interface - ACIFB CAT Capacitive Touch Module - CAT GLOC Glue Logic Controller - GLOC AW aWire - AW AT32UC3L016/32/64 34 ...

Page 35

... Local Bus Mapped GPIO Registers Register Output Driver Enable Register (ODER) Output Value Register (OVR) Pin Value Register (PVR) Output Driver Enable Register (ODER) Output Value Register (OVR) Pin Value Register (PVR) AT32UC3L016/32/64 Local Bus Mode Address Access WRITE 0x40000040 Write-only ...

Page 36

... I/O lines 32099F–11/2010 Section 32. on page 782 for power consumption on the various supply pins. Section 6.1.3 for regulator connection figures. Supply Decoupling C C IN3 IN2 C OUT2 AT32UC3L016/32/64 Section 32.9.1 on page VDDIN C IN1 Regulator VDDCORE C OUT1 1.8V 36 ...

Page 37

... VDDCORE VDDANA 32099F–11/2010 Figure 6-2 shows the power schematics to be used for 3.3V 3.3V Single Supply Mode + - VDDIN I/O Pins Linear ADC GNDANA AT32UC3L016/32/64 VDDIO GND I/O Pins OSC32K RC32K AST Wake POR33 SM33 CPU, Peripherals, Memories, SCIF, BOD, ...

Page 38

... VDDIO = VDDCORE). Figure 6-3. 1.62-1.98V 32099F–11/2010 1.8V Single Supply Mode VDDIN I/O Pins Linear VDDCORE VDDANA GNDANA AT32UC3L016/32/64 Figure 6-3. All I/O lines will be powered by the VDDIO I/O Pins OSC32K RC32K AST Wake POR33 SM33 CPU, Peripherals, ...

Page 39

... Supply Mode with 1.8V Regulated I/O Lines 1.98-3.6V + VDDIN - VDDCORE VDDANA GNDANA Section 3.2 on page 9 for description of power supply for each I/O line. AT32UC3L016/32/64 Figure 6-4. This configuration is required in order to VDDIO I/O Pins I/O Pins Linear OSC32K RC32K AST Wake ...

Page 40

... The code read from the internal Flash is free to configure the system to use, for example, the DFLL, to divide the frequency of the clock routed to some of the peripherals, and to gate the clocks to unused peripherals. 32099F–11/2010 Table 32-3 on page 783. for the minimum rise rate value. for the frequency for this oscillator. AT32UC3L016/32/64 40 ...

Page 41

... The PDCA communicates with the peripheral modules over a set of handshake interfaces. The peripheral signals the PDCA when it is ready to receive or transmit data. The PDCA acknowl- edges the request when the transmission has started. When a transmit buffer is empty or a receive buffer is full, an optional interrupt request can be generated. 32099F–11/2010 AT32UC3L016/32/64 41 ...

Page 42

... The PDCA interrupt request lines are connected to the interrupt controller. Using the PDCA interrupts requires the interrupt controller to be programmed first. 32099F–11/2010 PDCA Block Diagram Memory HSB to PB HSB Bridge HSB HSB Peripheral DMA Controller (PDCA) IRQ Interrupt AT32UC3L016/32/64 Peripheral 0 Peripheral 1 Peripheral 2 Peripheral (n-1) Handshake Interfaces 42 ...

Page 43

... MAR and TCR will be reloaded with the values in MARR and TCRR. The reload logic is always enabled and will trigger if the TCR reaches zero while TCRR holds a non-zero value. After reload, the MARR and TCRR registers are cleared. 32099F–11/2010 AT32UC3L016/32/64 Section 7.5.6. Section Section 7 ...

Page 44

... The current status of an interrupt source can be read through the Interrupt Status Register (ISR). The PDCA has three interrupt sources: • Reload Counter Zero - The TCRR register is zero. • Transfer Finished - Both the TCR and TCRR registers are zero. • Transfer Error - An error has occurred in accessing memory. 32099F–11/2010 AT32UC3L016/32/64 44 ...

Page 45

... PWSTALLn channel, all registers in the channel are reset. This behavior is altered if the Channel Overflow Freeze bit is one in the Performance Control register (PCONTROL.CHnOVF). If this bit is one, the channel registers are frozen when either DATA or STALL reaches its maxi- mum value. This simplifies one-shot readout of the counter values. 32099F–11/2010 AT32UC3L016/32/64 45 ...

Page 46

... PWLATn) are saturating when their maximum count value is reached. The PRLATn and PWLATn registers are reset only by writing a one to the CHnRES in PCONTROL. A counter must manually be enabled by writing a one to the Channel Enable bit in the Perfor- mance Control Register (PCONTROL.CHnEN). 32099F–11/2010 AT32UC3L016/32/64 46 ...

Page 47

... Register Register Name Control Register Mode Register Status Register 1. The reset values are device specific. Please refer to the Module Configuration section at the end of this chapter. AT32UC3L016/32/64 Contents ... Version register 7-1. Each channel has a set of configuration regis- Access MAR Read/Write ...

Page 48

... The number of performance monitors is device specific. If the device has only one perfor- mance monitor, the Channel1 registers are not available. Please refer to the Module Configuration section at the end of this chapter for the number of performance monitors on this device. Register Register Name AT32UC3L016/32/64 Access PCONTROL Read/Write PRDATA0 Read-only ...

Page 49

... Reset Value: 0x00000000 • MADDR: Memory Address Address of memory buffer. MADDR should be programmed to point to the start of the memory buffer when configuring the PDCA. During transfer, MADDR will point to the next memory location to be read/written. 32099F–11/2010 MADDR[31:24 MADDR[23:16 MADDR[15: MADDR[7:0] AT32UC3L016/32/ ...

Page 50

... Receive/Transfer Holding Register for the peripheral. See the Module Configuration section of PDCA for details. The width of the PID field is device specific and dependent on the number of peripheral modules in the device. 32099F–11/2010 PID AT32UC3L016/32/ ...

Page 51

... Reset Value: 0x00000000 • TCV: Transfer Counter Value Number of data items to be transferred by the PDCA. TCV must be programmed with the total number of transfers to be made. During transfer, TCV contains the number of remaining transfers to be done. 32099F–11/2010 TCV[15: TCV[7:0] AT32UC3L016/32/ ...

Page 52

... Reset Value: 0x00000000 • MARV: Memory Address Reload Value Reload Value for the MAR register. This value will be loaded into MAR when TCR reaches zero if the TCRR register has a non- zero value. 32099F–11/2010 MARV[31:24 MARV[23:16 MARV[15: MARV[7:0] AT32UC3L016/32/ ...

Page 53

... TCRV: Transfer Counter Reload Value Reload value for the TCR register. When TCR reaches zero, it will be reloaded with TCRV if TCRV has a positive value. If TCRV is zero, no more transfers will be performed for the channel. When TCR is reloaded, the TCRR register is cleared. 32099F–11/2010 TCRV[15: TCRV[7:0] AT32UC3L016/32/ ...

Page 54

... Writing a zero to this bit has no effect. Writing a one to this bit will disable transfer for the DMA channel. • TEN: Transfer Enable Writing a zero to this bit has no effect. Writing a one to this bit will enable transfer for the DMA channel. 32099F–11/2010 AT32UC3L016/32/ ECLR TDIS TEN 54 ...

Page 55

... Peripheral Select Register (PSR) requests a transfer. 1:Start transfer only when or after a peripheral event is received. • SIZE: Size of Transfer Table 7-5. Size of Transfer SIZE Size of Transfer 0 Byte 1 Halfword 2 Word 3 Reserved 32099F–11/2010 RING AT32UC3L016/32/ ETRIG SIZE 55 ...

Page 56

... Reset Value: 0x00000000 • TEN: Transfer Enabled This bit is cleared when the TDIS bit written to one. This bit is set when the TEN bit written to one. 0: Transfer is disabled for the DMA channel. 1: Transfer is enabled for the DMA channel. 32099F–11/2010 AT32UC3L016/32/ TEN 56 ...

Page 57

... Interrupt Enable Register Name: IER Access Type: Write-only Offset: 0x020 + n*0x040 Reset Value: 0x00000000 Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR. 32099F–11/2010 AT32UC3L016/32/ TERR TRC RCZ 57 ...

Page 58

... Interrupt Disable Register Name: IDR Access Type: Write-only Offset: 0x024 + n*0x040 Reset Value: 0x00000000 Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR. 32099F–11/2010 AT32UC3L016/32/ TERR TRC RCZ 58 ...

Page 59

... Reset Value: 0x00000000 The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. A bit in this register is cleared when the corresponding bit in IDR is written to one. A bit in this register is set when the corresponding bit in IER is written to one. 32099F–11/2010 AT32UC3L016/32/ TERR TRC RCZ 59 ...

Page 60

... This bit is cleared when the TCR and/or the TCRR holds a non-zero value. This bit is set when both the TCR and the TCRR are zero. • RCZ: Reload Counter Zero This bit is cleared when the TCRR holds a non-zero value. This bit is set when TCRR is zero. 32099F–11/2010 AT32UC3L016/32/ TERR TRC RCZ 60 ...

Page 61

... All performance channel registers are frozen just before DATA or STALL overflows. • CH1EN: Performance Channel 1 Enable 0: Performance channel 1 is disabled. 1: Performance channel 1 is enabled. • CH0EN: Performance Channel 0 Enable 0: Performance channel 0 is disabled. 1: Performance channel 0 is enabled. 32099F–11/2010 CH1OF CH0OF - AT32UC3L016/32/ MON1CH 18 17 MON0CH CH1RES CH1EN CH0RES 0 CH0EN 61 ...

Page 62

... Performance Channel 0 Read Data Cycles Name: PRDATA0 Access Type: Read-only Offset: 0x804 Reset Value: 0x00000000 • DATA: Data Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock 32099F–11/2010 DATA[31:24 DATA[23:16 DATA[15: DATA[7:0] AT32UC3L016/32/ ...

Page 63

... Performance Channel 0 Read Stall Cycles Name: PRSTALL0 Access Type: Read-only Offset: 0x808 Reset Value: 0x00000000 • STALL: Stall Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock 32099F–11/2010 STALL[31:24 STALL[23:16 STALL[15: STALL[7:0] AT32UC3L016/32/ ...

Page 64

... Access Type: Read/Write Offset: 0x80C Reset Value: 0x00000000 • LAT: Maximum Transfer Initiation Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock This counter is saturating. The register is reset only when PCONTROL.CH0RES is written to one. 32099F–11/2010 LAT[15: LAT[7:0] AT32UC3L016/32/ ...

Page 65

... Performance Channel 0 Write Data Cycles Name: PWDATA0 Access Type: Read-only Offset: 0x810 Reset Value: 0x00000000 • DATA: Data Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock 32099F–11/2010 DATA[31:24 DATA[23:16 DATA[15: DATA[7:0] AT32UC3L016/32/ ...

Page 66

... Performance Channel 0 Write Stall Cycles Name: PWSTALL0 Access Type: Read-only Offset: 0x814 Reset Value: 0x00000000 • STALL: Stall Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock 32099F–11/2010 STALL[31:24 STALL[23:16 STALL[15: STALL[7:0] AT32UC3L016/32/ ...

Page 67

... Access Type: Read/Write Offset: 0x818 Reset Value: 0x00000000 • LAT: Maximum Transfer Initiation Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock This counter is saturating. The register is reset only when PCONTROL.CH0RES is written to one. 32099F–11/2010 LAT[15: LAT[7:0] AT32UC3L016/32/ ...

Page 68

... Performance Channel 1 Read Data Cycles Name: PRDATA1 Access Type: Read-only Offset: 0x81C Reset Value: 0x00000000 • DATA: Data Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock 32099F–11/2010 DATA[31:24 DATA[23:16 DATA[15: DATA[7:0] AT32UC3L016/32/ ...

Page 69

... Performance Channel 1 Read Stall Cycles Name: PRSTALL1 Access Type: Read-only Offset: 0x820 Reset Value: 0x00000000 • STALL: Stall Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock 32099F–11/2010 STALL[31:24 STALL[23:16 STALL[15: STALL[7:0] AT32UC3L016/32/ ...

Page 70

... Access Type: Read/Write Offset: 0x824 Reset Value: 0x00000000 • LAT: Maximum Transfer Initiation Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock This counter is saturating. The register is reset only when PCONTROL.CH1RES is written to one. 32099F–11/2010 LAT[15: LAT[7:0] AT32UC3L016/32/ ...

Page 71

... Performance Channel 1 Write Data Cycles Name: PWDATA1 Access Type: Read-only Offset: 0x828 Reset Value: 0x00000000 • DATA: Data Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock 32099F–11/2010 DATA[31:24 DATA[23:16 DATA[15: DATA[7:0] AT32UC3L016/32/ ...

Page 72

... Performance Channel 1 Write Stall Cycles Name: PWSTALL1 Access Type: Read-only Offset: 0x82C Reset Value: 0x00000000 • STALL: Stall Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock 32099F–11/2010 STALL[31:24 STALL[23:16 STALL[15: STALL[7:0] AT32UC3L016/32/ ...

Page 73

... Access Type: Read/Write Offset: 0x830 Reset Value: 0x00000000 • LAT: Maximum Transfer Initiation Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock This counter is saturating. The register is reset only when PCONTROL.CH1RES is written to one. 32099F–11/2010 LAT[15: LAT[7:0] AT32UC3L016/32/ ...

Page 74

... PDCA Version Register Name: VERSION Access Type: Read-only Offset: 0x834 Reset Value • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated. 32099F–11/2010 VERSION[7:0] AT32UC3L016/32/ VARIANT VERSION[11: ...

Page 75

... Module Clock Name Clock Name Description CLK_PDCA_HSB Clock for the PDCA HSB interface CLK_PDCA_PB Clock for the PDCA PB interface Register Reset Values Reset Value 122 Peripheral Identity Values Direction Peripheral Instance RX USART0 RX USART1 RX USART2 RX USART3 AT32UC3L016/32/64 Peripheral Register RHR RHR RHR RHR 75 ...

Page 76

... Peripheral Instance RX SPI RX TWIM0 RX TWIM1 RX TWIS0 RX TWIS1 RX ADCIFB CAT TX USART0 TX USART1 TX USART2 TX USART3 TX SPI TX TWIM0 TX TWIM1 TX TWIS0 TX TWIS1 CAT AT32UC3L016/32/64 Peripheral Register RDR RHR RHR RHR RHR LCDR RHR ACOUNT THR THR THR THR TDR THR THR THR THR THR MBLEN 76 ...

Page 77

... FLASHCDW configuration and control registers. Failing may deadlock the bus. 8.3.3 Interrupts The FLASHCDW interrupt request lines are connected to the interrupt controller. Using the FLASHCDW interrupts requires the interrupt controller to be programmed first. 32099F–11/2010 AT32UC3L016/32/64 ™ technology 77 ...

Page 78

... Wait state support and a read granularity of 64 bits ensure efficiency in such systems. Performance for systems with high clock frequency is increased since the internal read word width of the flash memory is 64 bits. When a 32-bit word addressed, the word itself and 32099F–11/2010 AT32UC3L016/32/64 Figure 8-1 on page 80. 78 ...

Page 79

... The User page is permanently mapped to an offset of 0x00800000 from the start address of the flash memory. Table 8-1. Memory type Main array User 32099F–11/2010 User Page Addresses Start address, byte sized 0 0x00800000 AT32UC3L016/32/64 Figure 8-1. The memory space between Size pw words = 4pw bytes 64 words = 256 bytes 79 ...

Page 80

... Refer to the Electrical Characteristics chapter at the end of this datasheet for details on the max- imum clock frequencies in Normal and High Speed Read Mode. 32099F–11/2010 Memory Map for the Flash Memories Offset from base address 0x0080 0000 pw 0 Flash with User Page All addresses are byte addresses AT32UC3L016/32/64 Reserved User Page Flash base address 80 ...

Page 81

... A%32 in the page buffer. The PAGEN field in the Flash Command (FCMD) register will at the same time be updated with the value A/32. 32099F–11/2010 High Speed Mode Frequency AT32UC3L016/32/64 1 wait state 0 wait state Frequency limit for 0 wait state ...

Page 82

... Clear Page Buffer command. 32099F–11/2010 Mapping from Page Buffer to Flash Page Buffer 64-bit data AT32UC3L016/32/64 Flash Z31 Z30 Z29 Z28 Z27 Z26 Z25 Z24 Z23 Z22 Z21 Z20 Z19 Z18 Z17 Z16 Page Z Z15 Z14 Z13 Z12 Z11 Z10 ...

Page 83

... FCMD register. Writing FCMD with data that does not contain the correct key and/or with an invalid command has no effect on the flash memory; however, the PROGE bit is set in the Flash Status Register (FSR). This bit is automatically cleared by a read access to the FSR register. 32099F–11/2010 AT32UC3L016/32/64 Section 8.8.2 for a complete list of 83 ...

Page 84

... The entire memory is erased if the Erase All command (EA) is written to the Flash Command Register (FCMD). Erase All erases all bits in the flash array. The User page is not erased. All 32099F–11/2010 executed to unlock the corresponding region before programming can start. privileges. AT32UC3L016/32/64 Section 8.4.7 on page 81. 84 ...

Page 85

... The flash memory has a number of general-purpose fuse bits that the application programmer can use freely. The fuse bits can be written and erased using dedicated commands, and read 32099F–11/2010 Section 8.6. The general-purpose bit being in an erased (1) state means that the region 8.6. AT32UC3L016/32/64 85 ...

Page 86

... If programmed (i.e. “0”), the JTAG USER PROTECTION feature is enabled. If this fuse is programmed some HSB addresses will be accessible by JTAG access even if the flash UPROT security fuse is programmed. Refer to the JTAG documentation for more information on this functionality. This bit can only be changed when the security bit is cleared. AT32UC3L016/32/64 86 ...

Page 87

... Secure State Configuration Functionality Secure state disabled Secure enabled, secure state debug enabled Secure enabled, secure state debug disabled Secure state disabled while the flash is locked by the security bit. enabled. AT32UC3L016/32/64 SSE SSDE ...

Page 88

... Program General-Purpose Fuse Byte (PGPFB) of fuse byte 2 • Erase All General-Purpose Fuses (EAGPF) One error can be detected in the FSR register after issuing the command: • Programming Error: A bad keyword and/or an invalid command have been written in the FCMD register. 32099F–11/2010 AT32UC3L016/32/64 Section 8.5.3. Chip or aWire 88 ...

Page 89

... All bits in FGPRHI/LO are dependent on the programmed state of the fuses they map to. Any bits in these registers not mapped to a fuse read The reset values for these registers are device specific. Please refer to the Module Configuration section at the end of this chapter. 32099F–11/2010 Register Register Name AT32UC3L016/32/64 Access FCR Read/Write FCMD Read/Write FSR ...

Page 90

... LOCKE: Lock Error Interrupt Enable 0: Lock Error does not generate an interrupt request. 1: Lock Error generates an interrupt request. • FRDY: Flash Ready Interrupt Enable 0: Flash Ready does not generate an interrupt request. 1: Flash Ready generates an interrupt request. 32099F–11/2010 PROGE AT32UC3L016/32/ BRBUF SEQBUF - LOCKE - FRDY 90 ...

Page 91

... Erase General-Purpose Fuse Bit Set Security Bit 32099F–11/2010 KEY PAGEN [15: PAGEN [7: PAGEN description Not used The number of the page to write Not used Page number whose region should be locked Page number whose region should be unlocked Not used GPFUSE # GPFUSE # Not used AT32UC3L016/32/ CMD ...

Page 92

... High Speed Mode Disable RESERVED 32099F–11/2010 PAGEN description WriteData[7:0], ByteAddress[2:0] Not used Page number Not used Not used Not used Not used Not used Value Mnemonic 0 NOP CPB WGPB 8 EGPB 9 SSB 10 PGPFB 11 EAGPF 12 QPR 13 WUP 14 EUP 15 QPRUP 16 HSEN 17 HSDIS 16-31 AT32UC3L016/32/64 92 ...

Page 93

... FRDY: Flash Ready Status 0: The Flash Controller is busy and the application must wait before running a new command. 1: The Flash Controller is ready to run a new command. 32099F–11/2010 LOCK13 LOCK12 LOCK11 LOCK5 LOCK4 LOCK3 QPRR SECURITY PROGE AT32UC3L016/32/ LOCK10 LOCK9 LOCK8 LOCK2 LOCK1 LOCK0 LOCKE - FRDY 93 ...

Page 94

... Reset Value • PSZ: Page Size The size of each flash page. Table 8-8. Flash Page Size PSZ Page Size 0 32 Byte 1 64 Byte 2 128 Byte 3 256 Byte 4 512 Byte 5 1024 Byte 6 2048 Byte 7 4096 Byte 32099F–11/2010 AT32UC3L016/32/ PSZ FSZ 94 ...

Page 95

... The size of the flash. Not all device families will provide all flash sizes indicated in the table. Table 8-9. Flash Size FSZ Flash Size FSZ 0 4 Kbyte Kbyte Kbyte Kbyte Kbyte Kbyte Kbyte 14 7 128 Kbyte 15 32099F–11/2010 Flash Size 192 Kbyte 256 Kbyte 384 Kbyte 512 Kbyte 768 Kbyte 1024 Kbyte 2048 Kbyte Reserved AT32UC3L016/32/64 95 ...

Page 96

... Flash Version Register Name: FVR Access Type: Read-only Offset: 0x10 Reset Value: 0x00000000 • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated. 32099F–11/2010 VERSION[7:0] AT32UC3L016/32/ VARIANT VERSION[11: ...

Page 97

... GPFxx: General Purpose Fuse xx 0: The fuse has a written/programmed state. 1: The fuse has an erased state. 32099F–11/2010 GPF61 GPF60 GPF59 GPF53 GPF52 GPF51 GPF45 GPF44 GPF43 GPF37 GPF36 GPF35 AT32UC3L016/32/ GPF58 GPF57 GPF56 GPF50 GPF49 GPF48 GPF42 GPF41 GPF40 GPF34 GPF33 GPF32 97 ...

Page 98

... GPFxx: General Purpose Fuse xx 0: The fuse has a written/programmed state. 1: The fuse has an erased state. 32099F–11/2010 GPF29 GPF28 GPF27 GPF21 GPF20 GPF19 GPF13 GPF12 GPF11 GPF05 GPF04 GPF03 AT32UC3L016/32/ GPF26 GPF25 GPF24 GPF18 GPF17 GPF16 GPF10 GPF09 GPF08 GPF02 GPF01 GPF00 98 ...

Page 99

... These are Flash Controller fuses and are described in the FLASHCDW section. 32099F–11/2010 29 28 BODHYST 21 20 SECURE 13 12 LOCK[15: LOCK[7:0] Description BOD disabled BOD enabled, BOD reset enabled BOD enabled, BOD reset disabled BOD disabled 782. AT32UC3L016/32/ BODLEVEL[5: BOOTPROT ”Electrical Characteris EPFL 8 ...

Page 100

... Please refer to the WDT chapter for detail about timeout settings when the WDT is automatically enabled. 8.9.2.1 Default user page first word value The devices are shipped with the User page erased (all bits 1): • WDTAUTO set to 1, WDT disabled. 32099F–11/2010 AT32UC3L016/32/ WDTAUTO 100 ...

Page 101

... Please refer to the Power Manager chapter for details. Table 8-10. Feature Flash size Number of pages Page size 32099F–11/2010 SSADRR[15: SSADRR[7: SSADRF[15: SSADRF[7:0] Module Configuration AT32UC3L064 AT32UC3L032 64Kbytes 32Kbytes 256 128 256 bytes 256 bytes AT32UC3L016/32/ AT32UC3L016 16Kbytes 64 256 bytes 101 ...

Page 102

... Table 8-11. Module Name FLASHCDW Table 8-12. Register FVR FPR 32099F–11/2010 Module Clock Name Clock Name Description CLK_FLASHCDW_HSB Clock for the FLASHCDW HSB interface CLK_FLASHCDW_PB Clock for the FLASHCDW PB interface Register Reset Values Reset Value 0x00000102 0x00000305 AT32UC3L016/32/64 102 ...

Page 103

... Only one channel can be open at a time, opening a channel while another one is open locks the first one • Access to a locked channel is denied, a bus error and optionally an interrupt is returned • channel is relocked due to an unlock timeout, an interrupt can optionally be generated AT32UC3L016/32/64 103 ...

Page 104

... SAU. The CPU wants to Figure SAU Block Diagram CPU MPU Bus master Bus slave Bus master SAU Channel SAU Configuration SAU request AT32UC3L016/32/64 9-1. Flash RAM Bus slave Bus slave High Speed Bus Bus slave Bus bridge USART PWM 104 ...

Page 105

... PB register. When all channels have been configured, return to normal mode by writ- ing a one to the Setup Mode Disable (SDIS) in CR. The channels can now be enabled by writing ones to the corresponding bits in the Channel Enable Registers (CERH/L). The SAU is only able to remap addresses above 0xFFFC0000. 32099F–11/2010 AT32UC3L016/32/64 105 ...

Page 106

... HSB master interface to remap the access to the target address pointed to by the corresponding RTR. (SR.IDLE) to indicate the operation is completed. Then check SR for possible error conditions. The SAU can be configured to generate interrupt requests or a Bus Error Exception if the access failed. AT32UC3L016/32/64 106 ...

Page 107

... Example Memory Map for a System with SAU Receive Holding SAU Transmit Holding CONFIG UART SAU CHANNEL AT32UC3L016/32/64 Address X Baudrate Control UR RTR62 Channel 1 RTR1 RTR0 Address Z Section 9.5.7 107 ...

Page 108

... Disabling the SAU To disable the SAU, the user must first ensure that no SAU bus operations are pending. This can be done by checking that the STATUS.IDLE bit is set. The SAU may then be disabled by writing a one to the Disable (DIS) bit in CR. 32099F–11/2010 AT32UC3L016/32/64 Section 108 ...

Page 109

... Remap Target Register n 0xFC 32099F–11/2010 Register Control Register Configuration Register Status Register Interrupt Mask Register Interrupt Clear Register Parameter Register Version Register Register ... Unlock Register AT32UC3L016/32/64 Register Name Access CR Write-only 0x00000000 CONFIG Write-only 0x00000000 CERH Read/Write 0x00000000 CERL Read/Write 0x00000000 ...

Page 110

... DIS: SAU Disable Writing a zero to this bit has no effect. Writing a one to this bit disables the SAU. • EN: SAU Enable Writing a zero to this bit has no effect. Writing a one to this bit enables the SAU. 32099F–11/2010 BERREN SDIS AT32UC3L016/32/ SEN DIS EN 110 ...

Page 111

... Once a channel has been unlocked, it remains unlocked for this amount of CLK_SAU_HSB clock cycles or until one access to a channel has been made. • UKEY: Unlock Key The value in this register must be written into UR.KEY to unlock a channel. 32099F–11/2010 UCYC UKEY AT32UC3L016/32/ OPEN 111 ...

Page 112

... Channel Enable Register High Name: CERH Access Type: Read/Write Offset: 0x08 Reset Value: 0x00000000 • CERH[n]: Channel Enable Register High 0: Channel (n+32) is not enabled. 1: Channel (n+32) is enabled. 32099F–11/2010 CERH[30:24 CERH[23:16 CERH[15: CERH[7:0] AT32UC3L016/32/ 112 ...

Page 113

... Channel Enable Register Low Name: CERL Access Type: Read/Write Offset: 0x0C Reset Value: 0x00000000 • CERL[n]: Channel Enable Register Low 0: Channel n is not enabled. 1: Channel n is enabled. 32099F–11/2010 CERL[31:24 CERL[23:16 CERL[15: CERL[7:0] AT32UC3L016/32/ 113 ...

Page 114

... This bit is set if the Unlock Register was attempted written with an invalid key. • URREAD: Unlock Register Read This bit is cleared when the corresponding bit in ICR is written to one. This bit is set if the Unlock Register was read. 32099F–11/2010 URES URKEY URREAD AT32UC3L016/32/ IDLE SEN CAU CAS EXP 114 ...

Page 115

... This bit is set if channel access successful, i.e. one access was made after the channel was unlocked. • EXP: Channel Unlock Expired This bit is cleared when the corresponding bit in ICR is written to one. This bit is set if channel unlock has expired, i.e. no access being made after the channel was unlocked. 32099F–11/2010 AT32UC3L016/32/64 115 ...

Page 116

... IER Access Type: Write-only Offset: 0x14 Reset Value: 0x00000000 RTRADR MBERROR Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR. 32099F–11/2010 URES URKEY URREAD AT32UC3L016/32/ CAU CAS EXP 116 ...

Page 117

... IDR Access Type: Write-only Offset: 0x18 Reset Value: 0x00000000 RTRADR MBERROR Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR. 32099F–11/2010 URES URKEY URREAD AT32UC3L016/32/ CAU CAS EXP 117 ...

Page 118

... MBERROR 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. A bit in this register is cleared when the corresponding bit in IDR is written to one. A bit in this register is set when the corresponding bit in IER is written to one. 32099F–11/2010 URES URKEY URREAD AT32UC3L016/32/ CAU CAS EXP 118 ...

Page 119

... Reset Value: 0x00000000 RTRADR MBERROR Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in SR and any corresponding interrupt request. 32099F–11/2010 URES URKEY URREAD AT32UC3L016/32/ CAU CAS EXP 119 ...

Page 120

... Parameter Register Name: PARAMETER Access Type: Read-only Offset: 0x24 Reset Value • CHANNELS: Number of channels implemented 32099F–11/2010 CHANNELS AT32UC3L016/32/ 120 ...

Page 121

... Version Register Name: VERSION Access Type: Write-only Offset: 0x28 Reset Value • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated. 32099F–11/2010 VERSION[7:0] AT32UC3L016/32/ VARIANT VERSION[11: 121 ...

Page 122

... RTR: Remap Target Address for Channel n RTR[31:16] must have one of the following values, any other value will result in UNDEFINED behavior: 0xFFFC 0xFFFD 0xFFFE 0xFFFF RTR[1:0] must be written to 0, any other value will result in UNDEFINED behavior. 32099F–11/2010 RTR[31:24 RTR[23:16 RTR[15: RTR[7:0] AT32UC3L016/32/ 122 ...

Page 123

... Reset Value: 0x00000000 • KEY: Unlock Key The correct key must be written in order to unlock a channel. The key value written must correspond to the key value defined in CONFIG.UKEY. • CHANNEL: Channel Number Number of the channel to unlock. 32099F–11/2010 KEY AT32UC3L016/32/ CHANNEL 123 ...

Page 124

... Module name SAU SAU Table 9-5. Register VERSION PARAMETER 32099F–11/2010 Module configuration SAU 16 Module clock name Clock name Description CLK_SAU_HSB Clock for the SAU HSB interface CLK_SAU_PB Clock for the SAU PB interface Register Reset Values Reset Value 0x00000110 0x00000010 AT32UC3L016/32/64 124 ...

Page 125

... This bus granting mechanism sets a different default master for every slave. At the end of the current access other request is pending, the slave remains connected to its associated default master. A slave can be associated with three kinds of default masters: no default master, last access master, and fixed default master. 32099F–11/2010 AT32UC3L016/32/64 125 ...

Page 126

... This is described below. 4. Slot Cycle Limit: When the slot cycle counter has reached the limit value indicating that the current master access is too long and must be broken. This is described below. 32099F–11/2010 . AT32UC3L016/32/64 “Arbitration 126 ...

Page 127

... Round-Robin Arbitration with Last Default Master This is a biased round-robin algorithm used by Bus Matrix arbiters. It allows the Bus Matrix to remove the one latency cycle for the last master that accessed the slave. At the end of the cur- 32099F–11/2010 AT32UC3L016/32/64 127 ...

Page 128

... For each slave, the priority of each master may be defined through the Priority Registers for Slaves (PRAS and PRBS). 10.4.3 Slave and Master assignation The index number assigned to Bus Matrix slaves and masters are described in the Module Con- figuration section at the end of this chapter. 32099F–11/2010 AT32UC3L016/32/64 128 ...

Page 129

... Slave Configuration Register 13 0x0078 Slave Configuration Register 14 0x007C Slave Configuration Register 15 0x0080 Priority Register A for Slave 0 0x0084 Priority Register B for Slave 0 0x0088 Priority Register A for Slave 1 32099F–11/2010 AT32UC3L016/32/64 Name Access MCFG0 Read/Write MCFG1 Read/Write MCFG2 Read/Write MCFG3 Read/Write MCFG4 Read/Write ...

Page 130

... Special Function Register 0 0x0114 Special Function Register 1 0x0118 Special Function Register 2 0x011C Special Function Register 3 0x0120 Special Function Register 4 0x0124 Special Function Register 5 0x0128 Special Function Register 6 32099F–11/2010 AT32UC3L016/32/64 Name Access PRBS1 Read/Write PRAS2 Read/Write PRBS2 Read/Write PRAS3 Read/Write PRBS3 Read/Write PRAS4 ...

Page 131

... Special Function Register 9 0x0138 Special Function Register 10 0x013C Special Function Register 11 0x0140 Special Function Register 12 0x0144 Special Function Register 13 0x0148 Special Function Register 14 0x014C Special Function Register 15 32099F–11/2010 AT32UC3L016/32/64 Name Access SFR7 Read/Write SFR8 Read/Write SFR9 Read/Write SFR10 Read/Write SFR11 Read/Write SFR12 ...

Page 132

... The undefined length burst is split into a four-beat burst, allowing re-arbitration at each four-beat burst end. The undefined length burst is split into an eight-beat burst, allowing re-arbitration at each eight-beat burst end. The undefined length burst is split into a sixteen-beat burst, allowing re-arbitration at each sixteen-beat burst end. AT32UC3L016/32/ – – ...

Page 133

... This limit must not be very small. Unreasonably small values break every burst and the Bus Matrix arbitrates without performing any data transfer. 16 cycles is a reasonable value for SLOT_CYCLE. 32099F–11/2010 – – – FIXED_DEFMSTR – – – SLOT_CYCLE AT32UC3L016/32/ – – ARBT DEFMSTR_TYPE – – – 133 ...

Page 134

... PRAS0...PRAS15 Access Type: Read/Write Offset: - Reset Value: 0x00000000 • MxPR: Master x Priority Fixed priority of Master x for accessing the selected slave. The higher the number, the higher the priority. 32099F–11/2010 M7PR - M5PR - M3PR - M1PR - AT32UC3L016/32/ M6PR M4PR M2PR M0PR 134 ...

Page 135

... PRBS0...PRBS15 Access Type: Read/Write Offset: - Reset Value: 0x00000000 • MxPR: Master x Priority Fixed priority of Master x for accessing the selected slave. The higher the number, the higher the priority. 32099F–11/2010 M15PR - M13PR - M11PR - M9PR - AT32UC3L016/32/ M14PR M12PR M10PR M8PR 135 ...

Page 136

... Name: SFR0...SFR15 Access Type: Read/Write Offset: 0x110 - 0x14C Reset Value • SFR: Special Function Register Fields Those registers are not a HMATRIX specific register. The field of those will be defined where they are used. 32099F–11/2010 SFR SFR SFR SFR AT32UC3L016/32/ 136 ...

Page 137

... Slave 2 Slave 3 Slave 4 32099F–11/2010 HMATRIX Clocks Description Clock for the HMATRIX bus interface High Speed Bus Masters CPU Data CPU Instruction CPU SAB SAU PDCA High Speed Bus Slaves Internal Flash HSB-PB Bridge A HSB-PB Bridge B Internal SRAM SAU AT32UC3L016/32/64 137 ...

Page 138

... Figure 10-1. HMatrix Master / Slave Connections 32099F–11/2010 HMATRIX SLAVES 0 1 CPU Data 0 CPU 1 Instruction CPU SAB 2 SAU 3 PDCA 4 AT32UC3L016/32/ 138 ...

Page 139

... The interrupt requests from the peripherals (IREQn) and the NMI are input on the left side of the figure. Signals to and from the CPU are on the right side of the figure. 32099F–11/2010 gives an overview of the INTC. The grey boxes represent registers that can be AT32UC3L016/32/64 139 ...

Page 140

... INT3 by associating each group with the Interrupt Level (INTLEVEL) field in the corresponding 32099F–11/2010 Interrupt Controller ValReqN GrpReqN OR . IPRn . . IRRn . . Request . Masking ValReq1 GrpReq1 OR IPR1 IRR1 ValReq0 GrpReq0 OR IPR0 IRR0 IPR Registers IRR Registers AT32UC3L016/32/64 Masks INT_level, offset . INTLEVEL . . INT_level, AUTOVECTOR offset INT_level, offset ICR Registers CPU SREG Masks I[3-0]M GM 140 ...

Page 141

... Clearing of the interrupt request is done by writing to registers in the corresponding peripheral module, which then clears the corresponding NMIREQ/IREQ signal. The recommended way of clearing an interrupt request is a store operation to the controlling peripheral register, followed by a dummy load operation from the same register. This causes a 32099F–11/2010 AT32UC3L016/32/64 141 ...

Page 142

... AT32UC3L016/32/64 142 ...

Page 143

... Interrupt Cause Register 3 0x204 Interrupt Cause Register 2 0x208 Interrupt Cause Register 1 0x20C Interrupt Cause Register 0 32099F–11/2010 Register Name ... IPR63 IRR0 IRR1 ... IRR63 ICR3 ICR2 ICR1 ICR0 AT32UC3L016/32/64 Access IPR0 Read/Write IPR1 Read/Write ... ... Read/Write Read-only Read-only ... ... Read-only Read-only Read-only Read-only Read-only Reset ...

Page 144

... Indicates the EVBA-relative offset of the interrupt handler of the corresponding group: 00: INT0: Lowest priority 01: INT1 10: INT2 11: INT3: Highest priority • AUTOVECTOR: Autovector Address Handler offset is used to give the address of the interrupt handler. The least significant bit should be written to zero to give halfword alignment. 32099F–11/2010 AUTOVECTOR[13: AUTOVECTOR[7:0] AT32UC3L016/32/ 144 ...

Page 145

... The IRRs are read by the software interrupt handler in order to determine which interrupt request is pending. The IRRs are sampled continuously, and are read-only. 32099F–11/2010 IRR[32*x+28] IRR[32*x+27 IRR[32*x+20] IRR[32*x+19 IRR[32*x+12] IRR[32*x+11 IRR[32*x+4] IRR[32*x+3] AT32UC3L016/32/ IRR[32*x+26] IRR[32*x+25] IRR[32*x+24 IRR[32*x+18] IRR[32*x+17] IRR[32*x+16 IRR[32*x+10] IRR[32*x+9] IRR[32*x+ IRR[32*x+2] IRR[32*x+1] IRR[32*x+ ...

Page 146

... Offset: 0x200 - 0x20C Reset Value: N • CAUSE: Interrupt Group Causing Interrupt of Priority n ICRn identifies the group with the highest priority that has a pending interrupt of level n. This value is only defined when at least one interrupt of level n is pending. 32099F–11/2010 AT32UC3L016/32/ CAUSE 146 ...

Page 147

... Peripheral DMA Controller 6 2 Peripheral DMA Controller 3 Peripheral DMA Controller 7 0 Power Manager 8 0 System Control Interface 9 0 Asynchronous Timer AT32UC3L016/32/64 Description Clock for the INTC bus interface SYSREG COMPARE OCD DCEMU_DIRTY OCD DCCPU_READ FLASHCDW PDCA 0 PDCA 1 PDCA 2 PDCA 3 PDCA 4 PDCA 5 PDCA 6 PDCA 7 ...

Page 148

... Pulse Width Modulation Controller 0 Timer/Counter 25 1 Timer/Counter 2 Timer/Counter 0 Timer/Counter 26 1 Timer/Counter 2 Timer/Counter 27 0 ADC Interface AT32UC3L016/32/64 AST PER AST OVF AST READY AST CLKREADY EIC 1 EIC 2 EIC 3 EIC 4 EIC 5 FREQM GPIO 0 GPIO 1 GPIO 2 GPIO 3 GPIO 4 GPIO 5 USART0 USART1 USART2 USART3 ...

Page 149

... Table 11-3. 32099F–11/2010 Interrupt Request Signal Map 28 0 Analog Comparator Interface 29 0 Capacitive Touch Module 30 0 aWire AT32UC3L016/32/64 ACIFB CAT AW 149 ...

Page 150

... Only a small amount of logic, including 32KHz crystal oscillator and AST is left powered. The Power Manager also contains a Reset Controller, which collects all possible reset sources, generates hard and soft resets, and allows the reset source to be identified by software. 32099F–11/2010 AT32UC3L016/32/64 150 ...

Page 151

... The Shutdown mode is only available for the “3.3V supply mode, with 1.8V regulated I/O lines“ power configuration. 32099F–11/2010 Synchronous Clock Generator Sleep Controller Interrupts Reset Controller Type Input AT32UC3L016/32/64 Synchronous clocks CPU, HSB, PBx Sleep Instruction Resets Active Level Low ...

Page 152

... The synchronous clock source can be changed on-the CPU PBx, Section 12.6.3. Additionally, the clocks for each module in each synchro- Sleep Sleep Instruction Controller 0 Main Clock 1 CPUDIV CPUSEL (CPUSEL+ main AT32UC3L016/32/64 Mask CPU Clocks HSB Clocks PBx Clocks CPUMASK 152 ...

Page 153

... The modules will be halted regardless of the bit settings of the mask registers. Clock sources can also be switched off to save power. Some of these have a relatively long start-up time, and are only switched off when very low power consumption is required. 32099F–11/2010 AT32UC3L016/32/64 CPU Table 12-2 on page 154 as argument. ...

Page 154

... Run Run Stop Stop Stop Run Stop Stop Stop Run Stop Stop Stop Run Stop Stop Stop Run AT32UC3L016/32/64 Table 12-2 on page for more details. Voltage BOD & RCSYS Bandgap Regulator Run On Normal mode Run On Normal mode Run On Normal mode Run ...

Page 155

... VDDCORE and VDDIO power supplies. When the device enters Shutdown mode, the regulator is turned off and only the following logic is kept powered by VDDIN: – 2nd 32KHz crystal oscillator (available on PA13/PA20) 32099F–11/2010 AT32UC3L016/32/64 Section 12.6.4. 155 ...

Page 156

... CPU. writing a one to the EN bit of the SCIF.RC32KCR register. Because of internal synchronisation, this bit must be read as a one to ensure that the oscillator is stable before the sleep instruction is executed by the CPU AT32UC3L016/32/64 156 ...

Page 157

... The device is kept under reset until RESET_N is tied high again 32KHz Crystal oscillator must be set-up to use alternate pinout (XIN32_2 and XOUT32_2) See SCIF Chapter AST must be configured to use the clock from the 32KHz crystal oscillator AST must be configured to allow alarm,periodic or overflow wake-up AT32UC3L016/32/64 Table 12-4 on 157 ...

Page 158

... Supply voltage on VDDCORE below the brownout reset detector threshold voltage Supply voltage on VDDCORE below the brownout reset detector threshold voltage See Watchdog Timer documentation. See On-Chip Debug documentation AT32UC3L016/32/64 Table 12-5 on page 158 CPU, HSB, PBx OCD, AST, WDT, Clock Generator lists ...

Page 159

... AE: Access Error, set if a lock protected register is written without first being unlocked. • CKRDY: Clock Ready, set when new CKSEL settings are effective. • CFD: Clock Failure Detected, set if the system detects that the main clock is not running. 32099F–11/2010 AT32UC3L016/32/64 159 ...

Page 160

... CPUMASK HSB Mask HSBMASK PBA Mask PBAMASK PBB Mask PBBMASK Reserved PBADIVMASK Reserved CFDCTRL UNLOCK Reserved Reserved Reserved RCAUSE WCAUSE Reserved VERSION AT32UC3L016/32/64 Access Read/Write CPUSEL Read/Write HSBSEL Read-only PBASEL Read/Write PBBSEL Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Write-only IER ...

Page 161

... CPU. This division is selected by writing to the CPUSEL and CPUDIV bits in the CPUSEL register, before switching to RC120M as main clock source. Note that this register is protected by a lock. To write to this register the UNLOCK register has to be written first. Please ref- ere to the UNLOCK register description for details. 32099F–11/2010 DFLL (1) AT32UC3L016/32/ MCSEL 161 ...

Page 162

... Also note that writing this register clears POSCSR.CKRDY. The register must not be re-written until CKRDY goes high. Note that this register is protected by a lock. To write to this register the UNLOCK register has to be written first. Please ref- ere to the UNLOCK register description for details. 32099F–11/2010 (CPUSEL+1) . AT32UC3L016/32/ CPUSEL 162 ...

Page 163

... HSB Clock Select Name: HSBSEL Access Type: Read Offset: 0x008 Reset Value: 0x00000000 HSBDIV - This register is read-only and its content is always equal to CPUSEL 32099F–11/2010 AT32UC3L016/32/ HSBSEL 163 ...

Page 164

... Also note that writing this register clears SR.CKRDY. The register must not be re-written until SR.CKRDY goes high. Note that this register is protected by a lock. To write to this register the UNLOCK register has to be written first. Please ref- ere to the UNLOCK register description for details. 32099F–11/2010 (PBSEL+1) . AT32UC3L016/32/ PBSEL 164 ...

Page 165

... Maskable Module Clocks in AT32UC3L. Bit CPUMASK 0 OCD 32099F–11/2010 MASK[31:24 MASK[23:16 MASK[15: MASK[7:0] HSBMASK PDCA FLASHCDW SAU PBB bridge PBA bridge Peripheral Event System - - - - - - AT32UC3L016/32/ PBAMASK PBBMASK PDCA FLASHCDW INTC HMATRIX PM SAU SCIF - AST - WDT - EIC - FREQM - GPIO - USART0 - USART1 - USART2 - 165 ...

Page 166

... Note that this register is protected by a lock. To write to this register the UNLOCK register has to be written first. Please ref- ere to the UNLOCK register description for details. 32099F–11/2010 HSBMASK PBAMASK - USART3 - SPI - TWIM0 - TWIM1 - TWIS0 - TWIS1 - PWMA - TC0 - TC1 - ADCIFB - ACIFB - CAT - GLOC - AT32UC3L016/32/64 PBBMASK - - - - - - - - - - - - - - - 166 ...

Page 167

... MASK[6:0] (n+1) is stopped. If bit n is written to one, the clock divided by 2 Table 12-9 shows what clocks are affected by the different MASK bits. USART2 USART3 - - - - CLK_USART/ CLK_USART/ DIV DIV - - - - - - - - AT32UC3L016/32/ (n+1) is enabled TC0 TC1 TIMER_CLOCK2 TIMER_CLOCK2 - - TIMER_CLOCK3 TIMER_CLOCK3 - - TIMER_CLOCK4 TIMER_CLOCK4 - - TIMER_CLOCK5 TIMER_CLOCK5 ...

Page 168

... CFDEN: Clock Failure Detection Enable 0: Clock Failure Detector is disabled 1: Clock Failure Detector is enabled Note that this register is protected by a lock. To write to this register the UNLOCK register has to be written first. Please ref- ere to the UNLOCK register description for details. 32099F–11/2010 AT32UC3L016/32/ CFDEN 168 ...

Page 169

... ADDR field and 0xAA in the KEY field. Then, in the next PB access write to the register specified in the ADDR field. • KEY: Unlock Key Write this bit field to 0xAA to enable unlock. • ADDR: Unlock Address Write the address of the register to unlock to this field. 32099F–11/2010 KEY ADDR[7:0] AT32UC3L016/32/ ADDR[9: 169 ...

Page 170

... Interrupt Enable Register Name: IER Access Type: Write-only Offset: 0x0C0 Reset Value: 0x00000000 Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR. 32099F–11/2010 CKRDY - - AT32UC3L016/32/ 170 ...

Page 171

... Interrupt Disable Register Name: IDR Access Type: Write-only Offset: 0x0C4 Reset Value: 0x00000000 Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR. 32099F–11/2010 CKRDY - - AT32UC3L016/32/ 171 ...

Page 172

... Access Type: Read-only Offset: 0x0C8 Reset Value: 0x00000000 The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. This bit is cleared when the corresponding bit in IDR is written to one. This bit is set when the corresponding bit in IER is written to one. 32099F–11/2010 CKRDY - - AT32UC3L016/32/ 172 ...

Page 173

... Name: ISR Access Type: Read-only Offset: 0x0CC Reset Value: 0x00000000 The corresponding interrupt is cleared. 1: The corresponding interrupt is pending. This bit is cleared when the corresponding bit in ICR is written to one. This bit is set when the corresponding interrupt occurs. 32099F–11/2010 CKRDY - - AT32UC3L016/32/ 173 ...

Page 174

... Interrupt Clear Register Name: ICR Access Type: Write-only Offset: 0x0D0 Reset Value: 0x00000000 Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in ISR. 32099F–11/2010 CKRDY - - AT32UC3L016/32/ 174 ...

Page 175

... The CKSEL register has been written, and the new clock setting is not yet effective. 1: The synchronous clocks have frequencies as indicated in the CKSEL register. • CFD: Clock Failure Detected 0: Main clock is running corretly. 1: Failure on main clock detected. Main clock is now running on RC osc. 32099F–11/2010 CKRDY - - AT32UC3L016/32/ CFD 175 ...

Page 176

... External reset in test mode • FRC32 : Force RC32 out 0: RC32 signal is not forced as output 1: RC32 signal is forced as output • RSTPUN: Reset Pullup, active low 0: Pull-up for external reset on 1: Pull-up for external reset off 32099F–11/2010 PPC[31:24 PPC[23:16 PPC[15: PPC[7:0] AT32UC3L016/32/ 176 ...

Page 177

... TWIS1RCMASK : TWIS1 Request Clock Mask 0: TWIS1 Request Clock is disabled 1: TWIS1 Request Clock is enabled Note that this register is protected by a lock. To write to this register the UNLOCK register has to be written first. Please ref- ere to the UNLOCK register description for details. 32099F–11/2010 AT32UC3L016/32/64 177 ...

Page 178

... The CPU was reset due to the core supply voltage being lower than the power-on threshold level, or due to the input voltage being lower than the minimum required input voltage for the voltage regulator. 32099F–11/2010 AWIRE - WDT AT32UC3L016/32/ JTAG OCDRST EXT BOD POR 178 ...

Page 179

... A bit in this register is set on wake up caused by the peripheral referred to in Table 12-11. Wake Cause Bit Wake Cause 0 CAT 1 ACIFB 2 ADCIFB 3 TWI Slave 0 4 TWI Slave 1 5 WAKE_N 6 ADCIFB Pen Detect 15 EIC 17 AST 31:18 - 32099F–11/2010 WCAUSE[31:24 WCAUSE[23:16 WCAUSE[15: WCAUSE[7:0] AT32UC3L016/32/ Table 12-11 on page 179 179 ...

Page 180

... Each bit in this register corresponds to an asynchronous wake up, according to 0: The correcponding wake up is disabled. 1: The corresponding wake up is enabled Table 12-12. Asynchronous Wake Up Bit Asynchronous Wake Up 0 CAT 1 ACIFB 2 ADCIFB 3 TWIS0 4 TWIS1 5 WAKEN 6 ADCIFBPD 31:7 - 32099F–11/2010 AWEN[31:24 AWEN[23:16 AWEN[15: AWEN[7:0] AT32UC3L016/32/ Table 12-12 on page 180 180 ...

Page 181

... PBD: PBD Implemented 0: PBD not implemented. 1: PBD implemented. • PBC: PBC Implemented 0: PBC not implemented. 1: PBC implemented. • PBB: PBB Implemented 0: PBB not implemented. 1: PBB implemented. • PBA: PBA Implemented 0: PBA not implemented. 1: PBA implemented. 32099F–11/2010 PBD AT32UC3L016/32/ PBC PBB PBA 181 ...

Page 182

... Version Register Name: VERSION Access Type: Read-Only Offset: 0x3FC Reset Value • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated. 32099F–11/2010 VERSION[7:0] AT32UC3L016/32/ VARIANT VERSION[11: 182 ...

Page 183

... Clock control registers OSC control registers DFLL control registers OCD system and OCD registers 32099F–11/2010 Description Clock for the PM bus interface Reset Value 0x00000411 Power-On External Watchdog Reset Reset Reset AT32UC3L016/32/64 BOD SM33 CPU Error OCD Reset Reset Reset Reset ...

Page 184

... I/O Lines Description Pin Description RC32 output at start-up Crystal 0 input Crystal 32 input (primary location) Crystal 32 input (secondary location) Crystal 0 output Crystal 32 output (primary location) Crystal 32 output (secondary location) Generic clock output AT32UC3L016/32/64 Type Output Analog/Digital Analog/Digital Analog/Digital Analog Analog Analog Output ...

Page 185

... Power Manager chapter. After a hard reset, or when waking up from a sleep mode where the oscillators were disabled, the oscillator will need a certain amount of time to stabilize on the correct frequency. This start- up time can be set in the OSCCTRLn register. 32099F–11/2010 AT32UC3L016/32/64 185 ...

Page 186

... Digital Frequency Locked Loop (DFLL) Operation Rev: 2.0.1.0 The DFLL is controlled by the Digital Frequency Locked Loop Interface (DFLLIF). The DFLL is disabled by default, but can be enabled to provide a high-frequency source clock for synchro- nous and generic clocks. Features: • Internal oscillator with no external components 32099F–11/2010 AT32UC3L016/32/64 186 ...

Page 187

... When this bit is set, the DFLL can be configured, and CLK_DFLL is ready to be used. Any write to a DFLLIF configuration register while DFLLnRDY is cleared will be ignored. 32099F–11/2010 COARSE 8 FINE 9 CSIZE FSIZE FREQUENCY TUNER IMUL FMUL DFLLLOCKF DFLLLOCKLOSTF DFLLLOCKC DFLLOVERFLOW DFLLLOCKLOSTC DFLLUNDERFLOW AT32UC3L016/32/64 DAC VCO CLK_DFLLIF_REF 187 ...

Page 188

... DFLLnCONF.COARSE and thereby sets the output frequency to a value close to the correct frequency. The DFLLn Locked on 32099F–11/2010 ) is given by: DFLL f = DFLL is the frequency of CLK_DFLLIF_REF. COARSE and FINE in DFLLnCONF are read- REF AT32UC3L016/32/64 ⎛ FMUL ⎞ f IMUL + ---------------- - ⎝ ⎠ REF ...

Page 189

... However, the actual frequency will be alternating between two frequencies fixed fre- quency is required, the dithering should not be enabled. 32099F–11/2010 Measure f DFLLn DFLLnLOCKC 1 DFLLnLOCKF Calculate Calculate new new FINE COARSE value value AT32UC3L016/32/64 Compen- DITHER 1 DFLLnLOCKA 1 sate for drift 0 0 Calculate Compen- new sate for dithering drift dutycycle 189 ...

Page 190

... DFLLn Ratio Register (DFLLnRATIO). The relative error on CLK_DFLL compared to the target frequency can be calculated as follows: 32099F–11/2010 Target frequency Initial frequency DFLLnLOCKC DFLLnLOCKF DFLLnLOCKA RATIODIFF f error = ------------------------------------------------ - NUMREF 2 AT32UC3L016/32/64 without losing either of the DFLL ⋅ REF ⋅ f DFLL 190 ...

Page 191

... NUMREF is the number of reference clock cycles the DFLLIF is using for calculating the provide better Electromagnetic Compatibility (EMC) the DFLLIF DFLL . DFLL Pseudorandom CLK_DFLLIF_DITHER Binary Sequence AT32UC3L016/32/64 to ensure that the DFLLIF REF FINE 1 Spread Spectrum Generator 0 AMPLITUDE, PRBS STEPSIZE To DFLL ...

Page 192

... CPU. If the BOD.FCD is one then the BOD configuration will not be changed during a BOD reset. To prevent unexpected writes to BOD due to software bugs, write access to this register is protected by a locking mechanism. For details please refer to the UNLOCK register description. 32099F–11/2010 AT32UC3L016/32/64 . These can be tuned to DFLL is low, i.e. the ratio DFLL ...

Page 193

... Fuse setting chapter for more details about RCCR fuses and how to program the fuses. If the Flash Calibration Done (FCD) bit in the RCCR is zero at any reset except for POR and POR33, then the flash calibration will be redone and the RCCR.FCD bit will be set before pro- 32099F–11/2010 AT32UC3L016/32/64 VDDCORE POR18 POWER MANAGER(PM) ...

Page 194

... VREGCR.CALIB or altering the values for the VREGIFB flash fuses. If the Flash Calibration Done (FCD) bit in the VREGCR is zero at any reset except for POR and POR33, then the flash calibration will be redone and the VREGCR.FCD bit will be set before pro- 32099F–11/2010 AT32UC3L016/32/64 194 ...

Page 195

... The SM33 can operate in continuous mode or in sampling mode. In sampling mode, the SM33 i s periodically enabled for a short period of time, just enough to make a a measurement and then disabled for a longer time to reduce power consumption. The current state of the SM33 can be checked by reading the ON bit in SM33 (SM33.ON). 32099F–11/2010 AT32UC3L016/32/64 195 ...

Page 196

... Generic Clock section. The clock is enabled by writing a one to the Enable bit (EN) in the 120 MHz RC Oscillator Configuration Register (RC120MCR) and disabled by writing a zero to the RC120MCR.EN bit. The oscillator is automatically disabled in certain sleep modes to reduce power consumption, as described in the Power Manager chapter. 32099F–11/2010 AT32UC3L016/32/64 196 ...

Page 197

... SCIF Module Configuration section. The selected source can optionally be divided by any even integer up to 512. Each clock can be independently enabled and disabled, and is also automatically disabled along with peripheral clocks by the Sleep Controller in the Power Manager. 32099F–11/2010 AT32UC3L016/32/64 197 ...

Page 198

... Interrupts The SCIF has 14 interrupt sources: • Access Error: – A protected SCIF register was accessed without first being correctly unlocked. 32099F–11/2010 ivider GCLK is the frequency of the selected source clock, and f SRC AT32UC3L016/32/64 S leep C ontroller 0 M ask G eneric C lock SRC = ---------------------------- ( ) ...

Page 199

... Status Register (ISR) is cleared by writing a one to the corresponding bit in the Interrupt Clear Register (ICR). Because all the interrupt sources are ORed together, the interrupt request from the SCIF will remain active until all the bits in ISR are cleared. 32099F–11/2010 AT32UC3L016/32/64 199 ...

Page 200

... Oscillator 0 Version Register 0x03CC 32 KHz Oscillator Version Register 0x03D0 DFLL Version Register 0x03D4 BOD Version Register 0x03D8 Voltage Regulator Version Register 32099F–11/2010 Register Unlock Register Register VREGIFBVERSION AT32UC3L016/32/64 Register Name Access IER Write-only IDR Write-only IMR Read-only ISR Read-only ICR Write-only PCLKSR ...

Related keywords