PIC24F16KA102-I/SS Microchip Technology, PIC24F16KA102-I/SS Datasheet - Page 16

• Manufacturer Part Number: PIC24F16KA102-I/SS
• Description: IC PIC MCU FLASH 16K 28-SSOP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24F16KA102-I/SS

• Program Memory Type: FLASH
• Program Memory Size: 16KB (5.5K x 24)
• Package / Case: 28-SSOP
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 24
• Eeprom Size: 512 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24F
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 1.5 KB
• Interface Type: I2C/IrDA/SPI/UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM240001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 9-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA240017 - MODULE PLUG-IN PIC24F16KA102 PIM
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC24FXXKAXXX
3.8
The procedure for writing the Configuration registers is
the same as for writing code memory. The only differ-
ence is that, only one word is programmed in each
operation. When writing Configuration registers, one
word is programmed during each operation, only work-
ing register, W0, is used as a temporary holding
register for the data to be programmed.
Table 3-7
Configuration registers.
Table 3-7 provides the ICSP programming details for
programming the Configuration registers, including the
serial pattern with the ICSP command code, which
must be transmitted LSB first using the PGCx and
PGDx pins (see Figure 3-2). In Step 1 of Table 3-8, the
Reset vector is exited. In Step 2, the NVMCON register
is initialized for programming code memory. In Step 3,
the 24-bit starting destination address for programming
is loaded into the TBLPAG register and W7 register.
DS39919A-page 16
Note:
Note:
Writing Configuration Registers
provides
The TBLPAG register is hard-coded to
0xF8 (the upper byte address of all
locations of the Configuration registers).
The TBLPAG register must be loaded with
F8h.
the
default
values
Advance Information
of
the
TABLE 3-7:
FBS
FGS
FOSCSEL
FOSC
FWDT
FPOR
FICD
FDS
Note 1:
Configuration
(3)
Registers
(4)
(2,3)
(1)
2:
3:
4:
The I2C2SEL bit (FPOR<4>) is not
implemented on PIC24FXXKAX01 and
PIC24FXXKAX00 devices and should be
programmed as ‘1’.
The FICD<6> bit is a reserved bit and
should be programmed as ‘1’.
The Configuration registers, FBS and
FICD, are reserved locations on
PIC24F04KA2XX devices, and should be
programmed with the default value given
above.
The RTCSOSC bit (FDS<5>) is not
implemented on PIC24F04KA2XX
devices, and should be programmed
as ‘1’.
DEFAULT VALUES FOR
CONFIGURATION REGISTER
SERIAL INSTRUCTION
© 2008 Microchip Technology Inc.
Value
DFh
FBh
C3h
0Fh
FFh
FFh
03h
87h