PIC24F16KA102-I/SS Microchip Technology, PIC24F16KA102-I/SS Datasheet - Page 44

• Manufacturer Part Number: PIC24F16KA102-I/SS
• Description: IC PIC MCU FLASH 16K 28-SSOP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24F16KA102-I/SS

• Program Memory Type: FLASH
• Program Memory Size: 16KB (5.5K x 24)
• Package / Case: 28-SSOP
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 24
• Eeprom Size: 512 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24F
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 1.5 KB
• Interface Type: I2C/IrDA/SPI/UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM240001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 9-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA240017 - MODULE PLUG-IN PIC24F16KA102 PIM
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC24FXXKAXXX
6.0
The Device ID region of memory can be used to
determine the mask, variant and manufacturing
information about the device. The Device ID region is
2 x 16 bits and it can be read using the READC
command. This region of memory is read-only and can
also be read when code protection is enabled.
Table 6-1 provides the Device ID for each device;
Table 6-2 provides the Device ID registers; Table 6-3
describes the bit field of each register.
TABLE 6-1:
TABLE 6-2:
TABLE 6-3:
TABLE 6-4:
DS39919A-page 44
PIC24F08KA101
PIC24F16KA101
PIC24F08KA102
PIC24F16KA102
PIC24F04KA200
PIC24F04KA201
FF0000h
FF0002h
FAMID<7:0>
DEV<7:0>
REV<3:0>
PIC24F16KAXXX
PIC24F08KAXXX
PIC24F04KAXXX
Legend: Item
Address
Device ID
Device
Bit Field
DEVICE ID
SUM[a:b] =
CFGB
Byte sum of (FBS & 0x000F + FGS & 0x0003 + FOSCSEL & 0x0087 + FOSC & 0x00DF +
FWDT & 0x00DF + FPOR & 0x00FB + FICD & 0x00C3 + FDS & 0x00FF)
DEVREV
DEVID
Name
DEVICE IDs
PIC24FXXKAXXX DEVICE ID REGISTERS
DEVICE ID BITS DESCRIPTION
CHECKSUM COMPUTATION
=
Read Code Protection
Description
Byte sum of locations, a to b inclusive (all 3 bytes of code memory)
Configuration Block (masked),
DEVREV
Register
15
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
DEVID
DEVID
DEVID
0D0Ah
0D08h
0D01h
0D03h
0D02h
0D00h
14
13
Advance Information
FAMID<7:0>
Encodes the family ID of the device.
Encodes the individual ID of the device.
Encodes the revision number of the device.
12
Checksum Computation
CFGB + SUM (0:002BFE)
CFGB + SUM (0:0015FE)
CFGB + SUM (0:000AFE)
11
10
—
0
0
0
6.1
6.1.1
Checksums for the PIC24FXXKAXXX family are
16 bits. The checksum is calculated by summing the
following:
• Contents of the code memory locations
• Contents of the Configuration registers
Table 6-4 describes how to calculate the checksum for
each device.
All memory locations are summed, one byte at a time,
using only their native data size. More specifically,
Configuration registers are summed by adding the
lower two bytes of these locations (the upper byte is
ignored) while the code memory is summed by adding
all three bytes of the code memory.
9
Bit
8
Checksums
CHECKSUM COMPUTATION
Description
7
Checksum
Erased
0xC334
0xE434
0x74B4
0x0000
0x0000
0x0000
Value
6
© 2008 Microchip Technology Inc.
5
DEV<7:0>
4
Chip Checksum with
0xAAAAAA at 0x00
at Last Location
Location and
3
0xC136
0xE236
0x72B6
0x0000
0x0000
0x0000
REV<3:0>
2
1
0