IC PIC MCU FLASH 16K 28-SSOP

PIC24F16KA102-I/SS

Manufacturer Part NumberPIC24F16KA102-I/SS
DescriptionIC PIC MCU FLASH 16K 28-SSOP
ManufacturerMicrochip Technology
SeriesPIC® XLP™ 24F
PIC24F16KA102-I/SS datasheets
 


Specifications of PIC24F16KA102-I/SS

Program Memory TypeFLASHProgram Memory Size16KB (5.5K x 24)
Package / Case28-SSOPCore ProcessorPIC
Core Size16-BitSpeed32MHz
ConnectivityI²C, IrDA, SPI, UART/USARTPeripheralsBrown-out Detect/Reset, POR, PWM, WDT
Number Of I /o24Eeprom Size512 x 8
Ram Size1.5K x 8Voltage - Supply (vcc/vdd)1.8 V ~ 3.6 V
Data ConvertersA/D 9x10bOscillator TypeInternal
Operating Temperature-40°C ~ 85°CProcessor SeriesPIC24F
CorePICData Bus Width16 bit
Data Ram Size1.5 KBInterface TypeI2C/IrDA/SPI/UART
Maximum Clock Frequency32 MHzNumber Of Programmable I/os24
Number Of Timers3Operating Supply Voltage1.8 V to 3.6 V
Maximum Operating Temperature+ 85 CMounting StyleSMD/SMT
3rd Party Development Tools52713-733, 52714-737, 53276-922, EWDSPICDevelopment Tools By SupplierPG164130, DV164035, DV244005, DV164005, DM240001
Minimum Operating Temperature- 40 COn-chip Adc9-ch x 10-bit
Lead Free Status / RoHS StatusLead free / RoHS CompliantFor Use WithMA240017 - MODULE PLUG-IN PIC24F16KA102 PIM
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PIC24F16KA102 FAMILY
10.2.2
IDLE MODE
Idle mode has these features:
• The CPU will stop executing instructions.
• The WDT is automatically cleared.
• The system clock source remains active. By
default, all peripheral modules continue to operate
normally from the system clock source, but can
also be selectively disabled (see Section 10.4
“Selective Peripheral Module Control”).
• If the WDT or FSCM is enabled, the LPRC will
also remain active.
The device will wake from Idle mode on any of these
events:
• Any interrupt that is individually enabled
• Any device Reset
• A WDT time-out
On wake-up from Idle, the clock is re-applied to the
CPU and instruction execution begins immediately,
starting with the instruction following the PWRSAV
instruction or the first instruction in the ISR.
10.2.3
INTERRUPTS COINCIDENT WITH
POWER SAVE INSTRUCTIONS
Any interrupt that coincides with the execution of a
PWRSAV instruction will be held off until entry into Sleep
or Idle mode has completed. The device will then
wake-up from Sleep or Idle mode.
10.2.4
DEEP SLEEP MODE
In PIC24F16KA102 family devices, Deep Sleep mode
is intended to provide the lowest levels of power con-
sumption available without requiring the use of external
switches to completely remove all power from the
device. Entry into Deep Sleep mode is completely
under software control. Exit from Deep Sleep mode can
be triggered from any of the following events:
• POR event
• MCLR event
• RTCC alarm (If the RTCC is present)
• External Interrupt 0
• Deep Sleep Watchdog Timer (DSWDT) time-out
In Deep Sleep mode, it is possible to keep the device
Real-Time Clock and Calendar (RTCC) running without
the loss of clock cycles.
The device has a dedicated Deep Sleep Brown-out
Reset (DSBOR) and a Deep Sleep Watchdog Timer
Reset (DSWDT) for monitoring voltage and time-out
events. The DSBOR and DSWDT are independent of
the standard BOR and WDT used with other
power-managed modes (Sleep, Idle and Doze).
DS39927B-page 102
10.2.4.1
Entering Deep Sleep Mode
Deep Sleep mode is entered by setting the DSEN bit in
the DSCON register, and then executing a Sleep
command
(PWRSAV
#SLEEP_MODE),
instruction cycle, to minimize the chance that Deep
Sleep will be spuriously entered.
If the PWRSAV command is not given within one instruc-
tion cycle, the DSEN bit will be cleared by the hardware
and must be set again by the software before entering
Deep Sleep mode. The DSEN bit is also automatically
cleared when exiting the Deep Sleep mode.
To re-enter Deep Sleep after a Deep Sleep
Note:
wake-up, allow a delay of at least 3 T
after clearing the RELEASE bit.
The sequence to enter Deep Sleep mode is:
1.
If the application requires the Deep Sleep WDT,
enable it and configure its clock source (see
Section 10.2.4.5 “Deep Sleep WDT” for
details).
2.
If the application requires Deep Sleep BOR,
enable it by programming the DSBOREN
Configuration bit (FDS<6>).
3.
If the application requires wake-up from Deep
Sleep on RTCC alarm, enable and configure the
RTCC module (see Section 19.0 “Real-Time
Clock and Calendar (RTCC)” for more
information).
4.
If needed, save any critical application context
data by writing it to the DSGPR0 and DSGPR1
registers (optional).
5.
Enable Deep Sleep mode by setting the DSEN
bit (DSCON<15>).
6.
Enter Deep Sleep mode by issuing 3 NOP
commands, and then a PWRSAV #0 instruction.
Any time the DSEN bit is set, all bits in the DSWSRC
register will be automatically cleared.
10.2.4.2
Exiting Deep Sleep Mode
Deep Sleep mode exits on any one of the following events:
• POR event on V
supply. If there is no DSBOR
DD
circuit to re-arm the V
DD
external V
supply must be lowered to the
DD
natural arming voltage of the POR circuit.
• DSWDT time-out. When the DSWDT timer times
out, the device exits Deep Sleep.
• RTCC alarm (if RTCEN = 1).
• Assertion (‘0’) of the MCLR pin.
• Assertion of the INT0 pin (if the interrupt was
enabled before Deep Sleep mode was entered).
The polarity configuration is used to determine the
assertion level (‘0’ or ‘1’) of the pin that will cause
an exit from Deep Sleep mode. Exiting from Deep
Sleep mode requires a change on the INT0 pin
while in Deep Sleep mode.
Preliminary
© 2009 Microchip Technology Inc.
within
one
CY
supply POR circuit, the