IC PIC MCU FLASH 16K 28-SSOP

PIC24F16KA102-I/SS

Manufacturer Part NumberPIC24F16KA102-I/SS
DescriptionIC PIC MCU FLASH 16K 28-SSOP
ManufacturerMicrochip Technology
SeriesPIC® XLP™ 24F
PIC24F16KA102-I/SS datasheets
 


Specifications of PIC24F16KA102-I/SS

Program Memory TypeFLASHProgram Memory Size16KB (5.5K x 24)
Package / Case28-SSOPCore ProcessorPIC
Core Size16-BitSpeed32MHz
ConnectivityI²C, IrDA, SPI, UART/USARTPeripheralsBrown-out Detect/Reset, POR, PWM, WDT
Number Of I /o24Eeprom Size512 x 8
Ram Size1.5K x 8Voltage - Supply (vcc/vdd)1.8 V ~ 3.6 V
Data ConvertersA/D 9x10bOscillator TypeInternal
Operating Temperature-40°C ~ 85°CProcessor SeriesPIC24F
CorePICData Bus Width16 bit
Data Ram Size1.5 KBInterface TypeI2C/IrDA/SPI/UART
Maximum Clock Frequency32 MHzNumber Of Programmable I/os24
Number Of Timers3Operating Supply Voltage1.8 V to 3.6 V
Maximum Operating Temperature+ 85 CMounting StyleSMD/SMT
3rd Party Development Tools52713-733, 52714-737, 53276-922, EWDSPICDevelopment Tools By SupplierPG164130, DV164035, DV244005, DV164005, DM240001
Minimum Operating Temperature- 40 COn-chip Adc9-ch x 10-bit
Lead Free Status / RoHS StatusLead free / RoHS CompliantFor Use WithMA240017 - MODULE PLUG-IN PIC24F16KA102 PIM
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PIC24F16KA102 FAMILY
10.2.4.5
Deep Sleep WDT
To enable the DSWDT in Deep Sleep mode, program
the Configuration bit, DSWDTEN (FDS<7>). The
device Watchdog Timer (WDT) need not be enabled for
the DSWDT to function. Entry into Deep Sleep mode
automatically resets the DSWDT.
The DSWDT clock source is selected by the
DSWDTOSC
Configuration
bit
(FDS<4>).
postscaler
options
are
programmed
DSWDTPS<3:0> Configuration bits (FDS<3:0>). The
minimum time-out period that can be achieved is 2.1 ms
and the maximum is 25.7 days. For more details on the
FDS Configuration register and DSWDT configuration
options, refer to Section 26.0 “Special Features”.
10.2.4.6
Switching Clocks in Deep Sleep
Mode
Both the RTCC and the DSWDT may run from either
SOSC or the LPRC clock source. This allows both the
RTCC and DSWDT to run without requiring both the
LPRC and SOSC to be enabled together, reducing
power consumption.
Running the RTCC from LPRC will result in a loss of
accuracy in the RTCC of approximately 5 to 10%. If a
more accurate RTCC is required, it must be run from
the SOSC clock source. The RTCC clock source is
selected with the RTCOSC Configuration bit (FDS<5>).
Under certain circumstances, it is possible for the
DSWDT clock source to be off when entering Deep
Sleep mode. In this case, the clock source is turned on
automatically (if DSWDT is enabled), without the need
for software intervention. However, this can cause a
delay in the start of the DSWDT counters. In order to
avoid this delay when using SOSC as a clock source,
the application can activate SOSC prior to entering
Deep Sleep mode.
10.2.4.7
Checking and Clearing the Status of
Deep Sleep
Upon entry into Deep Sleep mode, the status bit
DPSLP (RCON<10>), becomes set and must be
cleared by the software.
On power-up, the software should read this status bit to
determine if the Reset was due to an exit from Deep
Sleep mode and clear the bit if it is set. Of the four
possible combinations of DPSLP and POR bit states,
three cases can be considered:
• Both the DPSLP and POR bits are cleared. In this
case, the Reset was due to some event other
than a Deep Sleep mode exit.
• The DPSLP bit is clear, but the POR bit is set.
This is a normal POR.
• Both the DPSLP and POR bits are set. This
means that Deep Sleep mode was entered, the
device was powered down and Deep Sleep mode
was exited.
DS39927B-page 104
10.2.4.8
Power-on Resets (
V
voltage is monitored to produce PORs. Since exit-
DD
ing from Deep Sleep functionally looks like a POR, the
technique described in Section 10.2.4.7 “Checking
and Clearing the Status of Deep Sleep” should be
used to distinguish between Deep Sleep and a true
POR event.
The
When a true POR occurs, the entire device, including
by
the
all Deep Sleep logic (Deep Sleep registers, RTCC,
DSWDT, etc.) is reset.
10.2.4.9
Summary of Deep Sleep Sequence
To review, these are the necessary steps involved in
invoking and exiting Deep Sleep mode:
1.
Device exits Reset and begins to execute its
application code.
2.
If DSWDT functionality is required, program the
appropriate Configuration bit.
3.
Select the appropriate clock(s) for the DSWDT
and RTCC (optional).
4.
Enable and configure the DSWDT (optional).
5.
Enable and configure the RTCC (optional).
6.
Write context data to the DSGPRx registers
(optional).
7.
Enable the INT0 interrupt (optional).
8.
Set the DSEN bit in the DSCON register.
9.
Enter Deep Sleep by issuing a PWRSV
#SLEEP_MODE command.
10. Device exits Deep Sleep when a wake-up event
occurs.
11. The DSEN bit is automatically cleared.
12. Read and clear the DPSLP status bit in RCON,
and the DSWAKE status bits.
13. Read the DSGPRx registers (optional).
14. Once all state related configurations are
complete, clear the RELEASE bit.
15. Application resumes normal operation.
Preliminary
)
PORs
© 2009 Microchip Technology Inc.