IC PIC MCU FLASH 16K 28-SSOP

PIC24F16KA102-I/SS

Manufacturer Part NumberPIC24F16KA102-I/SS
DescriptionIC PIC MCU FLASH 16K 28-SSOP
ManufacturerMicrochip Technology
SeriesPIC® XLP™ 24F
PIC24F16KA102-I/SS datasheets
 


Specifications of PIC24F16KA102-I/SS

Program Memory TypeFLASHProgram Memory Size16KB (5.5K x 24)
Package / Case28-SSOPCore ProcessorPIC
Core Size16-BitSpeed32MHz
ConnectivityI²C, IrDA, SPI, UART/USARTPeripheralsBrown-out Detect/Reset, POR, PWM, WDT
Number Of I /o24Eeprom Size512 x 8
Ram Size1.5K x 8Voltage - Supply (vcc/vdd)1.8 V ~ 3.6 V
Data ConvertersA/D 9x10bOscillator TypeInternal
Operating Temperature-40°C ~ 85°CProcessor SeriesPIC24F
CorePICData Bus Width16 bit
Data Ram Size1.5 KBInterface TypeI2C/IrDA/SPI/UART
Maximum Clock Frequency32 MHzNumber Of Programmable I/os24
Number Of Timers3Operating Supply Voltage1.8 V to 3.6 V
Maximum Operating Temperature+ 85 CMounting StyleSMD/SMT
3rd Party Development Tools52713-733, 52714-737, 53276-922, EWDSPICDevelopment Tools By SupplierPG164130, DV164035, DV244005, DV164005, DM240001
Minimum Operating Temperature- 40 COn-chip Adc9-ch x 10-bit
Lead Free Status / RoHS StatusLead free / RoHS CompliantFor Use WithMA240017 - MODULE PLUG-IN PIC24F16KA102 PIM
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Page 139/254

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17.3
Setting Baud Rate When
Operating as a Bus Master
To compute the Baud Rate Generator (BRG) reload
value, use Equation 17-1.
EQUATION 17-1:
COMPUTING BAUD RATE
RELOAD VALUE
F
CY
F
=
--------------------------------------------------------------------- -
SCL
F
CY
I2C1BRG
+ +
1
----------------------------- -
,
10 000 000
or
F
F
CY
CY
I2C1BRG
=
----------- -
----------------------------- -
,
,
F
10 000 000
SCL
Note 1: Based on F
= F
/2, Doze mode and
CY
OSC
PLL are disabled.
2
TABLE 17-1:
I
C™ CLOCK RATES
Required
System
F
CY
F
SCL
100 kHz
16 MHz
100 kHz
8 MHz
100 kHz
4 MHz
400 kHz
16 MHz
400 kHz
8 MHz
400 kHz
4 MHz
400 kHz
2 MHz
1 MHz
16 MHz
1 MHz
8 MHz
1 MHz
4 MHz
Based on F
= F
/2, Doze mode and PLL are disabled.
Note 1:
CY
OSC
2
TABLE 17-2:
I
C™ RESERVED ADDRESSES
Slave
R/W
Address
Bit
General Call Address
0000 000
0
Start Byte
0000 000
1
Cbus Address
0000 001
x
Reserved
0000 010
x
Reserved
0000 011
x
HS Mode Master Code
0000 1xx
x
Reserved
1111 1xx
x
10-Bit Slave Upper Byte
1111 0xx
x
The address bits listed here will never cause an address match, independent of the address mask settings.
Note 1:
Address will be Acknowledged only if GCEN = 1.
2:
Match on this address can only occur on the upper byte in 10-Bit Addressing mode.
3:
© 2009 Microchip Technology Inc.
PIC24F16KA102 FAMILY
17.4
Slave Address Masking
The I2C1MSK register (Register 17-3) designates
address bit positions as “don’t care” for both 7-Bit and
10-Bit Addressing modes. Setting a particular bit
location (= 1) in the I2C1MSK register causes the slave
module to respond whether the corresponding address
bit value is ‘0’ or ‘1’. For example, when I2C1MSK is set
(1)
to ‘00100000’, the slave module will detect both
addresses: ‘0000000’ and ‘00100000’.
To enable address masking, the Intelligent Peripheral
,
Management Interface (IPMI) must be disabled by
clearing the IPMIEN bit (I2C1CON<11>).
As a result of changes in the I
Note:
the addresses in Table 17-2 are reserved
1
and will not be Acknowledged in Slave
mode. This includes any address mask
settings
addresses.
(1)
I2C1BRG Value
(Decimal)
(Hexadecimal)
157
9D
78
4E
39
27
37
25
18
12
9
4
13
6
3
(1)
Description
(2)
(3)
Preliminary
2
C protocol,
that
include
any
of
these
Actual
F
SCL
100 kHz
100 kHz
99 kHz
404 kHz
404 kHz
9
385 kHz
4
385 kHz
D
1.026 MHz
6
1.026 MHz
3
0.909 MHz
DS39927B-page 137