IC PIC MCU FLASH 16K 28-SSOP

PIC24F16KA102-I/SS

Manufacturer Part NumberPIC24F16KA102-I/SS
DescriptionIC PIC MCU FLASH 16K 28-SSOP
ManufacturerMicrochip Technology
SeriesPIC® XLP™ 24F
PIC24F16KA102-I/SS datasheets
 


Specifications of PIC24F16KA102-I/SS

Program Memory TypeFLASHProgram Memory Size16KB (5.5K x 24)
Package / Case28-SSOPCore ProcessorPIC
Core Size16-BitSpeed32MHz
ConnectivityI²C, IrDA, SPI, UART/USARTPeripheralsBrown-out Detect/Reset, POR, PWM, WDT
Number Of I /o24Eeprom Size512 x 8
Ram Size1.5K x 8Voltage - Supply (vcc/vdd)1.8 V ~ 3.6 V
Data ConvertersA/D 9x10bOscillator TypeInternal
Operating Temperature-40°C ~ 85°CProcessor SeriesPIC24F
CorePICData Bus Width16 bit
Data Ram Size1.5 KBInterface TypeI2C/IrDA/SPI/UART
Maximum Clock Frequency32 MHzNumber Of Programmable I/os24
Number Of Timers3Operating Supply Voltage1.8 V to 3.6 V
Maximum Operating Temperature+ 85 CMounting StyleSMD/SMT
3rd Party Development Tools52713-733, 52714-737, 53276-922, EWDSPICDevelopment Tools By SupplierPG164130, DV164035, DV244005, DV164005, DM240001
Minimum Operating Temperature- 40 COn-chip Adc9-ch x 10-bit
Lead Free Status / RoHS StatusLead free / RoHS CompliantFor Use WithMA240017 - MODULE PLUG-IN PIC24F16KA102 PIM
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Page 27/254

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4.0
MEMORY ORGANIZATION
As with Harvard architecture devices, the PIC24F
microcontrollers feature separate program and data
memory space and busing. This architecture also
allows the direct access of program memory from the
data space during code execution.
4.1
Program Address Space
The program address memory space of the PIC24F
devices is 4M instructions. The space is addressable by
a 24-bit value derived from either the 23-bit Program
Counter (PC) during program execution, or from a table
operation or data space remapping, as described in
Section 4.3 “Interfacing Program and Data Memory
Spaces”.
FIGURE 4-1:
PROGRAM SPACE MEMORY MAP FOR PIC24F16KA102 FAMILY DEVICES
PIC24F08KA102
GOTO Instruction
Reset Address
Interrupt Vector Table
Reserved
Alternate Vector Table
Flash
Program Memory
(2816 instructions)
Unimplemented
Read ‘0’
Data EEPROM
Reserved
Device Config Registers
Reserved
DEVID (2)
Memory areas are not displayed to scale.
Note:
© 2009 Microchip Technology Inc.
PIC24F16KA102 FAMILY
The user access to the program memory space is
restricted to the lower half of the address range
(000000h to 7FFFFFh). The exception is the use of
TBLRD/TBLWT operations, which use TBLPAG<7> to
permit access to the Configuration bits and Device ID
sections of the configuration memory space.
Memory maps for the PIC24F16KA102 family of
devices are displayed in Figure 4-1.
PIC24F16KA102
000000h
GOTO Instruction
000002h
Reset Address
000004h
Interrupt Vector Table
0000FEh
000100h
Reserved
000104h
Alternate Vector Table
0001FEh
000200h
User Flash
Program Memory
0015FEh
(5632 instructions)
002BFE
Unimplemented
Read ‘0’
7FFE00h
Data EEPROM
7FFFFFh
800000h
Reserved
F7FFFEh
F80000h
Device Config Registers
F80010h
F80012h
Reserved
FEFFFEh
FF0000h
DEVID (2)
FFFFFFh
Preliminary
DS39927B-page 25