word-addressable blocks. Although it is treated as
24 bits wide, it is more appropriate to think of each
address of the program memory as a lower and upper
word, with the upper byte of the upper word being
unimplemented. The lower word always has an even
address, while the upper word has an odd address
Program memory addresses are always word-aligned
on the lower word, and addresses are incremented or
decremented by two during code execution. This
arrangement also provides compatibility with data
memory space addressing and makes it possible to
access data in the program memory space.
HARD MEMORY VECTORS
All PIC24F devices reserve the addresses between
00000h and 000200h for hard coded program
execution vectors. A hardware Reset vector is provided
to redirect code execution from the default value of the
PC on device Reset to the actual start of code. A GOTO
instruction is programmed by the user at 000000h with
the actual address for the start of code at 000002h.
PIC24F devices also have two interrupt vector
tables, located from 000004h to 0000FFh and
000104h to 0001FFh. These vector tables allow each
of the many device interrupt sources to be handled
by separate ISRs. Section 8.1 “Interrupt Vector
(IVT) Table” discusses the interrupt vector tables
more in detail.
PROGRAM MEMORY ORGANIZATION
most significant word
(read as ‘0’)
In the PIC24F16KA102 family, the data EEPROM is
mapped to the top of the user program memory space,
starting at address 7FFE00 and expanding up to
The data EEPROM is organized as 16-bit wide memory
and 256 words deep. This memory is accessed using
table read and write operations similar to the user code
DEVICE CONFIGURATION WORDS
Table 4-1 provides the addresses of the device Config-
uration Words for the PIC24F16KA102 family. Their
location in the memory map is displayed in Figure 4-1.
Refer to Section 26.1 “Configuration Bits” for more
information on device Configuration Words.
least significant word
WORDS FOR PIC24F16KA102
© 2009 Microchip Technology Inc.