IC PIC MCU FLASH 16K 28-SSOP

PIC24F16KA102-I/SS

Manufacturer Part NumberPIC24F16KA102-I/SS
DescriptionIC PIC MCU FLASH 16K 28-SSOP
ManufacturerMicrochip Technology
SeriesPIC® XLP™ 24F
PIC24F16KA102-I/SS datasheets
 


Specifications of PIC24F16KA102-I/SS

Program Memory TypeFLASHProgram Memory Size16KB (5.5K x 24)
Package / Case28-SSOPCore ProcessorPIC
Core Size16-BitSpeed32MHz
ConnectivityI²C, IrDA, SPI, UART/USARTPeripheralsBrown-out Detect/Reset, POR, PWM, WDT
Number Of I /o24Eeprom Size512 x 8
Ram Size1.5K x 8Voltage - Supply (vcc/vdd)1.8 V ~ 3.6 V
Data ConvertersA/D 9x10bOscillator TypeInternal
Operating Temperature-40°C ~ 85°CProcessor SeriesPIC24F
CorePICData Bus Width16 bit
Data Ram Size1.5 KBInterface TypeI2C/IrDA/SPI/UART
Maximum Clock Frequency32 MHzNumber Of Programmable I/os24
Number Of Timers3Operating Supply Voltage1.8 V to 3.6 V
Maximum Operating Temperature+ 85 CMounting StyleSMD/SMT
3rd Party Development Tools52713-733, 52714-737, 53276-922, EWDSPICDevelopment Tools By SupplierPG164130, DV164035, DV244005, DV164005, DM240001
Minimum Operating Temperature- 40 COn-chip Adc9-ch x 10-bit
Lead Free Status / RoHS StatusLead free / RoHS CompliantFor Use WithMA240017 - MODULE PLUG-IN PIC24F16KA102 PIM
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PIC24F16KA102 FAMILY
4.1.1
PROGRAM MEMORY
ORGANIZATION
The
program
memory
space
is
word-addressable blocks. Although it is treated as
24 bits wide, it is more appropriate to think of each
address of the program memory as a lower and upper
word, with the upper byte of the upper word being
unimplemented. The lower word always has an even
address, while the upper word has an odd address
(Figure 4-2).
Program memory addresses are always word-aligned
on the lower word, and addresses are incremented or
decremented by two during code execution. This
arrangement also provides compatibility with data
memory space addressing and makes it possible to
access data in the program memory space.
4.1.2
HARD MEMORY VECTORS
All PIC24F devices reserve the addresses between
00000h and 000200h for hard coded program
execution vectors. A hardware Reset vector is provided
to redirect code execution from the default value of the
PC on device Reset to the actual start of code. A GOTO
instruction is programmed by the user at 000000h with
the actual address for the start of code at 000002h.
PIC24F devices also have two interrupt vector
tables, located from 000004h to 0000FFh and
000104h to 0001FFh. These vector tables allow each
of the many device interrupt sources to be handled
by separate ISRs. Section 8.1 “Interrupt Vector
(IVT) Table” discusses the interrupt vector tables
more in detail.
FIGURE 4-2:
PROGRAM MEMORY ORGANIZATION
msw
most significant word
Address
000001h
00000000
000003h
00000000
00000000
000005h
000007h
00000000
Program Memory
‘Phantom’ Byte
(read as ‘0’)
DS39927B-page 26
4.1.3
DATA EEPROM
In the PIC24F16KA102 family, the data EEPROM is
mapped to the top of the user program memory space,
organized
in
starting at address 7FFE00 and expanding up to
address 7FFFFF.
The data EEPROM is organized as 16-bit wide memory
and 256 words deep. This memory is accessed using
table read and write operations similar to the user code
memory.
4.1.4
DEVICE CONFIGURATION WORDS
Table 4-1 provides the addresses of the device Config-
uration Words for the PIC24F16KA102 family. Their
location in the memory map is displayed in Figure 4-1.
Refer to Section 26.1 “Configuration Bits” for more
information on device Configuration Words.
TABLE 4-1:
Configuration Word
FBS
FGS
FOSCSEL
FOSC
FWDT
FPOR
FICD
FDS
least significant word
23
16
8
Instruction Width
Preliminary
DEVICE CONFIGURATION
WORDS FOR PIC24F16KA102
FAMILY DEVICES
Configuration Word
Addresses
F80000
F80004
F80006
F80008
F8000A
F8000C
F8000E
F80010
PC Address
(lsw Address)
0
000000h
000002h
000004h
000006h
© 2009 Microchip Technology Inc.