IC PIC MCU FLASH 16K 28-SSOP

PIC24F16KA102-I/SS

Manufacturer Part NumberPIC24F16KA102-I/SS
DescriptionIC PIC MCU FLASH 16K 28-SSOP
ManufacturerMicrochip Technology
SeriesPIC® XLP™ 24F
PIC24F16KA102-I/SS datasheets
 


Specifications of PIC24F16KA102-I/SS

Program Memory TypeFLASHProgram Memory Size16KB (5.5K x 24)
Package / Case28-SSOPCore ProcessorPIC
Core Size16-BitSpeed32MHz
ConnectivityI²C, IrDA, SPI, UART/USARTPeripheralsBrown-out Detect/Reset, POR, PWM, WDT
Number Of I /o24Eeprom Size512 x 8
Ram Size1.5K x 8Voltage - Supply (vcc/vdd)1.8 V ~ 3.6 V
Data ConvertersA/D 9x10bOscillator TypeInternal
Operating Temperature-40°C ~ 85°CProcessor SeriesPIC24F
CorePICData Bus Width16 bit
Data Ram Size1.5 KBInterface TypeI2C/IrDA/SPI/UART
Maximum Clock Frequency32 MHzNumber Of Programmable I/os24
Number Of Timers3Operating Supply Voltage1.8 V to 3.6 V
Maximum Operating Temperature+ 85 CMounting StyleSMD/SMT
3rd Party Development Tools52713-733, 52714-737, 53276-922, EWDSPICDevelopment Tools By SupplierPG164130, DV164035, DV244005, DV164005, DM240001
Minimum Operating Temperature- 40 COn-chip Adc9-ch x 10-bit
Lead Free Status / RoHS StatusLead free / RoHS CompliantFor Use WithMA240017 - MODULE PLUG-IN PIC24F16KA102 PIM
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TABLE 4-20:
CLOCK CONTROL REGISTER MAP
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
RCON
0740
TRAPR
IOPUWR SBOREN
OSCCON
0742
COSC2
COSC1
COSC0
CLKDIV
0744
ROI
DOZE2
DOZE1
DOZE0
OSCTUN
0748
REFOCON
074E
ROEN
ROSSLP
ROSEL
HLVDCON
0756
HLVDEN
HLSIDL
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Legend:
RCON register Reset values are dependent on type of Reset.
Note
1:
OSCCON register Reset values are dependent on configuration fuses and by type of Reset.
2:
TABLE 4-21:
DEEP SLEEP REGISTER MAP
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
DSCON
0758
DSEN
DSWSRC
075A
DSGPR0
075C
DSGPR1
075E
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Legend:
The Deep Sleep registers are only reset on a V
Note
1:
DD
TABLE 4-22:
NVM REGISTER MAP
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
NVMCON
0760
WR
WREN
WRERR
PGMONLY
NVMKEY
0766
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Legend:
Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset.
Note
1:
TABLE 4-23:
PMD REGISTER MAP
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12 Bit 11
PMD1
0770
T3MD
T2MD T1MD
PMD2
0772
PMD3
0774
PMD4
0776
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Legend:
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
DPSLP
PMSLP
EXTR
SWR
NOSC2
NOSC1
NOSC0
CLKLOCK
DOZEN
RCDIV2
RCDIV1
RCDIV0
RODIV3
RODIV2
RODIV1 RODIV0
VDIR
BGVST
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
DSINT0
DSFLT
Deep Sleep General Purpose Register 0
Deep Sleep General Purpose Register 1
POR event.
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
ERASE
NVMKEY7
NVMKEY6
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
I2C1MD
U2MD
U1MD
IC1MD
CMPMD
RTCCMD
CRCPMD
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
SWDTEN
WDTO
SLEEP
IDLE
BOR
LOCK
CF
SOSCEN OSWEN (Note 2)
TUN5
TUN4
TUN3
TUN2
TUN1
IRVST
HLVDL3
HLVDL2
HLVDL1
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
DSBOR
RELEASE
DSWDT
DSRTCC DSMCLR
DSPOR
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
NVMOP5
NVMOP4
NVMOP3
NVMOP2
NVMOP1
NVMKEY5 NVMKEY4 NVMKEY3 NVMKEY2 NVMKEY1 NVMKEY0 0000
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SPI1MD
ADC1MD
OC1MD
EEMD
REFOMD
CTMUMD
HLVDMD
All
Bit 0
Resets
POR
(Note 1)
3140
TUN0
0000
0000
HLVDL0
0000
All
Bit 0
(1)
Resets
0000
0000
0000
0000
All
Bit 0
Resets
(1)
NVMOP0
0000
All Resets
0000
0000
0000
0000