IC PIC MCU FLASH 16K 28-SSOP

PIC24F16KA102-I/SS

Manufacturer Part NumberPIC24F16KA102-I/SS
DescriptionIC PIC MCU FLASH 16K 28-SSOP
ManufacturerMicrochip Technology
SeriesPIC® XLP™ 24F
PIC24F16KA102-I/SS datasheets
 


Specifications of PIC24F16KA102-I/SS

Program Memory TypeFLASHProgram Memory Size16KB (5.5K x 24)
Package / Case28-SSOPCore ProcessorPIC
Core Size16-BitSpeed32MHz
ConnectivityI²C, IrDA, SPI, UART/USARTPeripheralsBrown-out Detect/Reset, POR, PWM, WDT
Number Of I /o24Eeprom Size512 x 8
Ram Size1.5K x 8Voltage - Supply (vcc/vdd)1.8 V ~ 3.6 V
Data ConvertersA/D 9x10bOscillator TypeInternal
Operating Temperature-40°C ~ 85°CProcessor SeriesPIC24F
CorePICData Bus Width16 bit
Data Ram Size1.5 KBInterface TypeI2C/IrDA/SPI/UART
Maximum Clock Frequency32 MHzNumber Of Programmable I/os24
Number Of Timers3Operating Supply Voltage1.8 V to 3.6 V
Maximum Operating Temperature+ 85 CMounting StyleSMD/SMT
3rd Party Development Tools52713-733, 52714-737, 53276-922, EWDSPICDevelopment Tools By SupplierPG164130, DV164035, DV244005, DV164005, DM240001
Minimum Operating Temperature- 40 COn-chip Adc9-ch x 10-bit
Lead Free Status / RoHS StatusLead free / RoHS CompliantFor Use WithMA240017 - MODULE PLUG-IN PIC24F16KA102 PIM
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Page 39/254

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4.2.5
SOFTWARE STACK
In addition to its use as a working register, the W15
register in PIC24F devices is also used as a Software
Stack Pointer. The pointer always points to the first
available free word and grows from lower to higher
addresses. It pre-decrements for stack pops and
post-increments for stack pushes, as depicted in
Figure 4-4.
For a PC push during any CALL instruction, the MSB of
the PC is zero-extended before the push, ensuring that
the MSB is always clear.
A PC push during exception processing
Note:
will concatenate the SRL register to the
MSB of the PC prior to the push.
The Stack Pointer Limit Value (SPLIM) register,
associated with the Stack Pointer, sets an upper
address boundary for the stack. SPLIM is uninitialized
at Reset. As is the case for the Stack Pointer,
SPLIM<0> is forced to ‘0’ as all stack operations must
be word-aligned. Whenever an EA is generated using
W15 as a source or destination pointer, the resulting
address is compared with the value in SPLIM. If the
contents of the Stack Pointer (W15) and the SPLIM
register are equal, and a push operation is performed,
a stack error trap will not occur. The stack error trap will
occur on a subsequent push operation.
Thus, for example, if it is desirable to cause a stack
error trap when the stack grows beyond address 0DF6
in RAM, initialize the SPLIM with the value, 0DF4.
Similarly, a Stack Pointer underflow (stack error) trap is
generated when the Stack Pointer address is found to
be less than 0800h. This prevents the stack from
interfering with the Special Function Register (SFR)
space.
A write to the SPLIM register should not be
Note:
immediately followed by an indirect read
operation using W15.
FIGURE 4-4:
CALL STACK FRAME
0000h
15
0
PC<15:0>
W15 (before CALL)
PC<22:16>
000000000
<Free Word>
W15 (after CALL)
POP : [--W15]
PUSH : [W15++]
© 2009 Microchip Technology Inc.
PIC24F16KA102 FAMILY
4.3
Interfacing Program and Data
Memory Spaces
The PIC24F architecture uses a 24-bit wide program
space and 16-bit wide data space. The architecture is
also a modified Harvard scheme, meaning that data
can also be present in the program space. To use this
data successfully, it must be accessed in a way that
preserves the alignment of information in both spaces.
Apart from the normal execution, the PIC24F
architecture provides two methods by which the
program space can be accessed during operation:
• Using table instructions to access individual bytes
or words anywhere in the program space
• Remapping a portion of the program space into
the data space, PSV
Table instructions allow an application to read or write
small areas of the program memory. This makes the
method ideal for accessing data tables that need to be
updated from time to time. It also allows access to all
bytes of the program word. The remapping method
allows an application to access a large block of data on
a read-only basis, which is ideal for look ups from a
large table of static data. It can only access the least
significant word (lsw) of the program word.
4.3.1
ADDRESSING PROGRAM SPACE
Since the address ranges for the data and program
spaces are 16 and 24 bits, respectively, a method is
needed to create a 23-bit or 24-bit program address
from 16-bit data registers. The solution depends on the
interface method to be used.
For table operations, the 8-bit Table Memory Page
Address register (TBLPAG) is used to define a 32K word
region within the program space. This is concatenated
with a 16-bit EA to arrive at a full 24-bit program space
address. In this format, the Most Significant bit (MSb) of
TBLPAG is used to determine if the operation occurs in
the user memory (TBLPAG<7> = 0) or the configuration
memory (TBLPAG<7> = 1).
For remapping operations, the 8-bit Program Space
Visibility Page Address register (PSVPAG) is used to
define a 16K word page in the program space. When
the MSb of the EA is ‘1’, PSVPAG is concatenated with
the lower 15 bits of the EA to form a 23-bit program
space address. Unlike the table operations, this limits
remapping operations strictly to the user memory area.
See Table 4-24 and Figure 4-5 to know how the
program EA is created for table operations and
remapping accesses from the data EA. Here, P<23:0>
refers to a program space word, whereas D<15:0>
refers to a data space word.
Preliminary
DS39927B-page 37