ATTINY24-15SSZ Atmel, ATTINY24-15SSZ Datasheet
ATTINY24-15SSZ
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ATTINY24-15SSZ Summary of contents
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... SOIC, 20-pin QFN/MLF: Twelve Programmable I/O Lines • Operating Voltage: – 2.7 - 5.5V for Atmel ATtiny24/44/84 • Speed Grade – Atmel ATtiny24/44/84 8MHz @ 2.7 - 5.5V 16MHz @ 4.5 - 5.5V • Automotive Temperature Range • Low Power Consumption – Active Mode: 1MHz, 2.7V: 800µ ...
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... Disclaimer Typical values contained in this data sheet are based on simulations and characterization of actual Atmel ATtiny24/44/84 AVR microcontrollers manufactured on the typical process tech- nology. Applicable Automotive Min. and Max. values will be available after devices representative of the whole process excursion (corner run) have been characterized. ...
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... Overview The Atmel enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the Atmel ATtiny24/44/84 achieves throughputs approaching 1MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1. VCC GND 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] ® ...
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... ISP flash allows the program memory to be re-programmed in-system through an SPI serial interface conventional non-volatile memory programmer on-chip boot code running on the AVR core. The Atmel ATtiny24/44/84 AVR is supported with a full suite of program and system develop- ment tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. ...
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... Port A has an alternate function as analog input for the ADC, analog comparator, timer/coun- ter, SPI and pin change interrupt as described in page 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] Section 12.3 “Alternate Port Functions” on page 60. ® ATtiny24/44/84 as 60. ...
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... For I/O registers located in the extended I/O map, IN, OUT, SBIS, SBIC, CBI, and SBI instruc- tions must be replaced with instructions that allow access to extended I/O, typically LDS and STS combined with SBRS, SBRC, SBR, and CBR. Atmel ATtiny24/44/84 [Preliminary] 6 7701D–AVR–09/10 ...
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... While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is in-system reprogrammable flash memory. 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] ® ® AVR core architecture in general. The main function of the ...
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... Note that the status register is updated after all ALU operations, as specified in the instruction set summary. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. Atmel ATtiny24/44/84 [Preliminary] 8 ® instructions have a single 16-bit word ® ...
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... The zero flag Z indicates a zero result in an arithmetic or logic operation. See the instruction set summary for detailed information. • Bit 0 – C: Carry Flag The carry flag C indicates a carry in an arithmetic or logic operation. See the instruction set summary for detailed information. 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary ...
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... The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indi- rect address registers X, Y, and Z are defined as described in Atmel ATtiny24/44/84 [Preliminary] 10 ® shows the structure of the 32 general purpose working registers in the ...
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... AVR this case, the SPH register will not be present. 5.6.1 SPH and SPL – Stack Pointer High and Low Bit 0x3E (0x5E) 0x3D (0x5D) Read/Write Initial Value 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] The X-, Y-, and Z-registers R27 (0x1B R29 (0x1D) ...
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... Interrupt Vectors. The complete list of vectors is shown in determines the priority levels of the different interrupts. The lower the address, the higher the priority level. RESET has the highest priority, and next is INT0, the external interrupt request 0. Atmel ATtiny24/44/84 [Preliminary] 12 ® ® AVR ...
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... CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence. Assembly Code Example C Code Example 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] in r16, SREG ; store SREG value ; disable interrupts during timed sequence cli sbi EECR, EEMPE ...
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... A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the program counter (two bytes) is popped back from the stack, the stack pointer is incremented by two, and the I-bit in SREG is set. Atmel ATtiny24/44/84 [Preliminary] 14 sei ; set Global Interrupt Enable sleep ...
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... This section describes the different memories in the Atmel tecture has two main memory spaces, the data memory space and the program memory space. In addition, the Atmel ATtiny24/44/84 features an EEPROM memory for data storage. All three memory spaces are linear and regular. ...
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... This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk page Figure 6-3. Atmel ATtiny24/44/84 [Preliminary] 16 ® ATtiny24/44/84 are all accessible through all these addressing Data Memory Map Data Memory 32 Registers 64 I/O Registers Internal SRAM (128/256/512 ...
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... Atmel ATtiny24/44/84 [Preliminary] ® ATtiny24/44/84 contains 128/256/512 bytes of EEPROM data memory orga- “Preventing EEPROM Corruption” on page 20 “Atomic Byte Programming” on page 17 “Serial Downloading” on page 166. ...
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... The following code examples show one assembly function and one C function for erase, write, or atomic write of the EEPROM. The examples assume that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions. Atmel ATtiny24/44/84 [Preliminary] 18 32. “Oscillator Calibration Register – OSCCAL” on ...
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... Assembly Code Example C Code Example Note: 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] EEPROM_write: ; Wait for completion of previous write sbic EECR,EEPE rjmp EEPROM_write ; Set Programming mode r16, (0<<EEPM1)|(0<<EEPM0) ldi EECR, r16 out ; Set up address (r17) in address register out EEARL, r17 ...
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... BOD does not match the needed detection level, an external low-V circuit can be used reset occurs while a write operation is in progress, the write operation will be completed provided the power supply voltage is sufficient. Atmel ATtiny24/44/84 [Preliminary] 20 EEPROM_read: ; Wait for completion of previous write ...
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... The I/O space definition of the Atmel page All Atmel ATtiny24/44/84 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions ...
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... Bit 0 – EEAR8: EEPROM Address The EEPROM address register, EEARH, specifies the most-significant bit for EEPROM address in the 512-byte EEPROM space for Tiny84. This bit is reserved in the ATtiny24/44, and will always read as zero. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed ...
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... Bit 6 – Res: Reserved Bit This bit is reserved in the Atmel ATtiny24/44/84 and will always read as zero. • Bits 5, 4 – EEPM1 and EEPM0: EEPROM Mode Bits The EEPROM programming mode bits define which programming action will be triggered when writing EEPE ...
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... GPIOR2 – General Purpose I/O Register 2 Bit 0x15 (0x35) Read/Write Initial Value 6.5.6 GPIOR1 – General Purpose I/O Register 1 Bit 0x14 (0x34) Read/Write Initial Value 6.5.7 GPIOR0 – General Purpose I/O Register 0 Bit 0x13 (0x33) Read/Write Initial Value Atmel ATtiny24/44/84 [Preliminary MSB R/W R/W R/W R ...
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... Flash Clock – clk FLASH The Flash clock controls operation of the Flash interface. The Flash clock is usually active simultaneously with the CPU clock. 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] presents the principal clock systems in the AVR Clock Distribution General I/O ADC ...
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... This default setting ensures that all users can make their desired clock source setting using an In-System or High-voltage Programmer. Atmel ATtiny24/44/84 [Preliminary] 26 Device Clocking Options Select 1. For all fuses “1” means unprogrammed while “0” means programmed. ...
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... Table 7-3. CKSEL3..1 100 Notes: The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown in Table 7-4 on page 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] Table 7-3 on page Crystal Oscillator Connections 27. Crystal Oscillator Operating Modes Frequency Range (MHz) (1) 0.4 - 0.9 101 0 ...
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... C1 and C2. When this oscillator is selected, start-up times are determined by the SUT fuses as shown in Table Table 7-5. SUT1.. Notes: Atmel ATtiny24/44/84 [Preliminary] 28 Start-up Times for the Crystal Oscillator Clock Selection Start-up Time from Power-down and SUT1..0 Power-save ( ...
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... To drive the device from an external clock source, CLKI should be driven as shown in 7-3 on page grammed to “0000”. 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] and “Internal Oscillator Speed” on page 203 7-6. If selected, it will operate with no external components. During reset, hardware Table 22-2 on page 179 ...
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... MCU is kept in reset during such changes in the clock frequency. Note that the system clock prescaler can be used to implement run-time changes of the inter- nal clock frequency while still ensuring stable operation. See page 31 Atmel ATtiny24/44/84 [Preliminary] 30 External Clock Drive Configuration EXTERNAL CLOCK SIGNAL 30 ...
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... Start-up Times for the 128kHz Internal Oscillator Start-up Time from Power-down and Power-save 6CK 6CK 6CK ® ATtiny24/44/84 system clock can be divided by setting the Clock Prescaler Regis- are divided by a factor as shown in Additional Delay from Reset Recommended Usage 14CK BOD enabled ...
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... Table 22-2 on page Table 22-2 on page 179. Calibration outside that range is not guaranteed CLKPCE – – – R ® ATtiny24/44/84 and will always read as zero. Table 7-10 on page 33 CAL3 CAL2 CAL1 CAL0 R/W R/W R/W R/W 179. The application software can write this ...
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... CKDIV8 Fuse setting. The Application software must ensure that a sufficient division factor is chosen if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed. Table 7-10. CLKPS3 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] Clock Prescaler Select CLKPS2 CLKPS1 ...
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... When the SM1..0 bits are written to “00”, the SLEEP instruction makes the MCU enter idle mode, stopping the CPU but allowing the analog comparator, ADC, timer/counter, watch- dog, and interrupt system to continue operating. This sleep mode basically halts clk clk FLASH Atmel ATtiny24/44/84 [Preliminary] 34 ® ® AVR ...
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... Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall power consumption. See sleep modes, the clock is already stopped. 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] , while allowing the other clocks to run. for details “Power-down Supply Current” on page 193 ...
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... Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current con- sumption. See Timer. Atmel ATtiny24/44/84 [Preliminary] 36 ® -controlled system. In general, sleep modes should be used as much as possible, and “ ...
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... ADC Noise Reduction 1 0 Power-down 1 1 Standby 1. Only recommended with external crystal or resonator selected as clock source ® ATtiny24/44/84 and will always read as zero. ) are stopped, the input buffers of the ADC /2, the input buffer will use excessive power. CC for details SM1 SM0 — ...
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... Read/Write Initial Value • Bits Res: Reserved Bits These bits are reserved bits in the ATtiny24/44/84 and will always read as zero. • Bit 3- PRTIM1: Power Reduction Timer/Counter1 Writing a logical one to this bit shuts down the timer/counter 1 module. When the timer/counter 1 is enabled, operation will continue like before the shutdown. ...
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... Fuses. The different selections for the delay period are presented in 26. 9.2 Reset Sources The Atmel ATtiny24/44/84 has four sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length when RESET function is enabled. • ...
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... A POR circuit ensures that the device is reset from power-on. Reaching the power-on reset threshold voltage invokes the delay counter, which determines how long the device is kept in RESET after V decreases below the detection level. Figure 9-2. V TIME-OUT INTERNAL Atmel ATtiny24/44/84 [Preliminary] 40 Reset Logic Power-on Reset Circuit Brown-out BODLEVEL [1..0] Reset Circuit ...
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... Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage – V its positive edge, the delay counter starts the MCU after the Time-out period – t expired. 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] MCU Start-up, RESET Extended Externally V POT V ...
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... Figure 9-4. 9.5 Brown-out Detection ATtiny24/44/84 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V during operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as ...
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... The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs. Ten dif- ferent clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog Reset, the Atmel ATtiny24/44/84 resets and executes from the Reset Vector. For timing details on the Watchdog Reset, refer to The Wathdog Timer can also be configured to generate an interrupt instead of a reset ...
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... WDE must be written to one to start the timed sequence. 2. Within the next four clock cycles, in the same operation, write the WDP bits as desired, but with the WDCE bit cleared. The value written to the WDE bit is irrelevant. Atmel ATtiny24/44/84 [Preliminary] 44 WDT Configuration as a Function of the Fuse Settings of WDTON ...
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... Initial Value • Bits 7..4 – Res: Reserved Bits These bits are reserved bits in the ATtiny24/44/84 and will always read as zero. • Bit 3 – WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset writing a logical zero to the flag. • ...
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... Bits 5, 2..0 – WDP3..0: Watchdog Timer Prescaler and 0 The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. The different prescaling values and their corresponding Timeout Periods are shown in Table 9-4 on page Atmel ATtiny24/44/84 [Preliminary] 46 Watchdog Timer Configuration WDIE Watchdog Timer State ...
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... Table 9-4. WDP3 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] Watchdog Timer Prescale Select Number of WDT Oscillator WDP2 WDP1 WDP0 Typical Time-out at Cycles cycles 16ms 4K cycles 32ms 8K cycles 64ms 16K cycles 0.125s 32K cycles 0.25s 64K cycles 0.5s 128K cycles 1.0s 256K cycles 2 ...
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... The following code example shows one assembly function and one C function for turning off the WDT. The example assumes that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions. Assembly Code Example C Code Example Note: Atmel ATtiny24/44/84 [Preliminary] 48 (1) WDT_off: WDR ; Clear WDRF in MCUSR ldi r16, (0< ...
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... Interrupts This section describes the specifics of the interrupt handling as performed in Atmel ATtiny24/44/84. For a general explanation of the AVR Interrupt Handling” on page 10.1 Interrupt Vectors Table 10-1. Vector No. 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] 12. Reset and Interrupt Vectors Program Address Source 1 0x0000 ...
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... Atmel ATtiny24/44/84 [Preliminary] 50 rjmp RESET rjmp EXT_INT0 rjmp PCINT0 rjmp PCINT1 rjmp WATCHDOG rjmp TIM1_CAPT rjmp TIM1_COMPA rjmp TIM1_COMPB rjmp TIM1_OVF rjmp ...
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... Pin Change Interrupt Timing An example of timing of a pin change interrupt is shown in Figure 11-1. Timing of pin change interrupts 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] “Clock Systems and their Distribution” on page “System Clock and Clock Options” on page pin_lat pcint_in_(0) PCINT(0) ...
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... Initial Value • Bits 7, 3..0 – Res: Reserved Bits These bits are reserved bits in the ATtiny24/44/84 and will always read as zero. • Bit 6 – INT0: External Interrupt Request 0 Enable When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled ...
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... Read/Write Initial Value • Bits 7, 3..0 – Res: Reserved Bits These bits are reserved bits in the ATtiny24/44/84 and will always read as zero. • Bit 6 – INTF0: External Interrupt Flag 0 When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set (logical one) ...
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... Each PCINT7..0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is set (logical one) and the PCIE0 bit in GIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is cleared, pin change interrupt on the cor- responding I/O pin is disabled. Atmel ATtiny24/44/84 [Preliminary ...
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... Most port pins are multiplexed with alternate functions for the peripheral features on the device. How each alternate function interferes with the port pin is described in Functions” on page alternate functions. 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] ® ® AVR ports have true read-modify-write functionality when used as general digital 55. See “ ...
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... If PORTxn is written logical one when the pin is configured as an input pin, the pull-up resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logical zero or the pin has to be configured as an output pin. The port pins are tri-stated when reset condition becomes active, even if no clocks are running. Atmel ATtiny24/44/84 [Preliminary] 56 (1) Pxn ...
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... The maximum and minimum propagation delays are denoted t respectively. 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] summarizes the control signals for the pin value. Port Pin Configurations PUD PORTxn ...
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... When reading back a software assigned pin value, a nop instruction must be inserted as indi- cated in positive edge of the clock. In this case, the delay t clock period. Figure 12-4. Synchronization when Reading a Software Assigned Pin Value INSTRUCTIONS Atmel ATtiny24/44/84 [Preliminary] 58 SYSTEM CLK XXX SYNC LATCH PINxn ...
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... SLEEP is overridden for port pins enabled as external interrupt pins. If the external interrupt request is not enabled, SLEEP is active also for these pins. SLEEP is also overridden by vari- ous other alternate functions as described in 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] (1) ... ; Define pull-ups and set outputs high ...
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... The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the Atmel microcontroller family. Atmel ATtiny24/44/84 [Preliminary] 60 shows how the port pin control signals from the simplified Figure 12-5 on ...
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... Figure 12-5. Alternate Port Functions Note: Table 12-2 on page 62 indexes from signals are generated internally in the modules having the alternate function. 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] PUOExn PUOVxn 1 0 DDOExn DDOVxn 1 0 PVOExn PVOVxn 1 Pxn 0 DIEOExn DIEOVxn 1 0 SLEEP PUOExn: ...
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... AIO The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function description for fur- ther details. Atmel ATtiny24/44/84 [Preliminary] 62 Generic Description of Overriding Signals for Alternate Functions Full Name ...
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... AREF pin by setting (one) the bit REFS0 in the ADC Multiplexer Selection Register (ADMUX). PCINT0: Pin Change Interrupt source 0. The PA0 pin can serve as an external interrupt source for pin change interrupt 0. 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] Port A Pins Alternate Functions Port Pin Alternate Function ADC0: ADC input channel 0. ...
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... Timer/Counter1 compare match B. The PA5 pin has to be configured as an output (DDA5 set (one)) to serve this function. The OC1B pin is also the output pin for the PWM mode timer function. PCINT5: Pin change interrupt source 5. The PA5 pin can serve as an external interrupt source for pin change interrupt 0. Atmel ATtiny24/44/84 [Preliminary ...
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... Table 12-4. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] to Table 12-6 on page 66 Figure 12-5 on page Overriding Signals for Alternate Functions in PA7..PA5 PA7/ADC7/OC0B/ICP1/ PA6/ADC6/DI/SDA/OC1A/ PCINT7 PCINT6 USIWM1 0 (SDA + PORTA6) • ...
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... PVOV PTOE DIEOE DIEOV DI AIO Table 12-6. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Atmel ATtiny24/44/84 [Preliminary] 66 Overriding Signals for Alternate Functions in PA4..PA2 PA4/ADC4/USCK/SCL/T1/ PCINT4 PA3/ADC3/T0/PCINT3 USIWM1 0 USI_SCL_HOLD + 0 PORTA4) • ADC4D USIWM1 • ADC4D USI_PTOE ...
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... It will also be output during reset. PCINT10: Pin change interrupt source 10. The PB2 pin can serve as an external interrupt source for pin change interrupt 1. 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] Port B Pins Alternate Functions Port Pin Alternate Function XTAL1: Crystal Oscillator Input. ...
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... Table 12-8. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 1. 2. Atmel ATtiny24/44/84 [Preliminary] 68 and Table 12-9 on page 69 Figure 12-5 on page Overriding Signals for Alternate Functions in PB3..PB2 RESET/dW/ PB3/ PCINT11 (1) RSTDISBL + DEBUGWIRE_ENABLE 1 (1) RSTDISBL + DEBUGWIRE_ENABLE (2) DEBUGWIRE_ENABLE • ...
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... Initial Value • Bits 7, 2– Res: Reserved Bits These bits are reserved bits in the ATtiny24/44/84 and will always read as zero. • Bit 6 – PUD: Pull-up Disable When this bit is written to logical one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01) ...
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... Read/Write Initial Value 12.4.6 DDRB – Port B Data Direction Register Bit 0x17 (0x37) Read/Write Initial Value 12.4.7 PINB – Port BInput Pins Address Bit 0x16 (0x36) Read/Write Initial Value Atmel ATtiny24/44/84 [Preliminary DDA7 DDA6 DDA5 DDA4 R/W R/W R/W R/W 0 ...
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... TIFR0 and TIMSK0 are not shown in the figure. The Timer/Counter can be clocked internally, via the prescaler external clock source on the T0 pin. The Clock Select logic block controls which clock source and edge the 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] Figure 1-1 on page “Register Description” on page 83. ...
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... Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. ure 13-2 on page 72 Figure 13-2. Counter Unit Block Diagram Atmel ATtiny24/44/84 [Preliminary “Output Compare Unit” on page 73 Table 13-1 on page 72 are also used extensively throughout the document. ...
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... The max and bottom signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation. See 76. Figure 13-3 on page 74 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] count Increment or decrement TCNT0 by 1. direction Select between increment and decrement. ...
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... All CPU write operations to the TCNT0 Register will block any Compare Match that occur in the next timer clock cycle, even when the timer is stopped. This feature allows OCR0x to be initialized to the same value as TCNT0 without triggering an interrupt when the Timer/Counter clock is enabled. Atmel ATtiny24/44/84 [Preliminary] 74 DATA BUS OCRnx ...
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... The data direction register bit for the OC0x pin (DDR_OC0x) must be set as output before the OC0x value is vis- ible on the pin. The port override function is independent of the waveform generation mode. 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] COMnx1 Waveform COMnx0 ...
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... OCR0A. The OCR0A defines the top value for the coun- ter, hence also its resolution. This mode allows greater control of the compare match output frequency. It also simplifies the operation of counting external events. Atmel ATtiny24/44/84 [Preliminary] 76 “Register Description” on page 83 83, and for phase correct PWM refer to “ ...
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... Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct PWM mode that uses dual-slope operation. 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary when OCR0A is set to zero (0x00). The waveform frequency is defined by the fol- ...
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... TCNT0, and clearing (or setting) the OC0x register at the timer clock cycle when the coun- ter is cleared (changes from top to bottom). The PWM frequency for the output can be calculated by the following equation: f OCnxPWM The variable N represents the prescale factor (1, 8, 64, 256, or 1024).. Atmel ATtiny24/44/84 [Preliminary] 78 Figure 13-6 on page ...
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... The diagram includes non-inverted and inverted PWM outputs. The small horizontal lines on the TCNT0 slopes rep- resent compare matches between OCR0x and TCNT0. 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] Figure 13-7 on page 80. The TCNT0 value is in the timing diagram, which when OCR0A is set to zero ...
Page 80
... PWM mode. For inverted PWM, the output will have the opposite logic values. At the very start of period 2 in even though there is no compare match. The point of this transition is to guarantee symmetry around bottom. There are two cases that give a transition without a compare match. Atmel ATtiny24/44/84 [Preliminary ...
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... TCNTn Figure 13-9 on page 81 Figure 13-9. Timer/Counter Timing Diagram, with Prescaler (f (clk TCNTn Figure 13-10 on page 82 except CTC mode and PWM mode, where OCR0A is TOP. 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] Figure 13-8 on page 81 clk I/O clk Tn /1) I/O MAX - 1 TOVn shows the same timing data, but with the prescaler enabled ...
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... OCFnx Figure 13-11 on page 82 and fast PWM mode where OCR0A is TOP. Figure 13-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with (clk TCNTn (CTC) OCRnx OCFnx Atmel ATtiny24/44/84 [Preliminary] 82 clk I/O clk Tn /8) I/O OCRnx - 1 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode ...
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... When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the WGM02:0 bit setting. WGM02:0 bits are set to a normal or CTC mode (non-PWM). Table 13-2. COM01 Table 13-3 on page 83 to fast PWM mode. Table 13-3. COM01 Note: 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary COM0A1 COM0A0 COM0B1 R/W R/W R/W 0 ...
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... WGM02:0 bits are set to a normal or CTC mode (non-PWM). Table 13-5. COM01 Table 13-3 on page 83 to fast PWM mode. Table 13-6. COM01 Atmel ATtiny24/44/84 [Preliminary] 84 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set Compare Output Mode, Phase Correct PWM Mode COM0A0 Description 0 0 Normal port operation, OC0A disconnected ...
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... Note: • Bits 3, 2 – Res: Reserved Bits These bits are reserved bits in the ATtiny24/44/84 and will always read as zero. • Bits 1:0 – WGM01:0: Waveform Generation Mode Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting ...
Page 86
... OCR0B as TOP. The FOC0B bit is always read as zero. • Bits 5:4 – Res: Reserved Bits These bits are reserved bits in the ATtiny24/44/84, and will always read as zero. • Bit 3 – WGM02: Waveform Generation Mode See the description in the • Bits 2:0 – CS02:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter ...
Page 87
... The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare interrupt generate a waveform output on the OC0B pin. 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] Clock Select Bit Description CS01 CS00 Description ...
Page 88
... Initial Value • Bits 7..3 – Res: Reserved Bits These bits are reserved bits in the ATtiny24/44/84 and will always read as zero. • Bit 2- OCIE0B: Timer/Counter 0 Output Compare Match B Interrupt Enable When the OCIE0B bit is written to one, and the I-bit in the status register is set, the timer/coun- ter 0 compare match B interrupt is enabled ...
Page 89
... When the SREG I-bit, TOIE0 (timer/counter 0 overflow inter- rupt enable), and TOV0 are set, the timer/counter 0 overflow interrupt is executed. The setting of this flag is dependent of the WGM02:0 bit setting. See and “Waveform Generation Mode Bit Description” on page 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] 85. Table 13-8 on page 85 89 ...
Page 90
... I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-spe- cific I/O Register and bit locations are listed in the Atmel ATtiny24/44/84 [Preliminary] 90 Figure 14-1 on page ® “Pinout Atmel ATtiny24/44/84” on page “Register Description” on page 91. For 2. CPU 112. 7701D–AVR–09/10 ...
Page 91
... T1 pin. The clock select logic block controls which clock source and edge the timer/counter uses to increment (or decrement) its value. The timer/counter is inactive when no clock source is selected. The output from the clock select logic is referred to as the timer clock (clk 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] Count Clear Control Logic Direction ...
Page 92
... WGM13 is added to TCCR1B. The 16-bit Timer/Counter has improvements that will affect the compatibility in some special cases. Atmel ATtiny24/44/84 [Preliminary] 92 99. The compare match event will also set the compare match 133). The input capture unit includes a digital filtering unit (noise The counter reaches the BOTTOM when it becomes 0x0000 ...
Page 93
... OCR1A/B and ICR1 registers. Note that when using C, the compiler handles the 16-bit access. Assembly Code Examples C Code Examples Note: The assembly code example returns the TCNT1 value in the r17:r16 register pair. 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] (1) ... ; Set TCNT1 to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNT1H,r17 out TCNT1L,r16 ...
Page 94
... The following code examples show how atomic read of the TCNT1 Register contents. Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle. Assembly Code Example C Code Example Note: The assembly code example returns the TCNT1 value in the r17:r16 register pair. Atmel ATtiny24/44/84 [Preliminary] 94 (1) TIM16_ReadTCNT1: ; Save global interrupt flag in r18,SREG ...
Page 95
... The timer/counter can be clocked by an internal or an external clock source. The clock source is selected by the clock select logic which is controlled by the clock select (CS12:0) bits located in the timer/counter control register B (TCCR1B). For details on clock sources and prescaler, see 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] (1) TIM16_WriteTCNT1: ; Save global interrupt flag in r18,SREG ...
Page 96
... For more details about advanced counting sequences and waveform generation, see Atmel ATtiny24/44/84 [Preliminary] 96 Figure 14-2 on page 96 shows a block diagram of the counter and its surroundings. ...
Page 97
... When the low byte is read, the high byte is cop- ied into the high byte temporary register (TEMP). When the CPU reads the ICR1H I/O location, it will access the TEMP register. 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] DATA BUS TEMP (8-bit) ICRnH (8-bit) ...
Page 98
... Using the input capture unit in any mode of operation when the top value (resolution) is actively changed during operation is not recommended. Atmel ATtiny24/44/84 [Preliminary] 98 93. (Figure 15-1 on page “ ...
Page 99
... The elements of the block diagram that are not directly a part of the output compare unit are shaded gray. Figure 14-4. Output Compare Unit, Block Diagram 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] (“Modes of Operation” on page 102). shows a block diagram of the output compare unit. The small "n" in the ...
Page 100
... The easiest way of setting the OC1x value is to use the force output com- pare (1x) strobe bits in normal mode. The OC1x register keeps its value even when changing between waveform generation modes. Atmel ATtiny24/44/84 [Preliminary] 100 93. “Accessing 16-bit Regis- ...
Page 101
... The design of the Output Compare pin logic allows initialization of the OC1x state before the output is enabled. Note that some COM1x1:0 bit settings are reserved for certain modes of operation. See The COM1x1:0 bits have no effect on the Input Capture unit. 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] COMnx1 Waveform COMnx0 Generator ...
Page 102
... OCR1A or ICR1 define the top value for the counter, and hence also its resolution. This mode allows greater control of the compare match output frequency. It also simplifies the operation of counting external events. Atmel ATtiny24/44/84 [Preliminary] 102 Table 14-1 on page 112, and for phase correct and phase and frequency correct PWM refer to 113. (“ ...
Page 103
... PWM waveform generation option. The fast PWM differs from the other PWM options by its single-slope operation. The counter counts from bottom to top then restarts from bottom. 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary when OCR1A is set to zero (0x0000). The waveform frequency is ...
Page 104
... OC1A or ICF1 flag is set on the same timer clock cycle on which TOV1 is set when either OCR1A or ICR1 is used for defining the top value. If one of the interrupts are enabled, the interrupt handler routine can be used for updating the top and compare values. Atmel ATtiny24/44/84 [Preliminary] 104 R FPWM 104 ...
Page 105
... OC1A to toggle its logical level on each compare match (COM1A1:0 = 1). The wave- form generated will have a maximum frequency of (0x0000). This feature is similar to the OC1A toggle in CTC mode, except the double buffer feature of the output compare unit is enabled in the fast PWM mode. 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] f clk_I/O = ------------------------------------- ...
Page 106
... The small horizontal lines on the TCNT1 slopes represent compare matches between OCR1x and TCNT1. The OC1x interrupt flag will be set when a compare match occurs. Figure 14-8. Phase Correct PWM Mode, Timing Diagram TCNTn OCnx OCnx Period Atmel ATtiny24/44/84 [Preliminary] 106 TOP log R = ---------------------------------- - ...
Page 107
... TCNT1 and OCR1x while up-counting, and set on the compare match while down-counting. 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] 113). The actual OC1x value will only be visible on the port pin if the data direction for f ...
Page 108
... ICR1 is used for defining the top value, the OC1A or ICF1 flag is set accordingly when TCNT1 has reached top. The interrupt flags can then be used to generate an interrupt each time the counter reaches the top or bottom value. Atmel ATtiny24/44/84 [Preliminary] 108 and Figure 14-9 on page 108) ...
Page 109
... OCR1x register is updated with the OCR1x buffer value (only for modes utilizing double buffering). setting of OCF1x. 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] shows, the output generated is, in contrast to the phase correct 113). The actual OC1x value will only be visible on the port pin if the data f ...
Page 110
... PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOV1 flag at BOTTOM. Atmel ATtiny24/44/84 [Preliminary] 110 clk I/O ...
Page 111
... Figure 14-12. Timer/Counter Timing Diagram, no Prescaling Figure 14-13 on page 111 Figure 14-13. Timer/Counter Timing Diagram, with Prescaler (f 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] clk I/O clk Tn (clk /1) I/O TCNTn TOP - 1 (CTC and FPWM) TCNTn TOP - 1 (PC and PFC PWM) TOVn (FPWM) ...
Page 112
... When OC1A or OC1B is connected to the pin, the function of the COM1x1:0 bits is dependent on the WGM13:0 bit settings. when the WGM13:0 bits are set to a normal or CTC mode (non-PWM). Table 14-1. COM1A1/COM1B1 Table 14-2 on page 112 to the fast PWM mode. Table 14-2. COM1A1/COM1B1 Note: Atmel ATtiny24/44/84 [Preliminary] 112 COM1A1 COM1A0 COM1B1 R/W R/W ...
Page 113
... Pulse Width Modulation (PWM) modes (see ation” on page 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the phase Compare Output Mode, Phase Correct and Phase and Frequency Correct ...
Page 114
... When a capture is triggered according to the ICES1 setting, the counter value is copied into the input capture register (ICR1). The event will also set the input capture flag (ICF1), and this can be used to cause an input capture interrupt, if this interrupt is enabled. Atmel ATtiny24/44/84 [Preliminary] 114 (1) ...
Page 115
... The OC1A/OC1B output is changed according to its COM1x1:0 bit settings. Note that the FOC1A/FOC1B bits are implemented as strobes. Therefore the value present in the COM1x1:0 bits that determine the effect of the forced compare. 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] and Figure 14-11. Clock Select Bit Description ...
Page 116
... The output compare registers are 16 bits in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit registers. See Atmel ATtiny24/44/84 [Preliminary] 116 7 6 ...
Page 117
... Bit 0 – TOIE1: Timer/Counter1, Overflow Interrupt Enable When this bit is written to logical one and the I-flag in the status register is set (interrupts glob- ally enabled), the timer/counter 1 overflow interrupt is enabled. The corresponding interrupt vector (see 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary ...
Page 118
... The setting of this flag is dependent of the WGM13:0 bit settings. In normal and CTC modes, the TOV1 flag is set when the timer overflows. See behavior when using another WGM13:0 bit setting. TOV1 is automatically cleared when the timer/counter 1 overflow interrupt vector is executed. Alternatively, TOV1 can be cleared by writing a logical one to its bit location. Atmel ATtiny24/44/84 [Preliminary] 118 – ...
Page 119
... Enabling and disabling of the clock input must be done when Tn has been stable for at least one system clock cycle, otherwise there is a risk that a false timer/counter clock pulse could be generated. 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] ). Alternatively, one of four taps from the prescaler can be CLK_I/O /256 /1024 ...
Page 120
... Bit 0 – PSR10: Prescaler 0 Reset Timer/Counter n When this bit is set to one, the timer/counter n prescaler will be reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Atmel ATtiny24/44/84 [Preliminary] 120 < f /2) given a 50/50 duty cycle. Because the edge detector ...
Page 121
... The serial input is always sampled from the data input (DI) pin independent of the configuration. 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] ® “Pinout Atmel ATtiny24/44/84” on page “Register Descriptions” on page USIDR ...
Page 122
... The counter overflow (interrupt) flag, or USIOIF, can therefore be used to deter- mine when a transfer is completed. The clock is generated by the master device software by toggling the USCK pin via the PORT register writing a logical one to the USITC bit in USICR. Atmel ATtiny24/44/84 [Preliminary] 122 Bit7 Bit6 ...
Page 123
... The data bytes transferred must now be processed before a new transfer can be initiated. The overflow interrupt will wake up the processor set to idle mode. Depending on the protocol used, the slave device can now set its out- put to high impedance. 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] ( Reference ) 1 2 USCK ...
Page 124
... The fourth and fifth instructions set the three-wire mode, positive edge shift register clock, count at USITC strobe, and toggle USCK. The loop is repeated 16 times. The following code demonstrates how to use the USI module as an SPI master with maximum speed (f SPITransfer_Fast: Atmel ATtiny24/44/84 [Preliminary] 124 out USIDR,r16 ldi r16,(1< ...
Page 125
... Note that the first two instructions are for initialization only and need only to be executed once. These instructions set the three-wire mode and positive edge shift register clock. The loop is repeated until the USI counter overflow flag is set. 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] out USICR,r17 in ...
Page 126
... The master generates clock by the by toggling the USCK pin via the PORT register. The data direction is not given by the physical layer. A protocol, like the one used by the TWI-bus, must be implemented to control the data flow. Atmel ATtiny24/44/84 [Preliminary] 126 Bit7 Bit6 ...
Page 127
... If the slave is not able to receive more data, it does not acknowledge the data byte it has last received. When the master does a read operation, it must terminate the operation by forcing the acknowledge bit low after the last byte is transmitted. Figure 16-6. Start Condition Detector, Logic Diagram 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] SDA SCL ...
Page 128
... The overflow flag and interrupt enable bit are then used for the external interrupt. This feature is selected by the USICS1 bit. 16.4.5 Software Interrupt The counter overflow interrupt can be used as a software interrupt triggered by a clock strobe. Atmel ATtiny24/44/84 [Preliminary] 128 Figure 16-6 on page “Clock Systems and their Distribution” on page for further details. ...
Page 129
... When two-wire mode is selected, the USISIF flag is set (one) when a start condition is detected. When output disable mode or three-wire mode is selected and (USICSx = 0b11 and USICLK = 0) or (USICS = 0b10 and USICLK = 0), any edge on the SCK pin sets the flag. 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary ...
Page 130
... USICR – USI Control Register Bit 0x0D (0x2D) Read/Write Initial Value The Control Register includes interrupt enable control, wire mode setting, Clock Select setting, and clock strobe. Atmel ATtiny24/44/84 [Preliminary] 130 USISIE USIOIE USIWM1 ...
Page 131
... The relation between USIWM1..0 and USI operation is summarized in Table 16-1. USIWM1 Note: 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] Relations between USIWM1..0 and the USI Operation USIWM0 Description 0 0 Outputs, clock hold, and start detector disabled. Port pins operate as normal. ...
Page 132
... When an external clock source is selected (USICS1 = 1) and the USICLK bit is set to one, writ- ing to the USITC strobe bit will directly clock the 4-bit counter. This allows an early detection of when the transfer is done when operating as a master device. Atmel ATtiny24/44/84 [Preliminary] 132 shows the relationship between the USICS1..0 and USICLK settings Relations between the USICS1 ...
Page 133
... ADCSRB) is set and the ADC is switched off (ADEN in ADCSRA is zero), MUX1..0 in ADMUX select the input pin to replace the negative input to the analog comparator, as shown in 17-1. If ACME is cleared or ADEN is set, AIN1 is applied to the negative input of the analog comparator. 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] Figure 17-1 on page 133. BANDGAP REFERENCE ...
Page 134
... When this bit is cleared, AIN0 is applied to the positive input of the analog comparator. • Bit 5 – ACO: Analog Comparator Output The output of the analog comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of one to two clock cycles. Atmel ATtiny24/44/84 [Preliminary] 134 Analog Comparator Multiplexed Input ADEN MUX4..0 ...
Page 135
... PIN register bit will always read as zero when this bit is set. When an analog signal is applied to the AIN1/0 pin and the digital input from this pin is not needed, this bit should be written logical one to reduce power consumption in the digital input buffer. 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] Table 17-2. ACIS1/ACIS0 Settings ...
Page 136
... There is also an option to use an external voltage reference and turn off the internal voltage reference. Atmel ATtiny24/44/84 [Preliminary] 136 ADC Input Voltage Range CC ® ATtiny24/44/84 features a 10-bit successive approximation analog-to-digital con- 137. Figure 7701D–AVR–09/10 ...
Page 137
... ADC. For differential measurements, all adjacent analog inputs can be selected as an input pair. Every input can also be measured with ADC3. These pairs of differ- ential inputs are measured by the ADC through the differential gain amplifier. 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] ADTS2...ADTS0 8-BIT DATA BUS ADC CTRL. & STATUS B ...
Page 138
... Note that an interrupt flag will be set even if the specific interrupt is disabled or the global interrupt enable bit in SREG is cleared. A conver- sion can thus be triggered without causing an interrupt. However, the Interrupt Flag must be cleared in order to trigger a new conversion at the next interrupt event . Atmel ATtiny24/44/84 [Preliminary] 138 7701D–AVR–09/10 ...
Page 139
... If a lower resolution than 10 bits is needed, the input clock frequency to the ADC can be higher than 200kHz to get a higher sample rate.The ADC module contains a prescaler, which generates an acceptable ADC clock frequency from any CPU frequency above 100kHz. 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] ADTS[2:0] ADIF SOURCE 1 . ...
Page 140
... Figure 18-4. ADC Timing Diagram, First Conversion (Single Conversion Mode) Cycle Number ADC Clock ADEN ADSC ADIF ADCH ADCL Figure 18-5. ADC Timing Diagram, Single Conversion Cycle Number ADC Clock ADSC ADIF ADCH ADCL Atmel ATtiny24/44/84 [Preliminary] 140 141 MUX and REFS Update Sample & ...
Page 141
... Trigger Source ADATE ADIF ADCH ADCL Figure 18-7. ADC Timing Diagram, Free Running Conversion Table 18-1. Condition First conversion Normal conversions Auto Triggered conversions 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary Sample & Prescaler Hold Reset MUX and REFS Update One Conversion ...
Page 142
... The reference voltage for the ADC (V gle-ended channels that exceed V as either V after switching the reference voltage source may be inaccurate, and the user is advised to dis- card this result. Atmel ATtiny24/44/84 [Preliminary] 142 ) indicates the conversion range for the ADC. Sin- REF will result in codes close to 0x3FF. V REF , internal 1 ...
Page 143
... The user is advised to remove high-frequency components with a low-pass filter before applying the signals as inputs to the ADC. 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] mode must be selected and the ADC conversion complete interrupt must be enabled. once the CPU has been halted. ...
Page 144
... The lowest code is read as 0, and the highest code is read as 2 Several parameters describe the deviation from the ideal behavior: • Offset Error: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5LSB). Ideal value: 0LSB. Figure 18-9. Offset Error Atmel ATtiny24/44/84 [Preliminary] 144 I IH ADCn ...
Page 145
... Figure 18-11. Integral Non-linearity (INL) • Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1LSB). Ideal value: 0LSB. 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] Output Code Output Code Gain ...
Page 146
... The result is presented in one-sided form, from 0x3FF to 0x000. 18.8.2 Unipolar Differential Conversion If differential channels and an unipolar input mode are used, the result is where V and V Atmel ATtiny24/44/84 [Preliminary] 146 Output Code 0x3FF 1 LSB 0x000 0 ...
Page 147
... EEPROM for each chip as a part of the production test. The software calibration can be done utilizing the formula: where ADCn are the ADC data registers fixed coefficient and T sensor offset value determined and stored into EEPROM as a part of the production test. 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] V POS ADC ------------------------------------------------------- ...
Page 148
... Selecting the single-ended channel ADC8 enables the temperature measurement. See are changed during a conversion, the change will not go into effect until this conversion is complete (ADIF in ADCSRA is set). Atmel ATtiny24/44/84 [Preliminary] 148 ...
Page 149
... For offset calibration purposes, the offset of certain differential channels can be measured by selecting the same input for both negative and positive input. This calibration can be done for ADC0, ADC3, and ADC7. detailed manner. 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] Single Ended Input Channel Selections. Single Ended Input ADC0 (PA0) ADC1 (PA1) ...
Page 150
... Table 18-5. Positive Differential 1. Atmel ATtiny24/44/84 [Preliminary] 150 Differential Input channel Selections. Negative Differential Input Input ADC0 (PA0) ADC0 (PA0) ADC1 (PA1) ADC3 (PA3) ADC0 (PA0) ADC1 (PA1) ADC2 (PA2) ADC3 (PA3) ADC1 (PA1) ADC2 (PA2) ADC3 (PA3) ADC0 (PA0) ADC1 (PA1) ...
Page 151
... When this bit is written to logical one and the I-bit in SREG is set, the ADC conversion com- plete interrupt is activated. • Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits These bits determine the division factor between the system clock frequency and the input clock to the ADC. Table 18-6. 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary ADEN ADSC ADATE ...
Page 152
... If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adjusted. • ADC9:0: ADC Conversion Result These bits represent the result from the conversion, as detailed in on page Atmel ATtiny24/44/84 [Preliminary] 152 ADC Prescaler Selections (Continued) ADPS2 ADPS1 ...
Page 153
... See “ADCSRB – ADC Control and Status Register B” on page • Bit 5 – Res: Reserved Bit This bit is reserved bit in the Atmel® ATtiny24/44/84, and will always read as what was written there. • Bit 4 – ADLAR: ADC Left Adjust Result The ADLAR bit affects the presentation of the ADC conversion result in the ADC data register. ...
Page 154
... The corresponding PIN register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed, this bit should be written logical one to reduce power consumption in the digital input buffer. Atmel ATtiny24/44/84 [Preliminary] 154 ADC Auto Trigger Source Selections ...
Page 155
... Figure 19-1. The debugWIRE Setup Figure 19-1 on page 155 and the emulator connector. The system clock is not affected by debugWIRE and will always be the clock source selected by the CKSEL Fuses. 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] ® instructions in the CPU and to program the different non-volatile VCC dW ...
Page 156
... The debugWire data register (DWDR) provides a communication channel from the program running in the MCU to the debugger. This register is only accessible by the debugWIRE sys- tem, and can, therefore, not be used as a general purpose register in normal operations. Atmel ATtiny24/44/84 [Preliminary] 156 will not work. ...
Page 157
... SPMCSR also erased after a system reset. Note that it is not possible to write more than one time to each address without erasing the temporary buffer. If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be lost. 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] 157 ...
Page 158
... Page Erase and Page Write operation. The LPM instruction uses the Z-pointer to store the address. Because this instruction addresses the flash byte-by-byte, the LSB (bit Z0) of the Z-pointer is also used. Figure 20-1. Addressing the Flash During SPM Note: Atmel ATtiny24/44/84 [Preliminary] 158 ...
Page 159
... Flash program corruption can occur for two reasons when the voltage is too low. First, a regu- lar write sequence to the flash requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly if the supply voltage is too low. 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary – ...
Page 160
... Initial Value • Bits 7..5 – Res: Reserved Bits These bits are reserved bits in the ATtiny24/44/84 and always read as zero. • Bit 4 – CTPB: Clear Temporary Page Buffer If the CTPB bit is written while filling the temporary page buffer, the temporary page buffer will be cleared and the data will be lost. • ...
Page 161
... SPM instruction SPM instruction is executed within four clock cycles. During page erase and page write, the SPMEN bit remains high until the operation is completed. Writing any combination other than "10001", "01001", "00101", "00011", or "00001" in the lower five bits will have no effect. 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] 161 ...
Page 162
... Program And Data Memory Lock Bits The ATtiny24/44/84 provides two lock bits which can be left unprogrammed (set to one) or can be programmed (set to zero) to obtain the additional security listed in The lock bits can only be erased to one with the chip erase command. ...
Page 163
... Fuse High Byte RSTDISBL DWEN SPIEN WDTON EESAVE BODLEVEL2 BODLEVEL1 BODLEVEL0 Notes: 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] ® ATtiny24/44/84 has three fuse bytes. describe briefly the functionality of all the fuses and how they are mapped into the Fuse Extended Byte Bit No Description ...
Page 164
... Calibration Byte The signature area of the Atmel ATtiny24/44/84 has one byte of calibration data for the inter- nal RC oscillator. This byte resides in the high byte of address 0x000. During reset, this byte is automatically written into the OSCCAL register to ensure the correct frequency of the cali- brated RC oscillator ...
Page 165
... Page Size Table 21-7. Device ATtiny24 ATtiny44 ATtiny84 Table 21-8. Device ATtiny24 ATtiny44 ATtiny84 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] No. of Words in a Page and No. of Pages in the Flash Flash Size Page Size PCWORD 1K words 16 words PC[3:0] (2K bytes) 2K words 32 words PC[4:0] ...
Page 166
... Depending on the CKSEL fuses, a valid clock must be present. The minimum low and high periods for the serial clock (SCK) input are defined as follows: Low: > 2 CPU clock cycles for f High: > 2 CPU clock cycles for f Atmel ATtiny24/44/84 [Preliminary] 166 MOSI MISO ...
Page 167
... Serial Programming Algorithm When writing serial data to the Atmel edge of SCK. When reading data from the Atmel ATtiny24/44/84, data are clocked on the falling edge of SCK. See To program and verify the Atmel ATtiny24/44/84 in the serial programming mode, the following sequence is recommended (see four-byte instruction formats in 1 ...
Page 168
... Read Fuse High bits Read Extended Fuse Bits Read Calibration Byte (6) Write Instructions Write Program Memory Page Write EEPROM Memory Write EEPROM Memory Page (page access) Write Lock bits Atmel ATtiny24/44/84 [Preliminary] 168 power off. CC and Figure 21-2 on page 169 Byte 1 Byte 2 $AC ...
Page 169
... Figure 21-2. Serial Programming Instruction example Load Program Memory Page (High/Low Byte)/ Load EEPROM Memory Page (page access) Byte 1 Byte 2 A Adr Bit 15 B 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] Byte 1 $AC $AC $AC 169. Serial Programming Instruction Byte 3 Byte 4 Adr LSB ...
Page 170
... SDO SCI The minimum period for the Serial Clock Input (SCI) during High-voltage Serial Programming is 220ns. Table 21-13. Pin Values Used to Enter Programming Mode Pin PA0 PA1 PA2 Atmel ATtiny24/44/84 [Preliminary] 170 ® ATtiny24/44/84. +11.5 - 12.5V PB3 (RESET) SCI PB0 GND ...
Page 171
... High-voltage has been applied to ensure the Prog_enable signature HVRST has elapsed. HVRST RESET Pin High-voltage Threshold V HVRST 11.5V 11.5V ® ATtiny24/44/84 in the high-voltage serial program- Table 21-13 on page 170 to “000” and wait at least Minimum High-voltage Period for Latching Prog_enable Table 21-15 t HVRST 100ns 100ns ...
Page 172
... PAGE ADDRESS WITHIN THE FLASH PROGRAM MEMORY PAGE (1) memories, as well as lock bits. The lock 174). 165. When programming the flash, 174). ® ATtiny24/44/84, data are clocked on the ris- 185, Figure 21-3 on page 170 PAGEMSB PCWORD WORD ADDRESS WITHIN A PAGE PAGE PCWORD[PAGEMSB:0]: 00 ...
Page 173
... Reading the Signature Bytes and Calibration Byte The algorithms for reading the Signature bytes and Calibration byte are shown in on page 21.8.10 Power-off sequence Set SCI to “0”. Set RESET to “1”. Turn V 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary Table 21-15 on page 174): gramming cycle to finish ...
Page 174
... Table 21-15. High-voltage Serial Programming Instruction Set for ATtiny24/44/84 Instruction Instr.1/5 SDI 0_1000_0000_00 Chip Erase SII 0_0100_1100_00 SDO x_xxxx_xxxx_xx SDI 0_0001_0000_00 Load “Write Flash” SII 0_0100_1100_00 Command SDO x_xxxx_xxxx_xx SDI 0_ bbbb_bbbb _00 SII 0_0000_1100_00 SDO x_xxxx_xxxx_xx Load Flash Page Buffer ...
Page 175
... Table 21-15. High-voltage Serial Programming Instruction Set for ATtiny24/44/84 (Continued) Instruction Instr.1/5 SDI 0_bbbb_bbbb_00 SII 0_0000_1100_00 Write SDO x_xxxx_xxxx_xx EEPROM SDI 0_0000_0000_00 Byte SII 0_0110_0100_00 SDO x_xxxx_xxxx_xx SDI 0_0000_0011_00 Load “Read EEPROM” SII 0_0100_1100_00 Command SDO x_xxxx_xxxx_xx SDI 0_bbbb_bbbb_00 Read ...
Page 176
... The EEPROM is written page-wise. But only the bytes that are loaded into the page are actually written to the EEPROM. Page-wise EEPROM access is more efficient when multiple bytes are to be written to the same page. Note that auto-erase of EEPROM is not available in High-voltage Serial Programming, only in SPI Programming. Atmel ATtiny24/44/84 [Preliminary] 176 7701D–AVR–09/10 ...
Page 177
... Input Leakage I IHPORTB Current I/O Pin Input Leakage I ILPORTB Current I/O Pin R Reset Pull-up Resistor RST R I/O Pin Pull-up Resistor pu 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] *NOTICE: +0.5V CC ....................... ±5.0mA ( -40°C to 125° 2.7V to 5.5V (unless otherwise noted Condition Min 2.4V - 5.5V ...
Page 178
... ACLK Leakage Current Notes: 1. All DC Characteristics contained in this data sheet are based on actual silicon characterization of Atmel ATtiny24/44/84 AVR microcontrollers manufactured in corner run process technology. These values are preliminary values representing design targets, and will be updated after characterization of actual Automotive silicon. 2. “Max” means the highest value where the pin is guaranteed to be read as low. ...
Page 179
... Low Time CLCX t Rise Time CLCH t Fall Time CHCL t Change in period from one clock cycle to the next CLCL 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary 2.7V - 5.5V 2.7V - 5.5V 1. The overall jitter increase proportionally to the divider ratio V IH1 Temperature 25°C -40°C - 125°C -40° ...
Page 180
... Bandgap reference voltage BG t Bandgap reference start-up time BG I Bandgap reference current consumption BG Notes: 1. Values are guidelines only. 2. This is the limit to which VDD can be lowered without losing RAM data Table 22-5. Note: Atmel ATtiny24/44/84 [Preliminary] 180 Condition ( 2.7V 2.7V 2.7V BODLEVEL Fuse Coding BODLEVEL [2 ...
Page 181
... Offset Error Conversion Time Clock Frequency Vref External Voltage Reference V Input Voltage IN V Internal Voltage Reference INT R Analog Input Resistance AIN 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] Condition Min Single-ended conversion Single-ended conversion 4V, REF CC ADC clock = 200kHz Single-ended conversion 4V, ...
Page 182
... Table 22-7. ADC Characteristics, Differential Channels, T Symbol Parameter Resolution TUE Absolute Accuracy INL Integral Non-Linearity (INL) DNL Differential Non-linearity (DNL) Gain Error Atmel ATtiny24/44/84 [Preliminary] 182 = -40°C to 125°C A Condition Min Gain = 1x Gain = 20x Gain = 4V REF CC ADC clock = 50 - 200kHz Gain = 20x ...
Page 183
... Input Voltage IN V Input Differential Voltage DIFF 22.6 Serial Programming Characteristics Figure 22-3. Serial Programming Timing Figure 22-4. Serial Programming Waveforms 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] = -40°C to 125°C (Continued) A Condition Gain = 4V, V REF CC ADC clock = 50 - 200kHz Bipolar - Gain = 20x ...
Page 184
... Otherwise Noted) Parameter Oscillator Frequency (Atmel ATtiny24/44/84V) Oscillator Period (Atmel ATtiny24/44/84V) Oscillator Frequency (ATtiny24/44/84, V 5.5V) Oscillator Period (ATtiny24/44/84, V 5.5V) SCK Pulse Width High SCK Pulse Width Low MOSI Setup to SCK High MOSI Hold after SCK High SCK Low to MISO Valid 1 ...
Page 185
... High-voltage Serial Programming Characteristics Figure 22-5. High-voltage Serial Programming Timing Table 22-9. Symbol WLWH_PFB 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary High-voltage Serial Programming Characteristics T = 25°C ± 10 5.0V ± 10% (Unless otherwise noted Parameter SCI (PB0) Pulse Width High SHSL SCI (PB0) Pulse Width Low ...
Page 186
... Power-down mode with Watchdog Timer disabled represents the differential cur- rent drawn by the Watchdog Timer. 23.1 Active Supply Current Figure 23-1. Active Supply Current vs. Low Frequency (0.1 - 1.0MHz) - Temp.=25°C Atmel ATtiny24/44/84 [Preliminary] 186 = load capacitance operating voltage and f = average switching frequency ACTIVE CURRENT vs ...
Page 187
... Figure 23-2. Active Supply Current vs. Low Frequency (0.1 - 1.0MHz) - Temp.=125°C Figure 23-3. Active Supply Current vs. frequency (1 - 20MHz) - Temp.=25°C 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] ACTIVE CURRENT vs . LOW FREQUENCY 0.1 - 1.0 MHz - Temperature = 125˚C 1.2 1 0.8 0.6 0.4 ...
Page 188
... Figure 23-4. Active Supply Current vs. frequency (1 - 20MHz) - Temp.=125°C Figure 23-5. Active Supply Current vs. V Atmel ATtiny24/44/84 [Preliminary] 188 ACTIVE CURRENT vs . FREQUENCY MHz - Temperature = 125˚ Frequency (MHz) ACTIVE CURRENT INTERNAL RC OSCILLATOR, 8 MHz 2 (Internal RC Oscillator, 8MHz 4 ( ...
Page 189
... Figure 23-6. Active Supply Current vs. V Figure 23-7. Active Supply Current vs. V 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] ACTIVE CURRENT INTERNAL RC OSCILLATOR, 1MHz 1.4 1.2 1 0.8 0.6 0.4 0.2 0 2.5 3 3.5 ACTIVE CURRENT INTERNAL RC OSCILLATOR, 128 KHz 0.2 0.16 0.12 0.08 ...
Page 190
... Idle Supply Current Figure 23-8. Idle Supply Current vs. Low Frequency (0.1 - 1.0MHz) Figure 23-9. Idle Supply Current vs. Frequency (1 - 20MHz) Atmel ATtiny24/44/84 [Preliminary] 190 IDLE CURRENT vs . LOW FREQUENCY 0.1 - 1.0 MHz - Temperature = 125˚C 0.012 0.01 0.008 0.006 0.004 0.002 0 0 0.1 ...
Page 191
... Figure 23-10. Idle Supply Current vs. V Figure 23-11. Idle Supply Current vs. V 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] CC IDLE CURRENT INTERNAL RC OSCILLATOR, 8 MHz 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 2.5 3 3.5 CC IDLE CURRENT INTERNAL RC OSCILLATOR, 1 MHz 0.35 0.3 0.25 ...
Page 192
... Figure 23-12. Idle Supply Current vs. V Atmel ATtiny24/44/84 [Preliminary] 192 CC IDLE CURRENT INTERNAL RC OSCILLATOR, 128 KHz 0.035 0.03 0.025 0.02 0.015 0.01 0.005 0 2.5 3 3.5 (Internal RC Oscillator, 8MHz 4 (V) CC 125 ˚C 85 ˚C 25 ˚C -40 ˚C 5.5 7701D–AVR–09/10 ...
Page 193
... PRR bit PRTIM1 PRTIM0 PRUSI PRADC 23.4 Power-down Supply Current Figure 23-13. Power-down Supply Current vs. V 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] Additional Current Consumption for the different I/O modules (absolute values) Typical numbers 1MHz CC 6.6µA 8.7µA 5.5µA 22µ ...
Page 194
... Figure 23-14. Power-down Supply Current vs. V 23.5 Pin Pull-up Figure 23-15. I/O Pin Pull-up Resistor Current vs. input Voltage (V Atmel ATtiny24/44/84 [Preliminary] 194 P OWER-DOWN CURRENT WATCHDOG TIMER ENABLED 2.5 3 3.5 I ULL-UP RES IS TOR CURRENT vs . INP UT VOLTAGE 0.5 1 (Watchdog Timer Enabled 4 ( 2.7V 2. ...
Page 195
... Figure 23-16. I/O pin Pull-up Resistor Current vs. Input Voltage (V Figure 23-17. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] I ULL-UP RES IS TOR CURRENT vs . INP UT VOLTAGE 160 140 120 100 0.5 1 1.5 2 RES ET P ULL-UP RES IS TOR CURRENT vs . RES VOLTAGE 60 -40 ˚ ...
Page 196
... Figure 23-18. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V 23.6 Pin Driver Strength Figure 23-19. I/O Pin Output Voltage vs. Sink Current (V Atmel ATtiny24/44/84 [Preliminary] 196 RES ET P ULL-UP RES IS TOR CURRENT vs . RES VOLTAGE 120 -40 ˚C 100 125 ˚ 0.5 1 1.5 I OUTP UT VOLTAGE INK CURRENT LOW POWER PINS @ Vcc = 3V 0 ...
Page 197
... Figure 23-20. I/O pin Output Voltage vs. Sink Current (V Figure 23-21. I/O Pin Output Voltage vs. Source Current (V 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] I OUTP UT VOLTAGE INK CURRENT LOW POWER PINS - Vcc = 5.0V 0.7 0.6 0.5 0.4 0.3 0 OUTP UT VOLTAGE OURCE CURRENT LOW POWER PINS @ vcc = 3V 3 ...
Page 198
... Figure 23-22. I/O Pin output Voltage vs. Source Current (V 23.7 Pin Threshold and Hysteresis Figure 23-23. I/O Pin Input Threshold Voltage vs. V Atmel ATtiny24/44/84 [Preliminary] 198 I OUTP UT VOLTAGE OURCE CURRENT LOW POWER PINS @ vcc = 5V 5.1 5 4.9 4.8 4.7 4.6 4.5 4.4 4.3 ...
Page 199
... Figure 23-24. I/O Pin Input threshold Voltage vs. V Figure 23-25. I/O Pin Input Hysteresis vs. V 7701D–AVR–09/10 Atmel ATtiny24/44/84 [Preliminary] I INP UT THRES HOLD VOLTAGE VIL, IO PIN READ AS '0' 2.5 2 1.5 1 0.5 0 2.5 3 3.5 I INP UT HYS TERES 0.5 0.45 0.4 0.35 ...
Page 200
... Figure 23-26. Reset Input Threshold Voltage vs. V Figure 23-27. Reset Input Threshold Voltage vs. V Atmel ATtiny24/44/84 [Preliminary] 200 RES I/O THRES HOLD VOLTAGE VIH, RESET READ AS '1' 3 2.5 2 1.5 1 0.5 0 2.5 3 3.5 RES I/O THRES HOLD VOLTAGE VIL, RESET READ AS ' ...