AT89C55WD-24PU Atmel, AT89C55WD-24PU Datasheet
AT89C55WD-24PU
Specifications of AT89C55WD-24PU
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AT89C55WD-24PU Summary of contents
Page 1
... The on-chip Flash allows the program memory to be user programmed by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C55WD is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications ...
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... Pin Configurations 2.1 44A – 44-lead TQFP 2.2 44J – 44-lead PLCC 2.3 40P6 – 40-lead PDIP AT89C55WD 2 P1 P0.4 (AD4) P1 P0.5 (AD5) P1 P0.6 (AD6) RST 4 30 P0.7 (AD7) (RXD) P3 EA/VPP (TXD) P3 ALE/PROG (INT0) P3 PSEN (INT1) P3 P2.7 (A15) (T0) P3 P2.6 (A14 ...
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... PORT 0 RAM LATCH ACC TMP2 TMP1 ALU INTERRUPT, SERIAL PORT, AND TIMER BLOCKS PSW REGISTER PORT 1 LATCH WATCH DOG PORT 1 DRIVERS P1.0 - P1.7 AT89C55WD P2.0 - P2.7 PORT 2 DRIVERS PORT 2 QUICK LATCH FLASH PROGRAM STACK ADDRESS POINTER REGISTER BUFFER PC INCREMENTER PROGRAM COUNTER ...
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... Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash program- ming and verification. AT89C55WD 4 ) because of the internal pull-ups. IL Alternate Functions ...
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... As inputs, Port 3 pins that are externally being pulled low will source current (I Port 3 receives some control signals for Flash programming and verification. Port 3 also serves the functions of various special features of the AT89C55WD, as shown in the following table. Port Pin P3 ...
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... Input to the inverting oscillator amplifier and input to the internal clock operating circuit. 4.12 XTAL2 Output from the inverting oscillator amplifier. 5. Special Function Registers A map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 5-1. AT89C55WD SFR Map and Reset Values 0F8H B 0F0H 00000000 0E8H ACC ...
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... Timer 2 overflows or negative transitions occur at T2EX when EXEN2 = 1. When either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow. 1921D–MICRO–6/08 Table 5-2) for Timer 2. The register pair (RCAP2H, RCAP2L) are the RCLK TCLK EXEN2 AT89C55WD Reset Value = 0000 0000B TR2 C/T2 CP/RL2 Table 5- 7 ...
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... AUXR1: Auxiliary Register 1 AUXR1 Address = A2H Not Bit Addressable – Bit 7 – Reserved for future expansion DPS Data Pointer Register Select DPS 0 Selects DPTR Registers DP0L, DP0H 1 Selects DPTR Registers DP1L, DP1H AT89C55WD 8 – – WDIDLE DISRTO – – – – ...
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... Data Memory The AT89C55WD implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. That means the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space. ...
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... AT89C52. For more detailed information on the UART operation, please click on the document link below: http://www.atmel.com/dyn/resources/prod_documents/DOC4316.PDF 11. Timer 0 and 1 Timer 0 and Timer 1 in the AT89C55WD operate the same way as Timer 0 and Timer 1 in the AT89C51 and AT89C52. For further information on the timers’ operation, please click on the document link below: http://www.atmel.com/dyn/resources/prod_documents/DOC4316.PDF ...
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... When DCEN is set, Timer 2 can count up or down, depending on the value of the T2EX pin. 1921D–MICRO–6/08 Timer 2 Operating Modes CP/RL2 Figure 12-1. Table 12-2). Upon reset, the DCEN bit is set that timer 2 will default to AT89C55WD Table 5-2). Timer 2 has Table 5-2. TR2 MODE 1 16-bit Auto-Reload 1 16-bit Capture 1 Baud Rate Generator 0 (Off) 11 ...
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... The EXF2 bit toggles whenever Timer 2 overflows or underflows and can be used as a 17th bit of resolution. In this operating mode, EXF2 does not flag an interrupt. Figure 12-2. Timer 2 Auto Reload Mode (DCEN = 0) OSC T2EX PIN AT89C55WD 12 ÷12 C/ TR2 C/ ...
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... COUNTING RELOAD VALUE) 0FFH 0FFH OVERFLOW TH2 TL2 CONTROL TR2 RCAP2H RCAP2L (UP COUNTING RELOAD VALUE) AT89C55WD Reset Value = XXXX XX00B – T2OE DCEN TOGGLE EXF2 TF2 TIMER 2 INTERRUPT COUNT DIRECTION 1=UP 0=DO T2EX PIN ...
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... The RCAP2 registers may be read but should not be written to, because a write might overlap a reload and cause write and/or reload errors. The timer should be turned off (clear TR2) before accessing the Timer 2 or RCAP2 registers. AT89C55WD 14 Timer 2 Overflow Rate Modes 1 and 3 Baud Rates ...
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... Note, however, that the baud-rate and clock-out frequencies cannot be determined independently from one another since they both use RCAP2H and RCAP2L. 1921D–MICRO–6/08 C/ TH2 CONTROL TR2 C/ RCAP2H EXF2 CONTROL EXEN2 Clock-Out Frequency AT89C55WD TIMER 1 OVERFLOW ÷ 2 "0" "1" "1" "0" TL2 ÷ "1" "0" RCAP2L TIMER 2 ...
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... P1.1 (T2EX) 15. Interrupts The AT89C55WD has a total of six interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. These interrupts are all shown in Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE ...
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... IE.4 Serial Port interrupt enable bit. IE.3 Timer 1 interrupt enable bit. IE.2 External interrupt 1 enable bit. IE.1 Timer 0 interrupt enable bit. IE.0 External interrupt 0 enable bit. 0 INT0 1 TF0 0 INT1 1 TF1 TI RI TF2 EXF2 AT89C55WD (LSB) ET1 EX1 ET0 EX0 IE0 IE1 17 ...
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... Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before V operating level and must be held active long enough to allow the oscillator to restart and stabilize. AT89C55WD 18 Figure 18-1. Either a quartz crystal or Figure 18-2 ...
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... C1 ± for Crystals = 40 pF ± for Ceramic Resonators NC EXTERNAL OSCILLATOR SIGNAL Status of External Pins During Idle and Power-down Modes Program Memory ALE PSEN Internal 1 External 1 Internal 0 External 0 AT89C55WD XTAL2 XTAL1 GND XTAL2 XTAL1 GND PORT0 PORT1 PORT2 1 Data Data Data 1 Float Data Address 0 ...
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... Program Memory Lock Bits The AT89C55WD has three lock bits that can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the following table. Table 19-1. Program Lock Bits When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. ...
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... Wait for 150 ms. 7. Power V Data Polling: The AT89C55WD features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the writ- ten data on P0.7. Once the write cycle has been completed, true data is valid on all outputs, and the next cycle may begin ...
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... Read Device Read Device Notes: 1. Write Code Data requires a 200 ns PROG pulse. 2. Write Lock Bits requires a 100 µs PROG pulse. 3. Chip Erase requires a 200 ns - 500 ns PROG pulse. 4. RDY/BSY signal is output on P3.0 during programming. AT89C55WD 22 ALE/ EA/ PROG V P2.6 P2.7 P3.3 PP (1) 12V ...
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... P0 DATA P3.4 P2.6 P2.7 ALE PROG P3.3 P3.6 P3.7 XTAL2 RDY/ P3.0 BSY XTAL1 RST V IH GND PSEN 4.5V to 5.5V AT89C55WD V P1.0 - P1.7 CC PGM DATA P0 P2.0 - P2.5 (USE 10K P3.4 PULL-UPS) P2.6 P2.7 ALE P3.3 P3 P3.7 XTAL XTAL1 RST IH GND PSEN ...
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... GHSL PP t PROG Width GLGH t Address to Data Valid AVQV t ENABLE Low to Data Valid ELQV t Data Float After ENABLE EHQZ t PROG High to BUSY Low GHBL t Byte Write Cycle Time WC AT89C55WD 24 PP Min Max Units 11.5 12 MHz 48t CLCL 48t CLCL 48t CLCL ...
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... GLGH V LOGIC 1 PP LOGIC 0 t EHSH t ELQV t GHBL BUSY t WC 100 µs Test Conditions Setup 200 ns DC Erase 10 ms AT89C55WD VERIFICATION ADDRESS t AVQV DATA OUT t EHQZ READY V = 4.5V to 5.5V CC Wait reload new lock bit status DC Erase Erase V = 4.5V to 5.5V CC Wait 10 ms before ...
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... OL Port Ports Maximum total I for all output pins exceeds the test condition than the listed test conditions. 2. Minimum V for Power-down is 2V. CC AT89C55WD 26 *NOTICE: = -40°C to 85°C and V = 4.0V to 5.5V, unless otherwise noted Condition (Except EA) (Except XTAL1, RST) (XTAL1, RST 1 ...
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... CLCL 252 517 585 200 300 3t -50 CLCL 203 4t -75 CLCL 23 t -30 CLCL 433 7t -130 CLCL 33 t -25 CLCL 0 43 123 t -25 CLCL AT89C55WD Max Units 33 MHz -65 ns CLCL -60 ns CLCL ns t -25 ns CLCL ns 5t -80 ns CLCL -90 ns CLCL ns 2t ...
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... External Program Memory Read Cycle ALE PSEN PORT 0 PORT 2 30. External Data Memory Read Cycle ALE PSEN FROM RI OR DPL PORT 0 PORT 2 AT89C55WD 28 t LHLL t t AVLL LLIV t LLPL t PLIV t PLAZ t LLAX t PXIX INSTR IN t AVIV A8 - A15 t LHLL t LLDV t RLRH t LLWL ...
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... LHLL t t LLWL WLWH t LLAX t t QVWX AVLL t QVWH FROM RI OR DPL DATA OUT t AVWL P2 A15 FROM DPH t t CHCX CLCH CC - 0.1V t CLCX Min AT89C55WD t WHLH t WHQX FROM PCL INSTR A15 FROM PCH t CHCX t CLCL Max Units 33 MHz CHCL 29 ...
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... Clock Rising Edge to Input Data Valid XHDV 35. Shift Register Mode Timing Waveforms INSTRUCTION 0 ALE CLOCK t QVXH WRITE TO SBUF OUTPUT DATA CLEAR RI INPUT DATA 36. AC Testing Input/Output Waveforms Note: (1) 37. Float Waveforms V Note: AT89C55WD 30 = 4.0V to 5.5V and Load Capacitance = 80 pF MHz Osc Min 1.0 700 XLXL t XHQX 0 1 ...
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... Thin Plastic Gull Wing Quad Flatpack (TQFP) 44J 44-lead, Plastic J-leaded Chip Carrier (PLCC) 40P6 40-pin, 0.600" Wide, Plastic Dual Inline Package (PDIP) 1921D–MICRO–6/08 Ordering Code AT89C55WD-24AU AT89C55WD-24JU AT89C55WD-24PU AT89C55WD-33AU AT89C55WD-33JU AT89C55WD-33PU Package Type AT89C55WD Package Operation Range 44A ...
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... This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. 2325 Orchard Parkway San Jose, CA 95131 R AT89C55WD TITLE 44A, 44-lead Body Size, 1 ...
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... Lead coplanarity is 0.004" (0.102 mm) maximum. 2325 Orchard Parkway San Jose, CA 95131 R 1921D–MICRO–6/08 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER TITLE 44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC) AT89C55WD 0.318(0.0125) 0.191(0.0075) D2/ COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX A 4.191 – ...
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... PDIP A SEATING PLANE Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). 2325 Orchard Parkway San Jose, CA 95131 R AT89C55WD 34 D PIN 0º ~ 15º REF eB TITLE 40P6, 40-lead (0.600" ...
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... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...