PIC18LF2410T-I/SO Microchip Technology, PIC18LF2410T-I/SO Datasheet - Page 109

IC MCU FLASH 8KX16 28SOIC

PIC18LF2410T-I/SO

Manufacturer Part Number
PIC18LF2410T-I/SO
Description
IC MCU FLASH 8KX16 28SOIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18LF2410T-I/SO

Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
TABLE 9-9:
TABLE 9-10:
© 2009 Microchip Technology Inc.
PORTE
LATE
TRISE
ADCON1
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE.
Note 1:
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
Legend:
Note 1:
MCLR/V
Name
(2)
2:
2:
Pin
PP
/RE3
Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0).
RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are
implemented only when PORTE is implemented (i.e., 40/44-pin devices).
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
RE3 is available on both 28-pin and 40/44-pin devices. All other PORTE pins are only implemented on 40/44-pin
devices.
RE3 does not have a corresponding TRIS bit to control data direction.
(1)
Bit 7
IBF
PORTE I/O SUMMARY
SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Function
MCLR
RE0
AN5
RE1
AN6
RE2
AN7
RE3
WR
V
RD
CS
PP
Bit 6
OBF
Setting
TRIS
0
1
1
1
0
1
1
1
0
1
1
1
(2)
VCFG1
IBOV
Bit 5
I/O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
Type
ANA
ANA
ANA
ANA
DIG
TTL
DIG
TTL
DIG
TTL
I/O
ST
ST
ST
ST
ST
PSPMODE
VCFG0
Bit 4
LATE<0> data output; not affected by analog input.
PORTE<0> data input; disabled when analog input enabled.
PSP read enable input (PSP enabled).
A/D input channel 5; default input configuration on POR.
LATE<1> data output; not affected by analog input.
PORTE<1> data input; disabled when analog input enabled.
PSP write enable input (PSP enabled).
A/D input channel 6; default input configuration on POR.
LATE<2> data output; not affected by analog input.
PORTE<2> data input; disabled when analog input enabled.
PSP write enable input (PSP enabled).
A/D input channel 7; default input configuration on POR.
External Master Clear input; enabled when MCLRE Configuration bit is
set.
High-voltage detection; used for ICSP™ mode entry detection. Always
available, regardless of pin mode.
PORTE<3> data input; enabled when MCLRE Configuration bit is
clear.
RE3
PCFG3
Bit 3
(1,2)
PIC18F2X1X/4X1X
LATE Data Output Register
TRISE2
PCFG2
Bit 2
RE2
Description
TRISE1
PCFG1
Bit 1
RE1
TRISE0
PCFG0
Bit 0
DS39636D-page 111
RE0
on page
Values
Reset
54
54
54
53

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