PIC18LF2410T-I/SO Microchip Technology, PIC18LF2410T-I/SO Datasheet - Page 132

IC MCU FLASH 8KX16 28SOIC

PIC18LF2410T-I/SO

Manufacturer Part Number
PIC18LF2410T-I/SO
Description
IC MCU FLASH 8KX16 28SOIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18LF2410T-I/SO

Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
PIC18F2X1X/4X1X
14.3
In Compare mode, the 16-bit CCPRx register value is
constantly compared against either the TMR1 or TMR3
register pair value. When a match occurs, the CCPx pin
can be:
• driven high
• driven low
• toggled (high-to-low or low-to-high)
• remain unchanged (that is, reflects the state of the
The action on the pin is based on the value of the mode
select bits (CCPxM3:CCPxM0). At the same time, the
interrupt flag bit CCPxIF is set.
14.3.1
The user must configure the CCPx pin as an output by
clearing the appropriate TRIS bit.
FIGURE 14-2:
DS39636D-page 134
I/O latch)
Note:
Compare Mode
CCP PIN CONFIGURATION
Clearing the CCP2CON register will force
the RB3 or RC1 compare output latch
(depending on device configuration) to the
default low level. This is not the PORTB or
PORTC I/O data latch.
0
1
CCPR2H
CCPR1H
COMPARE MODE OPERATION BLOCK DIAGRAM
TMR1H
TMR3H
T3CCP1
Comparator
Comparator
CCPR2L
CCPR1L
TMR1L
TMR3L
Compare
Compare
Match
Match
0
1
Set CCP1IF
T3CCP2
Set CCP2IF
(Timer1/Timer3 Reset, A/D Trigger)
(Timer1/Timer3 Reset)
Special Event Trigger
14.3.2
Timer1 and/or Timer3 must be running in Timer mode
or Synchronized Counter mode if the CCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.
14.3.3
When the Generate Software Interrupt mode is chosen
(CCPxM3:CCPxM0 = 1010), the corresponding CCPx
pin is not affected. Only a CCP interrupt is generated,
if enabled and the CCPxIE bit is set.
14.3.4
Both CCP modules are equipped with a special event
trigger. This is an internal hardware signal generated
in Compare mode to trigger actions by other modules.
The special event trigger is enabled by selecting the
Compare
(CCPxM3:CCPxM0 = 1011).
For either CCP module, the special event trigger resets
the timer register pair for whichever timer resource is
currently assigned as the module’s time base. This
allows the CCPRx registers to serve as a programma-
ble period register for either timer.
The special event trigger for CCP2 can also start an A/D
conversion. In order to do this, the A/D converter must
already be enabled.
Special Event Trigger
CCP1CON<3:0>
CCP2CON<3:0>
Output
Output
Logic
4
Logic
4
TIMER1/TIMER3 MODE SELECTION
SOFTWARE INTERRUPT MODE
SPECIAL EVENT TRIGGER
Special
S
R
S
R
Q
Q
© 2009 Microchip Technology Inc.
Event
Output Enable
Output Enable
TRIS
TRIS
Trigger
CCP1 pin
CCP2 pin
mode

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