PIC18LF2410T-I/SO Microchip Technology, PIC18LF2410T-I/SO Datasheet - Page 274

IC MCU FLASH 8KX16 28SOIC

PIC18LF2410T-I/SO

Manufacturer Part Number
PIC18LF2410T-I/SO
Description
IC MCU FLASH 8KX16 28SOIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18LF2410T-I/SO

Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
PIC18F2X1X/4X1X
COMF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39636D-page 276
Q Cycle Activity:
Before Instruction
After Instruction
Decode
REG
REG
W
Q1
=
=
=
register ‘f’
Complement f
COMF
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
N, Z
The contents of register ‘f’ are
complemented. If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 23.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1
COMF
( f )
Read
0001
Q2
13h
13h
ECh
→ dest
f {,d {,a}}
11da
REG, 0, 0
Process
Data
Q3
ffff
destination
Write to
Q4
ffff
CPFSEQ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
PC Address
W
REG
If REG
If REG
No
No
No
Q1
Q1
Q1
PC
PC
register ‘f’
operation
operation
operation
Compare f with W, Skip if f = W
CPFSEQ
0 ≤ f ≤ 255
a ∈ [0,1]
(f) – (W),
skip if (f) = (W)
(unsigned comparison)
None
Compares the contents of data memory
location ‘f’ to the contents of W by
performing an unsigned subtraction.
If ‘f’ = W, then the fetched instruction is
discarded and a NOP is executed
instead, making this a two-cycle
instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 23.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1(2)
Note: 3 cycles if skip and followed
HERE
NEQUAL
EQUAL
Read
0110
No
No
No
Q2
Q2
Q2
=
=
=
=
=
=
© 2009 Microchip Technology Inc.
by a 2-word instruction.
HERE
?
?
W;
Address (EQUAL)
W;
Address (NEQUAL)
f {,a}
CPFSEQ REG, 0
:
:
001a
operation
operation
operation
Process
Data
No
No
No
Q3
Q3
Q3
ffff
operation
operation
operation
operation
No
No
No
No
Q4
Q4
Q4
ffff

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